# A Zero Input Current Ripple ZVS/ZCS Boost Converter with Boundary-Mode Control

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## Abstract

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## 1. Introduction

## 2. Circuit Topology and Operation Principle

#### 2.1. Configuration of the Proposed Converter

_{RM}and S'

_{RM}, a RM inductor L

_{RM}, and a blocking capacitor C

_{B}.

_{s}is the sum of inductor current i

_{L}and the RM inductor current i

_{RM}. Also, due to the mirror control signals, when switches S and S

_{RM}are turned on i

_{L}will be increased generating a linearly increasing ripple current as shown in Figure 2a for 0 < t <dT

_{s}. At the same time, switch S'

_{RM}is turned off, and current i

_{RM}will decrease generating a linearly decreasing ripple current as shown in Figure 2b for 0 < t < dT

_{s}. Hence, with proper design a zero input ripple effect can be achieved as shown in Figure 2c for 0 < t < dT

_{s}. Similarly, the same ripple canceling effect can be achieved for distinct.

**Figure 2.**Steady-state current waveforms of the proposed converter (

**a**) inductor current i

_{L}; (

**b**) RM (Ripple Mirror) inductor current i

_{LRM}and (

**c**) input current i

_{s}.

#### 2.2. Operation Principle of the Proposed Converter with Boundary-Mode Control Strategy

_{L}and R

_{C}, R

_{RM}and R

_{CB}are ESRs of the corresponding inductors and capacitors. In addition, assuming that the power flow is unidirectional, one can replace MOSFET S' with a simple diode while the corresponding control circuit can be ignored. The gating signals as well as the voltage and current waveforms of the key components are shown in Figure 3b. From it, one can see that the gate signals of the ripple mirror circuit are the same as that of the conventional boost converter. The operation principle of the proposed converter can be analyzed and described mode by mode under assumptions: (1) all components are assumed to be ideal components except capacitors and inductors; (2) the proposed converter is operated under boundary-mode control, and is in the steady-state.

**Figure 3.**(

**a**) The equivalent circuit of the corresponding power circuit, and (

**b**) the gate signals and key voltage and current waveforms of the proposed converter.

#### 2.2.1. Mode 1: t_{0} ≤ t ≤ t_{1} = dT_{s}

_{0}, the main switch S and the ripple mirror switch S

_{RM}are turned on and the complementary ripple mirror switch S'

_{RM}is turned off. In this mode, source energy of the ideal voltage source V

_{s}is stored in the main inductor L and the energy stored in the capacitor C is discharged to the output resistor R. In the time interval [t

_{0}, t

_{1}], the ripple mirror inductor is reversed biased by the voltage V

_{CB}+ V

_{o}− V

_{s}. Hence, one can see from Figure 3b that i

_{RM}decreases from a positive value to a negative value. In other words, the loop current flow directions for intervals [t

_{0}, t

_{1}'] and [t

_{1}', t

_{1}] are different. This explains why the proposed ripple mirror circuit requires an active switch S

_{RM}to achieve bidirectional current flow capability. Also from Figure 4, one can see clearly that the ripple mirror current i

_{RM}can be designed to cancel the ripple of the main inductor current i

_{L}to achieve constant input current i

_{s}. Mode 1 ends when t = dT

_{s}= t

_{1}and the main switch S as well as the ripple mirror switch S

_{RM}is turned off.

_{S}(t) = i

_{L}(t) + i

_{RM}(t)

#### 2.2.2. Mode 2: t_{1} ≤ t ≤ t_{2} = T_{s}

_{1}, the complementary ripple mirror switch S'

_{RM}is turned on, and the main switch S and the ripple mirror switch S

_{RM}are turned off. The energy of the main inductor L is discharged to the output resistor R and the capacitor C in this mode. In the time interval between t

_{1}and t

_{2}, the ripple mirror inductor is forward biased by the input voltage. Hence, one can see from Figure 3b that i

_{RM}increases from a negative value to a positive value. In other words, the loop current flow directions for intervals [t

_{1}, t

_{2}'] and [t

_{2}', t

_{2}] are different. Similarly, one can observe from Figure 3b that the ripple mirror current i

_{LRM}can be designed to cancel the ripple of the main inductor current i

_{L}to achieve constant input current i

_{s}which is the sum of inductor current i

_{L}and ripple mirror inductor current i

_{RM}. Mode 2 ends when t = T

_{s}= t

_{2}and the main inductor current i

_{L}reaches zero. The complementary ripple mirror switch S'

_{RM}is turned off and the main switch S as well as the ripple mirror switch S

_{RM}is turned on at the end of Mode 2.

_{s}(t) = i

_{L}(t) + i

_{RM}(t)

#### 2.3. Steady-State Analysis the Proposed Converter

_{RM}

_{s}= I

_{L}+ I

_{RM}

_{C}is much smaller than the load resistance R (R >> R

_{C}), Equations (13)–(18) can be simplified further as shown in Equations (19)–(24), and the equivalent circuit of the DC model can be expressed as shown in Figure 6. It can be observed that the blocking capacitor C

_{B}blocks the DC current from the primary side of the upper DC transformer. Therefore, the ripple mirror circuit does not process real power, and the RM circuit does not induce much power dissipation:

_{s}= R

_{L}I

_{L}+ (1 − D)V

_{C}

_{s}= DV

_{C}+ DV

_{CB}

_{RM}

_{s}= I

_{L}

_{o}= V

_{C}

_{C}, Equation (25) can be simplified further as shown in Equation (26):

_{C}into Equation (14), the voltage across the blocking capacitor V

_{CB}, can be expressed in terms of V

_{s}as follows:

_{L}is too small to be neglected, with the same approximation, Equation (27) can be simplified further as:

_{s}can be derived from Equation (15) by substituting V

_{o}with Equation (25) as follows:

_{C}, Equation (29) can be simplified further as shown in Equation (30):

## 3. Analysis, Design and Control Strategy of Proposed Topology

#### 3.1. Analysis of the Boost Converter

_{s}can be regarded as a pure DC value. The steady-state main inductor current I

_{L}equals the sum of the inductor current i

_{L}and the ripple mirror inductor current i

_{RM}. Thus, one can derive the relationship between the main inductor L and the ripple mirror inductor L

_{RM}by the sum of di

_{L}/dt and di

_{RM}/dt from the circuit Equations (1) and (2), allow the result to be zero to achieve the following equation:

_{RM}is dependent upon the voltage across ESRs of the inductors, namely R

_{L}and R

_{RM}, and the designed duty ratio D

_{dr}. Furthermore, if the designed duty ratio D

_{dr}is over than 0.5, the inductance of the ripple mirror inductor L

_{RM}will be smaller than that of the main inductor L. The input current ripple, Δi

_{s}of the proposed converter can be derived as follows:

_{dr}. When D

_{dr}equals d and when assuming R

_{L}× I

_{L}equals zero, the peak to peak input current ripple equals zero. Hence, one can design the zero input current ripple operating point at the desired point. To further understand, a converter prototype with 48 V input, 200 V/200 W output, and switching frequency of 20 kHz specifications, is used to illustrate it, where the resistance of ESR of the is equal to 0.3 Ω and resistance of the output resistor R is equal to 200 Ω. The dissipation term R

_{L}I

_{L}/V

_{s}of the system is about 0.025. Substituting the per unit values of the input current ripple Δi

_{s}, the input voltage V

_{s}, the operation period T

_{s}, and the inductance of the main inductor L into Equation (32) and let the design operating point D

_{dr}be 0.75, one can obtain the following result:

_{s}| = |Δi

_{L}+ Δi

_{RM}| = |−2.925 + 3.925d|

_{s}|, versus duty ratio d with three different techniques. The proposed converter has a smaller input current ripple as compared with the two-phase interleaving control and the conventional boost converter when the duty ratio d is over 0.67. A better view of the ripple canceling capability around the duty ratio d of 0.75 is shown in Figure 7b. It can be seen that the proposed ripple mirror circuit technique possesses a much better ripple canceling capability than others around the designed operating point. Furthermore, unlike the fixed ripple canceling capability curve of the two-phase interleaving control, the proposed ripple mirror circuit shows a much better flexibility of being able to locate the zero input current ripple operating point dependent upon different designs. That means the |Δi

_{s}| curve of the entire converter can be moved to the left or to the right side depending on the design.

**Figure 7.**The absolute value of the input current ripple, |Δi

_{s}|, versus the duty ratio d with different techniques. (

**a**) With full range of duty ratio d and (

**b**) around the duty ratio d = 0.75.

#### 3.2. Design Considerations of Main Components for the Boost Converter

_{b}, to avoid overheating of the component, the product of the current stress and the on-resistance of the power MOSFET should be about 50% lower than the power dissipation limit for the power MOSFET S and the current stress of the power diode should be 50% lower than the forward current limit for the diode D

_{b}.

#### 3.3. Design Considerations of Main Components for the Ripple Mirror Circuit

_{RM}can be found from Equation (31) as follows:

_{B}can be found from Equation (27) as follows:

_{B}and ripple mirror inductor L

_{RM}. For the power MOSFETs of the ripple mirror circuit, namely S

_{RM}and S'

_{RM}, the current stress and the voltage stress are about a half times large than the boost converter power MOSFET S. However, because of the switching loss caused by the hard switching, the avalanche capability is much more important to these power MOSFETs. Thus, one can apply smaller gate resistor and a high speed MOSFET to lessen the crossover region of the drain to source voltage and current, which may also have better synchronization with the power MOSFET S of the boost converter.

#### 3.4. Control Strategy Realization of the Proposed Converter

_{CT}. In other words, the MOSFETs turns on when the voltage across the inductor V

_{CT}crosses the zero from negative to positive. However, the turn-off of the MOSFETs is similar to that of an average current mode control. Note that the starter will be bypassed either after the boost converter is starting up or when the switching frequency f

_{sw}is over 15 kHz.

_{b}of the proposed converter can be achieved naturally. The soft-switching capability can enhance the conversion efficiency by lessening both the switching loss and the reverse recovery loss. Third, the size of the main inductor L can be made smaller than that of the CCM control and contribute to the reducing of conduction loss as well. Hence, it is seen that the boundary-mode control is especially suitable for the proposed converter where not only the on-time can be fixed but also many additional advantages mentioned above can be fully utilized.

## 4. Experimental Results

Specifications | Values |
---|---|

Input Voltage | 48 V |

Output Voltage | 200 V |

Output Voltage Ripple | ≤0.1% |

Rated Output Power | 200 W |

Rated Switching Frequency | 20 kHz |

**Figure 10.**Experimental prototype of the proposed converter: (

**a**) the circuit schematic; (

**b**) top side view and (

**c**) bottom side view.

_{GS}waveforms of the MOSFETs, among the main switch S, the RM switch S

_{RM}, and the complementary RM switch S'

_{RM}, are shown in Figure 12. From Figure 12a and Figure 12b, it can be found that the switching frequency f

_{sw}, under a full load condition, is merely half of the under half load condition. Also, with the cursor tools of the LeCroy wave runner, one can obtain the on-time delay of the MOSFETs of the RM circuit as about 562 ns and the off-time delay of the MOSFETs of the RM circuit as about 166ns compared with the v

_{GS}waveform of the main switch S.

**Figure 11.**The output voltage waveform of the proposed converter under full load condition (50 ms/div).

**Figure 12.**Gate signal waveforms of the proposed converter under (

**a**) half, and (

**b**) full load conditions (50 ms/div).

**Figure 13.**Current waveforms of the proposed converter under (

**a**) half, and (

**b**) full load conditions (50 ms/div).

_{b}being turned off naturally with zero current switching as shown in Figure 17. Both the soft switching on the main switch S and the power diode D

_{b}may lessen the switching loss of the proposed converter. Hence, the proposed converter can have better efficiency.

**Figure 17.**The turn-off ZCS waveform of the power diode D

_{b}under full load conditions (20 ms/div).

Load Conditions | Without RM | With RM |
---|---|---|

25% load | 95.00% | 94.89% |

50% load | 95.67% | 95.57% |

60% load | 95.42% | 95.39% |

70% load | 95.07% | 95.05% |

80% load | 94.76% | 94.72% |

90% load | 94.50% | 94.43% |

Rated load | 93.94% | 93.90% |

**Figure 18.**Efficiency comparison for the constructed experiment prototype with and without the proposed RM circuit.

## 5. Conclusions

## Acknowledgments

## Author Contributions

## Conflicts of Interest

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## Share and Cite

**MDPI and ACS Style**

Lai, C.-M.; Yang, M.-J.; Liang, S.-K.
A Zero Input Current Ripple ZVS/ZCS Boost Converter with Boundary-Mode Control. *Energies* **2014**, *7*, 6765-6782.
https://doi.org/10.3390/en7106765

**AMA Style**

Lai C-M, Yang M-J, Liang S-K.
A Zero Input Current Ripple ZVS/ZCS Boost Converter with Boundary-Mode Control. *Energies*. 2014; 7(10):6765-6782.
https://doi.org/10.3390/en7106765

**Chicago/Turabian Style**

Lai, Ching-Ming, Ming-Ji Yang, and Shih-Kun Liang.
2014. "A Zero Input Current Ripple ZVS/ZCS Boost Converter with Boundary-Mode Control" *Energies* 7, no. 10: 6765-6782.
https://doi.org/10.3390/en7106765