Current Sharing Control of an Interleaved Three-Phase Series-Resonant Converter with Phase Shift Modulation

Abstract

Recently, three-phase series-resonant converters (SRCs) have been proposed for high power applications. Three-phase SRCs can achieve zero-voltage-switching (ZVS) of the primary power switches and regulate the output voltage by pulse-frequency modulation. The interleaving technique is also a conventional method for DC-DC converters to achieve a high power level, reducing the output voltage ripples due to operating out of phase at the same frequency between the two converters. However, an interleaved three-phase SRC cannot easily synchronize switching instants between the two modules due to the component tolerances of circuits. In the proposed control method, phase shift modulation (PSM) is used to solve the output current imbalance caused by component tolerances. The power switches of the converter can also maintain synchronizing switching instants between the two modules. Therefore, the lower output voltage ripple can be achieved. A detailed analysis and design of this new control method for interleaved three-phase SRCs are described. Finally, prototype converters with a 2.4 kW total output were built and successfully tested to verify the feasibility of the current sharing modulation.

1. Introduction

In the past decades, the resonant converter has been widely used in many applications such as laptop adapters, server power supply units and battery chargers. The reason for its wide use is its many advantages such as zero-voltage-switching (ZVS) at primary-side power switches, zero-current-switching at secondary-side rectifiers and a high conversion efficiency. However, the resonant converter is not suitable in high power and large output current applications because the secondary-side rectifiers do not use stored energy inductors such as an LLC resonant converter; thus, the secondary-side current is larger compared with other DC-DC converters. Therefore, many output capacitors are needed to parallel with the output side to satisfy the rated ripple voltage. The interleaved technique has been widely used for the high output power level. This technique can divide load current into each module and reduce output current ripple and voltage ripple. However, the conventional interleaving control for pulse-width modulation (PWM) cannot be directly applied to the resonant converters because they use pulse-frequency modulation (PFM) to regulate output voltage and the operational frequency of each module must be synchronized for the interleaved operations. However, when component tolerance occurs between the two modules, different gain characteristics will arise at a synchronized operational frequency. Thus, it will lose the advantage of interleaving control and will cause large output voltage ripples. Many studies have proposed an interleaving method of resonant converters. The influence of parameter mismatch of a resonant circuit and the improvement of current balancing are discussed in [1,2,3,4,5,6,7,8,9,10,11]. In [12], the output voltage of power-factor correction (PFC) was used to compensate for the parameter of the resonant circuit mismatch between the two modules. The PFC had to be placed in front of each module of the resonant converters. In [13], the switch-controlled capacitor method was used to control output current sharing on each module. However, extra power switches had to be added, increasing the cost and volume of the converter. In [14], the current sharing method needed an additional power stage to regulate the output voltage but this method caused a lower conversion efficiency because the additional power stage caused other power losses. Three-phase series-resonant converters (SRCs) have been proposed for high power level applications. In comparison with other approaches, these SRCs can achieve better power loss distributions, excellent thermal distribution and much lower output voltage ripples. The three-phase SRC, three-phase LCC resonant converter and three-phase LLC resonant converter were proposed in [15,16,17,18]. These studies discussed the principle of operations about three-phase resonant converters. Similar to ordinary single-phase resonant converters, the output voltage of the three-phase SRC is regulated by a PFM control so that the interleaving technique is also difficult to use on three-phase SRCs.

In this paper, an interleaved structure of the three-phase SRC is proposed. In the proposed method, the three-phase SRC operates at a PFM control for regulated output voltage. Moreover, the influence of circuit parameter mismatch is compensated by a PSM control to achieve current balance. The proposed method does not require any auxiliary circuits and switching instants between modules can achieve synchronization. Section 2 describes the operation principle of an interleaved structure of a three-phase SRC with PSM. Section 3 provides an analysis and design for this proposed method. Section 4 demonstrates the experimental results of a 2.4 kW prototype. Section 5 concludes the paper.

2. Operation Principle of a Three-Phase Series-Resonant Converters (SRC)

The three-phase SRC schematic is shown in Figure 1. The circuit on the primary-side consists of three switch legs and three resonant tanks. The control signal is shown in Figure 2. Switches S₁–S₆ are controlled at a 0.5 duty ratio and three legs exhibit phase shifts at 0°, 120° and 240°, respectively. The secondary-side transformers consist of three switch legs; switches S_a–S_f are also controlled at a 0.5 duty ratio and three legs exhibit phase shifts at 120° and 240°. The phase shift degree φ between the primary-side and secondary-side is for output power control. Therefore, switches S₁ and S_a represent phase shift degree φ, as do switches S₃ and S_c as well as S₅ and S_e.

Figure 3 shows the key waveforms of the three-phase SRC in one switching cycle. A complete half positive switching cycle comprises five states because the inductor current can be i_Lrα = i_Lrβ = i_Lrγ with phase shifts of 120° and 240°, which can only use one phase to analyze simplified calculations. The basic idea about the three-phase SRC has been discussed in many studies [19,20]. The resonant frequency f_r and the power transfer of a three-phase SRC has been expressed as:

$$f_r=\frac{1}{2\mathsf{\pi }\sqrt{L_r\times C_r}}.$$

(1)

$$P_o=3\cdot P_{phase\alpha }=\frac{n{V}_o{V}_{in}(\phi -30°)}{360f_{sw}{L}_r}.$$

(2)

Equation (2) can explain the elements that can use the phase shift degree φ and switching frequency f_sw to regulate output power P_o. Figure 4 depicts the relationship between the phase shift degree φ and output power P_o. The phase shift degree φ must be limited between 30° and 60° to transform the power into the output load side. In addition, the specifications in Figure 5 are used except for frequency f_sw, which is defined as 125 kHz. To explain the relationship among the voltage gain, phase shift degree φ and switching frequency f_sw,the voltage gain is defined as nV_o/V_in and Equation (3) can be derived from Equation (2) where n is the turn ratio of the primary-side to the secondary-side of the transformers, assuming a voltage gain nV_o/V_in = 0.56, V_in = 400 V_DC, V_o = 48 V_DC and I_o = 25 A. Therefore, R_L is equal to 1.92 Ω, the resonant inductor L_r is 18 μH, the resonant capacitor C_r is 141 nF and the switching frequency f_sw is limited between 100 and 200 kHz to normalize the frequency f_sw. The gain curve diagram is shown in Figure 5. The frequency f_sw is normalized as f_n by dividing the resonant frequency f_r, which is 100 kHz. As the color changes from blue to yellow, this indicates that the gain is from low to high. The output voltage can be regulated by the phase shift degree φ and normalized frequency f_n. Furthermore, when increasing the phase shift degree φ or decreasing the normalized frequency f_n, the voltage gain obviously rises.

$$Gain=\frac{n{V}_o}{V_{in}}=\frac{n^2{R}_L(\phi -30°)}{360f_{sw}{L}_r}$$

(3)

where R_L = V_o/I_o and n = N_p/N_s.

3. Principle of an Interleaved Three-Phase SRC with PSM Current Sharing Control

3.1. Design of Phase Lagging Degree and Phase Shift Degree

The interleaved three-phase SRC schematic is shown in Figure 6. The SRC consists of two modules of a three-phase SRC, which are divided into modules A and B. C_r is the resonant capacitor. L_rA is the resonant inductor of module A and L_rB is the resonant inductor of module B. In ideal conditions, the L_rA and L_rB have equivalent values. The key waveforms of the interleaved three-phase SRC are shown in Figure 7. The phase shift degree φ_A is module A between the primary- and secondary-sides. The phase shift degree φ_B is module B between the primary- and secondary-sides. The phase shift degrees φ_A and φ_B are separately independent to control modules A and B for output power, respectively. Moreover, to achieve a minimum total output ripple current I_{o_pp}, module B control signals will be lagging the φ_AB degree of module A. The phase lagging degree φ_AB can be calculated as

$$\begin{array}{l}{i}_{o\_pp}\left({\phi }_{AB}\right)=\hfill \\ \{\begin{array}{c}\frac{\pi I_o}{3}\left[2\cos (\frac{{\phi }_{AB}}{2})-\sin ({\phi }_{AB}+60°)-\frac{\sqrt{3}}{2}\right] \mathrm{for} 0°\le {\phi }_{AB}\le 30° \hfill \\ \frac{\pi I_o}{3}\left[2\sin (\frac{{\phi }_{AB}}{2}+60°)+\sin ({\phi }_{AB}-120°)-\frac{\sqrt{3}}{2}\right] \mathrm{for} 30°\le {\phi }_{AB}\le 60°\hfill \end{array}\hfill \end{array}.$$

(4)

$$i_{o\_pp\max }=i_{o\_pp}(0°)=i_{o\_pp}(60°)=\frac{\pi I_o}{3}\left[2-\sqrt{3}\right] .$$

(5)

Equation (4) is drawn in Figure 8, which is normalized by i_{o_ppmax}. When the phase lagging φ_AB is 30°, the converter will have a minimum total output ripple current i_{o_pp}. Therefore, module B control signals will be set to lagging module A by 30°.

3.2. Current Sharing Control of PSM

The digital control block diagram of the interleaved three-phase SRC is shown in Figure 9. To achieve output voltage stabilization and current sharing under all load ranges, the control method combines a PFM control to regulate the output voltage and a PSM control to achieve current sharing.

H_v(s) and H_i(s) contain a voltage divider resistance and RC filter transfer circuit signals to a DC value under 3.3 V for ADC inputs. The ADC sample transfers analogue values to digital values such as V_o[k], I_oA[k] and I_oB[k]. The error between the reference voltage V_ref and the sampled V_o[k] is entered into a compensator. The frequency is then controlled through a voltage-control oscillator as a PFM control. The error between reference current I_ref, which is half of the total output current, and either I_oA[k] or I_oB[k] is entered into a compensator to control the phase shift angle Δφ and as a PSM control. The initial phase angle φ_i is calculated through Equation (6) with I_ref and f_sw. Finally, 12 enhanced pulse-width modulator (ePWM) modules with desired periods and phases are used to generate the 24 signals to control the circuit.

The program is implemented by a digital signal processor (DSP), namely, TMS320F28379. The main control flow chart is shown in Figure 10. The cycled steps of the proposed modulation are shown as follows.

• To achieve the above functions, three ADC inputs are needed to convert the sampled signals into digital values after interruption.
• The same operating frequency of modules A and B are determined by the output voltage feedback with a proportional-integral (PI) controller.
• For the φ_i calculation and average current sharing control, a reference current I_ref set as half of the total output current is needed.
• φ_i is calculated through Equation (6), which is derived from Equation (2) with I_ref and f_sw.

  $${\phi }_i=30°+\frac{360f_{sw}{L}_r{I}_{ref}}{n{V}_{in}}.$$

  (6)
• I_oA and I_oB are negative feedbacks to compare I_ref with integral controllers. When output currents are balanced, Δφ and −Δφ are generated by the I-Loop compensation. Therefore, φ_A is equal to φ_i + Δφ; φ_B is equal to φ_i − Δφ.

3.3. Closed Loop Design

As the state-space averaging method can maintain an accuracy under 1/5 of f_sw [21], the simplified small-signal model of the proposed converter as shown in Figure 11 is used for the closed loop design [22]. The expressions of the small-signal value of the output current i_o can be derived by taking the partial derivative of Equation (2) with respect to f_sw and φ as follows.

$$\widetilde{i_o}=\frac{n{V}_{in}(\phi -30°)}{360f_{sw}{}^2{L}_r}\times \widetilde{f_{sw}}+\frac{n{V}_{in}}{360f_{sw}{L}_r}\times \tilde{\phi }.$$

(7)

$$\frac{\widetilde{i_o}}{\tilde{\phi }}=\frac{n{V}_{in}}{360f_{sw}{L}_r}.$$

(8)

$$\frac{\widetilde{v_o}}{\widetilde{f_{sw}}}=\frac{n{V}_{in}(\phi -30°)}{360f_{sw}{}^2{L}_r}\times \frac{R_L}{1+s{R}_L{C}_o}.$$

(9)

As the digital sample and delay cause a phase margin drop, the crossover frequency needs to be designed smaller than analog. The PI controller is designed with a crossover frequency of 5 kHz and a phase margin of 96° for output voltage stabilization and a fast load transient. The integral controllers are designed with a crossover frequency of 500 Hz and a phase margin of 91° for a current sharing feedback loop. The Bode plots of the compensated loop gain for both functions are shown in Figure 12.

3.4. Simulation Results of PSM Control

The combination of the single 1.2 kW module forming the interleaved three-phase SRC was designed and simulated for V_in = 400 V_DC, V_o = 48 V_DC and P_o = 2.4 kW and the component values and specifications are listed in

Table 1. Designed parameters of the experiment and simulation.

Parameter	Values
Input voltage	400 VDC
Output voltage	48 VDC
Total output current (single module)	50 A (25 A)
Total output power (single module)	2.4 kW (1.2 kW)
Limit of switching frequency fsw	120–130 kHz
Limit of phase shift degree φA and φB	30–40°
Lagging degree φAB	30°
Resonant inductors (LrA, LrB)	18 μH ± 10%
Voltage gain nVo/Vin	0.56
Turn ratio of transformer n = Np/Ns	14/3

. In general, 130 kHz was the maximum limit of the switching frequency f_sw for the power density and the high conversion efficiency. The phase shift degree φ_A and φ_B were limited to a maximum of 40° and the lagging degree φ_AB was set at 30° for the minimum output ripple voltage. Equation (3) shows that the voltage gain was 0.56. The equivalent output resistances of the single module R_L were 7.38 Ω at 25% load condition, 3.84 Ω at the 50% load condition and 1.92 Ω at the 100% load condition. Therefore, the resonant inductor followed Equation (1) and it could be obtained at approximately 18 μH.

Figure 13 shows the simulation results of the ideal interleaved three-phase SRC. The resonant inductors L_rA and L_rB were equal to 18 μH. When the output load from 25% increased to the full load, modules A and B showed that switching frequency f_sw changed from 130 kHz to 121 kHz and the phase shift degree φ_A and φ_B changed from 32.8° to approximately 40°. By contrast, the module cause of the imbalanced condition was the tolerance in the resonant inductor values of the converter. Generally, a 10% change in the magnetic component values could be expected, causing an imbalanced output current between modules A and B. Figure 14, Figure 15 and Figure 16 show the simulation results of the imbalanced conditions when L_rA was 20 μH and L_rB was 16 μH. Figure 12 shows 25% output power load conditions. To maintain a voltage gain at 0.56 for regulated output voltage and interleaved operation, the switching frequency f_sw of modules A and B operated at 130 kHz. The phase shift degree φ_A of module A and the phase shift degree φ_B of module B were 33.1° and 32.5°, respectively. In Figure 15, when the output load condition was at 50%, the switching frequency f_sw operated at 127 kHz, the phase shift degree φ_A of module A operated at 36.1° and the phase shift degree φ_B operated at 34.9°. Figure 14 shows the output power at full load. The switching frequency f_sw was at 121 kHz and the phase shift degree φ_A and φ_B operated at 41.7° and 39.3°, respectively.

Figure 17 shows the simulation results of the output current and output voltage ripple when the resonant inductors L_rA and L_rB were 20 and 16 μH at full load conditions, respectively. In Figure 17a, the gate signal V_gsBa lagged V_gsAa by approximately 30° so that the output ripple voltage V_oac could be decreased. By contrast, because the PSM control was disabled, the phase shift degree φ_A and the phase shift degree φ_B were the same at 40.5° so the output current I_oA and I_oB were imbalanced. In Figure 17b, the PSM control was used for the output current balance. The switching frequency was approximately 121.2 kHz, the phase shift degree φ_A was 41.8° and φ_B was 39.2°. These simulation results corresponded with those in Figure 16.

4. Experimental Results

To verify the theoretical analysis, a 2.4 kW prototype was designed and built as shown in Figure 18. Its key parameters are shown in Table 1. The component values are listed in

Table 2. Summary of components.

Component	Part Number
MOSFETs (primary-side)	IPL60R199CP
MOSFETs (secondary-side)	IPB020N08N5
Transformer core (T1~T6)	PQ-4040
Resonant inductor core (LrA, LrB)	CH330060
DSP controller	TMS320F28379

. The PQ-4040 core was used for isolation transformers T₁, T₂, T₃, T₄, T₅ and T₆, the resonant inductor core was CH330060 and the power switches were IPL60R199CP and IPB020N08N5.

Figure 19 shows the ZVS waveform measured by the primary- and secondary-side power switches at a 25% load. The power switch was turned on after the V_ds of the power switch dropped to a zero level, achieving ZVS.

Figure 20 shows the waveforms of the first bridge primary and secondary phase voltage and inductor currents at a 25% load. The phase shift degree φ_A was approximately 33° and the switching frequency was 130 kHz. Compared with Figure 13a, Figure 20 was identical to the simulation results.

Figure 21 shows typical waveforms at a single module. The resonant inductor L_rA was equal to 18 μH and had different output load conditions (6.25, 12.5, 18.75 and 25 A). The measured waveforms were the waveforms of V_gs2 and V_ds2 of the primary-side low-bridge switch S₂, the resonant inductor current i_Lrα and the V_gsb of the secondary-side switch S_b.

The values of resonant inductors L_rA and L_rB were set at different values to test imbalanced current conditions. L_rA was designed as 20 μH and L_rB was 16 μH. Figure 22 shows the output current waveforms of the two modules in parallel at a 25% load conduction. Figure 22a,b show without and with a current sharing control. When the function of the current sharing control was disabled, the current was imbalanced due to component mismatch. With a PSM control, the imbalanced current was improved. Both ripple current frequencies of i_oA and i_oB were six times larger than the switching frequency. Furthermore, with phase lagging φ_AB at 30°, the ripple current frequency of i_o was twelve times larger than the switching frequency, achieving a minimum output ripple current i_{o_pp}.

The trend of switching frequency and phase shift changing was the same as Figure 13 in that when the load was increased, the switching frequency f_sw decreased and the phase shift degree φ_A increased.

Figure 23 shows the current sharing waveforms of the two modules with the current sharing phase shift control at 50%, 75% and 100% load conditions. The output currents were balanced at different loads.

Table 3. The output current error of two modules.

Load	IoA (A)	IoB (A)	Io (A)	IError (%)
25%	6.5	6.8	13.3	2.3
50%	12	12.4	24.4	1.6
75%	17.7	18.1	35.8	1.1
100%	24.2	24.3	48.5	0.2
IError = |IoA − IoB|/Io

shows the output current error of the two modules and the current sharing error ratio was under 3%.

Figure 24 shows the phase shift waveforms of modules A and B at different load conditions. The phase lagging was approximately 30°. When the load was increased, the phase shift degree φ_A and φ_B increased and the switching frequency decreased to regulate the output voltage. In addition, the phase shift degree φ_A and φ_B operated in different degrees to balance the output current between modules A and B. The measurement results were identical to the simulation results in Figure 14, Figure 15 and Figure 16.

Figure 25 shows the output ripple voltage waveform at a 100% load and with the interleaved two modules, which achieved a minimum output ripple current i_{o_pp} to reduce the volume of the output capacitor. In addition, Figure 26 shows the result of the dynamic load from 10 A to 50 A. The overshoot and undershoot of the output voltage were about 4 V. The efficiency curve of the converter was measured with a power meter and is shown in Figure 27. The highest efficiency could reach 94.5%.

5. Conclusions

To solve the current imbalance between two modules, this paper presented the PSM control for an interleaved three-phase SRC. The component mismatch of the resonant inductor was made to verify the validity of the proposed method. Using the proposed method achieved a current sharing function and synchronized switching frequencies. Thus, the proposed method is important in decreasing the output ripple voltage and equally distributing conduction losses between modules A and B. The experimental results on a 2.4 kW prototype were recorded to verify the theoretical analysis. The results showed that the PSM control could achieve the current sharing The phase lagging of 30° could achieve the minimized output ripple voltage.