Network-on-Chip (NoC) and Related Technologies and Applications

A special issue of Micromachines (ISSN 2072-666X). This special issue belongs to the section "E:Engineering and Technology".

Deadline for manuscript submissions: closed (31 May 2023) | Viewed by 1673

Special Issue Editors

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Guest Editor
Department of Electrical and Computer Engineering, College of Engineering, Sultan Qaboos University, Al Seeb Al Khoudh SQU SEPS, Muscat OM 123, Oman
Interests: embedded systems

Special Issue Information

Dear Colleagues,

With the advent of diverse computing platforms, such as many-core CPUs, GPUs, FPGAs, and other domain-specific processors, the communication of data is becoming increasingly important and presents a great challenge. Emerging technologies for networks-on-chips (NoCs), inter-chip communication and rack-scale networks offer good opportunities to accelerate data movement and improve overall system performance. New trends in architecture, application, and technology require innovative communication designs, design approaches, and interconnection networks for the next generation of computing systems. This Special Issue will explore academic, interdisciplinary and industrial research on all topics related to NoC, chip-to-chip, and datacenter rack-scale communication technology, architecture, design methods, applications and systems. Current practices, innovations and future research on NoC, inter-chip and datacenter rack-scale networks are solicited for diverse applications, including optimization and algorithms, computer architecture, networking, circuits and systems, packaging, embedded systems, and design automation. 

Dr. Ahmed Chiheb Ammari
Dr. Mengchu Zhou
Guest Editors

Manuscript Submission Information

Manuscripts should be submitted online at by registering and logging in to this website. Once you are registered, click here to go to the submission form. Manuscripts can be submitted until the deadline. All submissions that pass pre-check are peer-reviewed. Accepted papers will be published continuously in the journal (as soon as accepted) and will be listed together on the special issue website. Research articles, review articles as well as short communications are invited. For planned papers, a title and short abstract (about 100 words) can be sent to the Editorial Office for announcement on this website.

Submitted manuscripts should not have been published previously, nor be under consideration for publication elsewhere (except conference proceedings papers). All manuscripts are thoroughly refereed through a single-blind peer-review process. A guide for authors and other relevant information for submission of manuscripts is available on the Instructions for Authors page. Micromachines is an international peer-reviewed open access monthly journal published by MDPI.

Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 2600 CHF (Swiss Francs). Submitted papers should be well formatted and use good English. Authors may use MDPI's English editing service prior to publication or during author revisions.


  • NoC architecture and implementation
  • NoC for intelligent cyber-physical systems
  • communication analysis, optimization, and verification
  • NoC at the un-core and system-level
  • novel NoC technologies
  • inter/intra-chip and rack-scale networks
  • complex system and network modeling and performance analysis
  • NoC-based system design automation
  • NoC related benchmark studies

Published Papers (1 paper)

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15 pages, 3931 KiB  
Design of GPU Network-on-Chip for Real-Time Video Super-Resolution Reconstruction
by Zhiyong Peng, Jiang Du and Yulong Qiao
Micromachines 2023, 14(5), 1055; - 16 May 2023
Viewed by 1133
Deep learning has a better output quality compared with traditional algorithms for video super-resolution (SR), but the network model needs large resources and has poor real-time performance. This paper focuses on solving the speed problem of SR; it achieves real-time SR by the [...] Read more.
Deep learning has a better output quality compared with traditional algorithms for video super-resolution (SR), but the network model needs large resources and has poor real-time performance. This paper focuses on solving the speed problem of SR; it achieves real-time SR by the collaborative design of a deep learning video SR algorithm and GPU parallel acceleration. An algorithm combining deep learning networks with a lookup table (LUT) is proposed for the video SR, which ensures both the SR effect and ease of GPU parallel acceleration. The computational efficiency of the GPU network-on-chip algorithm is improved to ensure real-time performance by three major GPU optimization strategies: storage access optimization, conditional branching function optimization, and threading optimization. Finally, the network-on-chip was implemented on a RTX 3090 GPU, and the validity of the algorithm was demonstrated through ablation experiments. In addition, SR performance is compared with existing classical algorithms based on standard datasets. The new algorithm was found to be more efficient than the SR-LUT algorithm. The average PSNR was 0.61 dB higher than the SR-LUT-V algorithm and 0.24 dB higher than the SR-LUT-S algorithm. At the same time, the speed of real video SR was tested. For a real video with a resolution of 540×540, the proposed GPU network-on-chip achieved a speed of 42 FPS. The new method is 9.1 times faster than the original SR-LUT-S fast method, which was directly imported into the GPU for processing. Full article
(This article belongs to the Special Issue Network-on-Chip (NoC) and Related Technologies and Applications)
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