Advances in Microelectronics Reliability

A special issue of Micromachines (ISSN 2072-666X). This special issue belongs to the section "A:Physics".

Deadline for manuscript submissions: 31 October 2024 | Viewed by 6472

Special Issue Editors


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Guest Editor
Department of Electrical Engineering and Electronics, Ariel University, Ariel 40700, Israel
Interests: microelectronics device reliability; microelectronic system reliability; power electrtonics using GaN transistors; SiC and GaN in power electronic systems
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Guest Editor
Microsystems Technology Laboratories (MTL) Department, Massachusetts Institute of Technology, Cambridge, MA 02142, USA
Interests: microelectronics reliability

Special Issue Information

Dear Colleagues,

Over the last few decades, our knowledge of the root cause and physical behavior of critical failure mechanisms in microelectronic devices has grown significantly. Confidence in the reliability of models has led to more aggressive design rules that have been successfully applied to the latest nanoscale technology. One result of improved reliability modeling has been accelerated performance, beyond the expectation of Moore’s Law. A consequence of more aggressive design rules has been a reduction in the weight of a single failure mechanism. Hence, in modern devices, there is no single failure mode that is more likely to occur than any other, as guaranteed by the integration of modern failure physics modeling and advanced device simulation tools in the design process. The consequence of more advanced reliability modeling tools is a new phenomenon of device failures resulting from a combination of several competing failure mechanisms. Therefore, new approaches are required for reliability modeling and prediction.

We solicit papers focusing on failure mechanisms that have a compact formula for lifetime prediction as a function of operating conditions, including voltage, current, frequency, temperature, stress, etc. In particular, we are interested to show that multiple simultaneous mechanisms can be isolated either experimentally or statistically through machine learning or AI approaches. The goal of any physics of failure study is to predict the lifetime under user determined operational conditions; hence, any mechanism that is studied requires a proper weighting of all the relevant mechanisms, leading to failure at operational conditions. This is true for deep sub-micron, nanoscale FINFETs, GaN, and SiC. The same applies for discrete power devices and fully integrated circuits. This Special Issue solicits papers to publish practical research, leading to accurate lifetime prediction by combining the effects of multiple failure and degradation mechanisms into a simple compact model.

Prof. Dr. Joseph Bernstein
Dr. Emmanuel Bender
Guest Editors

Manuscript Submission Information

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Submitted manuscripts should not have been published previously, nor be under consideration for publication elsewhere (except conference proceedings papers). All manuscripts are thoroughly refereed through a single-blind peer-review process. A guide for authors and other relevant information for submission of manuscripts is available on the Instructions for Authors page. Micromachines is an international peer-reviewed open access monthly journal published by MDPI.

Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 2600 CHF (Swiss Francs). Submitted papers should be well formatted and use good English. Authors may use MDPI's English editing service prior to publication or during author revisions.

Keywords

  • multiple mechanisms
  • reliability
  • physics of failure
  • GaN
  • SiC
  • nanoscale
  • BTI
  • FINFET
  • HCI
  • TDDB

Published Papers (5 papers)

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Research

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15 pages, 8066 KiB  
Article
A Reliability Investigation of VDMOS Transistors: Performance and Degradation Caused by Bias Temperature Stress
by Emilija Živanović, Sandra Veljković, Nikola Mitrović, Igor Jovanović, Snežana Djorić-Veljković, Albena Paskaleva, Dencho Spassov and Danijel Danković
Micromachines 2024, 15(4), 503; https://doi.org/10.3390/mi15040503 - 5 Apr 2024
Viewed by 690
Abstract
This study aimed to comprehensively understand the performance and degradation of both p- and n-channel vertical double diffused MOS (VDMOS) transistors under bias temperature stress. Conducted experimental investigations involved various stress conditions and annealing processes to analyze the impacts of BT stress on [...] Read more.
This study aimed to comprehensively understand the performance and degradation of both p- and n-channel vertical double diffused MOS (VDMOS) transistors under bias temperature stress. Conducted experimental investigations involved various stress conditions and annealing processes to analyze the impacts of BT stress on the formation of oxide trapped charge and interface traps, leading to threshold voltage shifts. Findings revealed meaningful threshold voltage shifts in both PMOS and NMOS devices due to stresses, and the subsequent annealing process was analyzed in detail. The study also examined the influence of stress history on self-heating behavior under real operating conditions. Additionally, the study elucidated the complex correlation between stress-induced degradation and device reliability. The insights contribute to optimizing the performance and permanence of VDMOS transistors in practical applications, advancing semiconductor technology. This study underscored the importance of considering stress-induced effects on device reliability and performance in the design and application of VDMOS transistors. Full article
(This article belongs to the Special Issue Advances in Microelectronics Reliability)
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24 pages, 14704 KiB  
Article
Degradation Measurement and Modelling under Ageing in a 16 nm FinFET FPGA
by Justin Sobas and François Marc
Micromachines 2024, 15(1), 19; https://doi.org/10.3390/mi15010019 - 22 Dec 2023
Viewed by 766
Abstract
Most of the latest generation of integrated circuits use FinFET transistors for their performance, but what about their reliability? Does the architectural evolution from planar MOSFET to FinFET transistor have any effect on the integrated circuit reliability? In this article, we present a [...] Read more.
Most of the latest generation of integrated circuits use FinFET transistors for their performance, but what about their reliability? Does the architectural evolution from planar MOSFET to FinFET transistor have any effect on the integrated circuit reliability? In this article, we present a test bench we have developed to age and measure the degradation of 5103 ring oscillators (ROs) implemented in nine FPGAs with 16nm FinFET under different temperature and voltage conditions (VnomVstress1.3Vnom and 25°CTstress115°C) close to operational conditions in order to predict reliability regarding degradation mechanisms at the transistor scale (BTI, HCI and TDDB) as realistically as possible. By comparing our initial RO measurements and the data extracted from Vivado, we will show that the performance of the nine FPGAs is between 50% and 70% of the best performance expected by Vivado. After 8000 h of ageing, we will see that the relative degradations of the RO are a maximum of 1%, which is a first indicator proving the FPGAs’ good reliability. By comparing our results with similar studies on 28 nm MOSFET FPGAs, we will reveal that 16 nm FinFET FPGAs are more reliable. To be implemented in an FPGA, an RO uses logic resources (LUT) and routing resources. We will show that degradation in the two types of resources is different. For this reason, we will present a method for separating degradations in logical and routing resources based on RO degradation measures. Finally, we will model rising and falling edge propagation time degradations in an FPGA as a function of time, temperature, voltage, signal duty cycle and resources used in the FPGA. Full article
(This article belongs to the Special Issue Advances in Microelectronics Reliability)
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17 pages, 15441 KiB  
Article
Temperature Cycle Reliability Analysis of an FBAR Filter-Bonded Ceramic Package
by Wenchao Tian, Wenbin Li, Shuaiqi Zhang, Liming Zhou and Heng Wang
Micromachines 2023, 14(11), 2132; https://doi.org/10.3390/mi14112132 - 20 Nov 2023
Viewed by 1017
Abstract
On the background that the operating frequency of electronic devices tends to the radio frequency (RF) segment, a film bulk acoustic resonator (FBAR) filter is widely used in communication and military fields because of its advantages of high upper frequency, ample power capacity, [...] Read more.
On the background that the operating frequency of electronic devices tends to the radio frequency (RF) segment, a film bulk acoustic resonator (FBAR) filter is widely used in communication and military fields because of its advantages of high upper frequency, ample power capacity, small size, and low cost. However, the complex and harsh working environment puts higher requirements for packaging FBAR filters. Based on the Anand constitutive equation, the stress–strain response of the bonded ceramic package was studied by the finite element method for the FBAR filter-bonded ceramic package, and the thermal fatigue life of the device was predicted. We developed solder models with various spillage morphologies based on the random generation technique to examine the impact of spillage on device temperature reliability. The following are the primary conclusions: (1) Solder undergoes periodic deformation, stress, and strain changes throughout the cycle. (2) The corner of the contact surface between the chip and the solder layer has the largest stress at the end of the cycle, measuring 19.377 MPa. (3) The Engelmaier model predicts that the gadget will have a thermal fatigue life of 1928.67 h. (4) Expanding the layered solder area caused by any solder overflow mode may shorten the device’s thermal fatigue life. The thermal fatigue life of a completely spilled solder is higher than that of a partially spilled solder. Full article
(This article belongs to the Special Issue Advances in Microelectronics Reliability)
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Review

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24 pages, 12282 KiB  
Review
Research on the Reliability of Advanced Packaging under Multi-Field Coupling: A Review
by Yongkun Wang, Haozheng Liu, Linghua Huo, Haobin Li, Wenchao Tian, Haoyue Ji and Si Chen
Micromachines 2024, 15(4), 422; https://doi.org/10.3390/mi15040422 - 22 Mar 2024
Viewed by 1831
Abstract
With the advancement of Moore’s Law reaching its limits, advanced packaging technologies represented by Flip Chip (FC), Wafer-Level Packaging (WLP), System in Package (SiP), and 3D packaging have received significant attention. While advanced packaging has made breakthroughs in achieving high performance, miniaturization, and [...] Read more.
With the advancement of Moore’s Law reaching its limits, advanced packaging technologies represented by Flip Chip (FC), Wafer-Level Packaging (WLP), System in Package (SiP), and 3D packaging have received significant attention. While advanced packaging has made breakthroughs in achieving high performance, miniaturization, and low cost, the smaller thermal space and higher power density have created complex physical fields such as electricity, heat, and stress. The packaging interconnects responsible for electrical transmission are prone to serious reliability issues, leading to the device’s failure. Therefore, conducting multi-field coupling research on the reliability of advanced packaging interconnects is necessary. The development of packaging and the characteristics of advanced packaging are reviewed. The reliability issues of advanced packaging under thermal, electrical, and electromagnetic fields are discussed, as well as the methods and current research of multi-field coupling in advanced packaging. Finally, the prospect of the multi-field coupling reliability of advanced packaging is summarized to provide references for the reliability research of advanced packaging. Full article
(This article belongs to the Special Issue Advances in Microelectronics Reliability)
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22 pages, 1988 KiB  
Review
Modern Trends in Microelectronics Packaging Reliability Testing
by Emmanuel Bender, Joseph B. Bernstein and Duane S. Boning
Micromachines 2024, 15(3), 398; https://doi.org/10.3390/mi15030398 - 15 Mar 2024
Viewed by 1584
Abstract
In this review, recent trends in microelectronics packaging reliability are summarized. We review the technology from early packaging concepts, including wire bond and BGA, to advanced techniques used in HI schemes such as 3D stacking, interposers, fan-out packaging, and more recently developed silicon [...] Read more.
In this review, recent trends in microelectronics packaging reliability are summarized. We review the technology from early packaging concepts, including wire bond and BGA, to advanced techniques used in HI schemes such as 3D stacking, interposers, fan-out packaging, and more recently developed silicon interconnect fabric integration. This review includes approaches for both design modification studies and packaged device validation. Methods are explored for compatibility in new complex packaging assemblies. Suggestions are proposed for optimizations of the testing practices to account for the challenges anticipated in upcoming HI packaging schemes. Full article
(This article belongs to the Special Issue Advances in Microelectronics Reliability)
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