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JLPEA
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RISC-V Architectures and Systems: Hardware and Software Perspectives
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RISC-V Architectures and Systems: Hardware and Software Perspectives

A special issue of Journal of Low Power Electronics and Applications (ISSN 2079-9268).

Deadline for manuscript submissions: closed (1 October 2022) | Viewed by 21253

Special Issue Editors

Dr. Teresa Cervero

E-Mail Website
Guest Editor
Barcelona Supercomputing Center, 08034 Barcelona, Spain
Interests: dynamic reconfigurable FPGA-based systems; scalable architectures; parallel computing; embedded systems
Dr. Kevin Martin

E-Mail Website
Guest Editor
Lab-STICC, Université Bretagne-Sud, CEDEX, 56321 Lorient , France
Interests: system-level design and methodologies; custom processors; embedded multi-processor platforms; CGRAs; high-level synthesis; computer-aided design for SoCs; embedded systems
Dr. Mario Kovač

E-Mail Website
Guest Editor
Department of Control and Computer Engineering, University of Zagreb, 10000 Zagreb, Croatia
Interests: computer architecture; accelerator architectures; high performance computing; image processing
Prof. Maurizio Martina

E-Mail Website
Guest Editor
Department of Electronics and Telecommunications, Polytechnic University of Turin, 10129 Torino, Italy
Interests: VLSI design; channel decoder architectures; image and video compression; digital signal processing
Special Issues, Collections and Topics in MDPI journals

Special Issue Information

RISC-V is attracting a lot of interest in different directions, ranging from hardware to software aspects, such as low-power implementation, high-performance computing, compilers and tools, and several emerging applications. Depending on the application domain, different requirements must be taken into proper account. Opening the ISA of RISC-V paved the way to the opening of the whole digital design ecosystem. Thus, aspects such as energy efficiency, reliability, security, and open-source CAD/EDA tools can be tackled from different perspectives.

Such an interest is fostering a high number of academic and industrial research efforts around worldwide projects and initiatives  to provide not only implementations but also analysis and methodologies either at the hardware or software level.

This Special Issue aims to shed some light on some of the aforementioned topics, tackled by RISC-V-based initiatives and projects, by sharing the most recent and promising results with the research community.

Authors are invited to submit regular papers following the JLPEA submission guidelines, within the remit of this Special Issue call. Topics include but are not limited to:

  • RISC-V processors, micro-architecture optimizations, and hardware accelerators;
  • Edge computing and ISA extension (e.g., packed-SIMD, floating point, bit-manipulation);
  • System integration, atomic memory operations, OS support (e.g., hypervisor), compiler and runtimes, containerization, and virtualization;
  • Simulation and emulation, performance analysis tools, and methodologies,
  • Quality assurance and reliability, design verification/validation, and security (secure architectures and cryptography).

Dr. Teresa Cervero
Dr. Kevin Martin
Dr. Mario Kovač
Prof. Maurizio Martina
Guest Editors

Manuscript Submission Information

Manuscripts should be submitted online at www.mdpi.com by registering and logging in to this website. Once you are registered, click here to go to the submission form. Manuscripts can be submitted until the deadline. All submissions that pass pre-check are peer-reviewed. Accepted papers will be published continuously in the journal (as soon as accepted) and will be listed together on the special issue website. Research articles, review articles as well as short communications are invited. For planned papers, a title and short abstract (about 100 words) can be sent to the Editorial Office for announcement on this website.

Submitted manuscripts should not have been published previously, nor be under consideration for publication elsewhere (except conference proceedings papers). All manuscripts are thoroughly refereed through a single-blind peer-review process. A guide for authors and other relevant information for submission of manuscripts is available on the Instructions for Authors page. Journal of Low Power Electronics and Applications is an international peer-reviewed open access quarterly journal published by MDPI.

Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 1800 CHF (Swiss Francs). Submitted papers should be well formatted and use good English. Authors may use MDPI's English editing service prior to publication or during author revisions.

Keywords

  • Hardware architectures
  • Methodologies and CAD/EDA tools
  • Security
  • Software stack, tools, and applications

Published Papers (6 papers)

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21 pages, 1719 KiB  
Article
A Bottom-Up Methodology for the Fast Assessment of CNN Mappings on Energy-Efficient Accelerators
by Guillaume Devic, Gilles Sassatelli and Abdoulaye Gamatié
J. Low Power Electron. Appl. 2023, 13(1), 5; https://doi.org/10.3390/jlpea13010005 - 05 Jan 2023
Viewed by 2119
Abstract
The execution of machine learning (ML) algorithms on resource-constrained embedded systems is very challenging in edge computing. To address this issue, ML accelerators are among the most efficient solutions. They are the result of aggressive architecture customization. Finding energy-efficient mappings of ML workloads [...] Read more.
The execution of machine learning (ML) algorithms on resource-constrained embedded systems is very challenging in edge computing. To address this issue, ML accelerators are among the most efficient solutions. They are the result of aggressive architecture customization. Finding energy-efficient mappings of ML workloads on accelerators, however, is a very challenging task. In this paper, we propose a design methodology by combining different abstraction levels to quickly address the mapping of convolutional neural networks on ML accelerators. Starting from an open-source core adopting the RISC-V instruction set architecture, we define in RTL a more flexible and powerful multiply-and-accumulate (MAC) unit, compared to the native MAC unit. Our proposal contributes to improving the energy efficiency of the RISC-V cores of PULPino. To effectively evaluate its benefits at system level, while considering CNN execution, we build a corresponding analytical model in the Timeloop/Accelergy simulation and evaluation environment. This enables us to quickly explore CNN mappings on a typical RISC-V system-on-chip model, manufactured under the name of GAP8. The modeling flexibility offered by Timeloop makes it possible to easily evaluate our novel MAC unit in further CNN accelerator architectures such as Eyeriss and DianNao. Overall, the resulting bottom-up methodology assists designers in the efficient implementation of CNNs on ML accelerators by leveraging the accuracy and speed of the combined abstraction levels. Full article
(This article belongs to the Special Issue RISC-V Architectures and Systems: Hardware and Software Perspectives)
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13 pages, 1845 KiB  
Article
Evaluation of Dynamic Triple Modular Redundancy in an Interleaved-Multi-Threading RISC-V Core
by Marcello Barbirotta, Abdallah Cheikh, Antonio Mastrandrea, Francesco Menichelli, Marco Ottavi and Mauro Olivieri
J. Low Power Electron. Appl. 2023, 13(1), 2; https://doi.org/10.3390/jlpea13010002 - 28 Dec 2022
Cited by 9 | Viewed by 2837
Abstract
Functional safety is a key requirement in several application domains in which microprocessors are an essential part. A number of redundancy techniques have been developed with the common purpose of protecting circuits against single event upset (SEU) faults. In microprocessors, functional redundancy may [...] Read more.
Functional safety is a key requirement in several application domains in which microprocessors are an essential part. A number of redundancy techniques have been developed with the common purpose of protecting circuits against single event upset (SEU) faults. In microprocessors, functional redundancy may be achieved through multi-core or simultaneous-multi-threading architectures, with techniques that are broadly classifiable as Double Modular Redundancy (DMR) and Triple Modular Redundancy (TMR), involving the duplication or triplication of architecture units, respectively. RISC-V plays an interesting role in this context for its inherent extendability and the availability of open-source microarchitecture designs. In this work, we present a novel way to exploit the advantages of both DMR and TMR techniques in an Interleaved-Multi-Threading (IMT) microprocessor architecture, leveraging its replicated threads for redundancy, and obtaining a system that can dynamically switch from DMR to TMR in the case of faults. We demonstrated the approach for a specific family of RISC-V cores, modifying the microarchitecture and proving its effectiveness with an extensive RTL fault-injection simulation campaign. Full article
(This article belongs to the Special Issue RISC-V Architectures and Systems: Hardware and Software Perspectives)
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18 pages, 3345 KiB  
Article
CCALK: (When) CVA6 Cache Associativity Leaks the Key
by Valentin Martinoli, Elouan Tourneur, Yannick Teglia and Régis Leveugle
J. Low Power Electron. Appl. 2023, 13(1), 1; https://doi.org/10.3390/jlpea13010001 - 27 Dec 2022
Viewed by 2218
Abstract
In this work, we study an end-to-end implementation of a Prime + Probe covert channel on the CVA6 RISC-V processor implemented on a FPGA target and running a Linux OS. We develop the building blocks of the covert channel and provide a detailed [...] Read more.
In this work, we study an end-to-end implementation of a Prime + Probe covert channel on the CVA6 RISC-V processor implemented on a FPGA target and running a Linux OS. We develop the building blocks of the covert channel and provide a detailed view of its behavior and effectiveness. We propose a realistic scenario for extracting information of an AES-128 encryption algorithm implementation. Throughout this work, we discuss the challenges brought by the presence of a running OS while carrying out a micro architectural covert channel. This includes the effects of having other running processes, unwanted cache evictions and the OS’ timing behavior. We also propose an analysis of the relationship between the data cache’s characteristics and the developed covert channel’s capacity to extract information. According to the results of our experimentations, we present guidelines on how to build and configure a micro architectural covert channel resilient cache in a mono-core mono-thread scenario. Full article
(This article belongs to the Special Issue RISC-V Architectures and Systems: Hardware and Software Perspectives)
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19 pages, 2629 KiB  
Article
Advanced Embedded System Modeling and Simulation in an Open Source RISC-V Virtual Prototype
by Pascal Pieper, Vladimir Herdt and Rolf Drechsler
J. Low Power Electron. Appl. 2022, 12(4), 52; https://doi.org/10.3390/jlpea12040052 - 29 Sep 2022
Cited by 1 | Viewed by 5471
Abstract
RISC-V is a modern Instruction Set Architecture (ISA) that, by its open nature in combination with a clean and modular design, has enormous potential to become a game changer in the Internet of Things (IoT) era. Recently, SystemC-based Virtual Prototypes (VPs) have been [...] Read more.
RISC-V is a modern Instruction Set Architecture (ISA) that, by its open nature in combination with a clean and modular design, has enormous potential to become a game changer in the Internet of Things (IoT) era. Recently, SystemC-based Virtual Prototypes (VPs) have been introduced into the RISC-V ecosystem to lay the foundation for advanced industry-proven system-level use-cases. However, VP-driven environment modeling and interaction have mostly been neglected in the RISC-V context. In this paper, we propose such an extension to broaden the application domain for virtual prototyping in the RISC-V context. As a foundation, we built upon the open source RISC-V VP available at GitHub. For a visualization of the environment purposes, we designed a Graphical User Interface (GUI) and designed appropriate libraries to offer hardware communication interfaces such as GPIO and SPI from the VP to an interactive environment model. Our approach is designed to be integrated with SystemC-based VPs that leverage a Transaction-Level Modeling (TLM) communication system to prefer a speed-optimized simulation. To show the practicability of an environment model, we provide a set of building blocks such as buttons, LEDs and an OLED display and configured them in two demonstration environments. Moreover, for rapid prototyping purposes, we provide a modeling layer that leverages the dynamic Lua scripting language to design components and integrate them with the VP-based simulation. Our evaluation with two different case-studies demonstrates the applicability of our approach in building virtual environments effectively and correctly when matching the real physical systems. To advance the RISC-V community and stimulate further research, we provide our extended VP platform with the environment configuration and visualization toolbox, as well as both case-studies as open source on GitHub. Full article
(This article belongs to the Special Issue RISC-V Architectures and Systems: Hardware and Software Perspectives)
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19 pages, 701 KiB  
Article
FAC-V: An FPGA-Based AES Coprocessor for RISC-V
by Tiago Gomes, Pedro Sousa, Miguel Silva, Mongkol Ekpanyapong and Sandro Pinto
J. Low Power Electron. Appl. 2022, 12(4), 50; https://doi.org/10.3390/jlpea12040050 - 27 Sep 2022
Cited by 4 | Viewed by 4068
Abstract
In the new Internet of Things (IoT) era, embedded Field-Programmable Gate Array (FPGA) technology is enabling the deployment of custom-tailored embedded IoT solutions for handling different application requirements and workloads. Combined with the open RISC-V Instruction Set Architecture (ISA), the FPGA technology provides [...] Read more.
In the new Internet of Things (IoT) era, embedded Field-Programmable Gate Array (FPGA) technology is enabling the deployment of custom-tailored embedded IoT solutions for handling different application requirements and workloads. Combined with the open RISC-V Instruction Set Architecture (ISA), the FPGA technology provides endless opportunities to create reconfigurable IoT devices with different accelerators and coprocessors tightly and loosely coupled with the processor. When connecting IoT devices to the Internet, secure communications and data exchange are major concerns. However, adding security features requires extra capabilities from the already resource-constrained IoT devices. This article presents the FAC-V coprocessor, which is an FPGA-based solution for an RISC-V processor that can be deployed following two different coupling styles. FAC-V implements in hardware the Advanced Encryption Standard (AES), one of the most widely used cryptographic algorithms in IoT low-end devices, at the cost of few FPGA resources. The conducted experiments demonstrate that FAC-V can achieve performance improvements of several orders of magnitude when compared to the software-only AES implementation; e.g., encrypting a message of 16 bytes with AES-256 can reach a performance gain of around 8000× with an energy consumption of 0.1 μJ. Full article
(This article belongs to the Special Issue RISC-V Architectures and Systems: Hardware and Software Perspectives)
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21 pages, 851 KiB  
Tutorial
Computer Engineering Education Experiences with RISC-V Architectures—From Computer Architecture to Microcontrollers
by Peter Jamieson, Huan Le, Nathan Martin, Tyler McGrew, Yicheng Qian, Eric Schonauer, Alan Ehret and Michel A. Kinsy
J. Low Power Electron. Appl. 2022, 12(3), 45; https://doi.org/10.3390/jlpea12030045 - 09 Aug 2022
Cited by 1 | Viewed by 2972
Abstract
With the growing popularity of RISC-V and various open-source released RISC-V processors, it is now possible for computer engineers students to explore this simple and relevant architecture, and also, these students can explore and design a microcontroller at a low-level using real tool-flows [...] Read more.
With the growing popularity of RISC-V and various open-source released RISC-V processors, it is now possible for computer engineers students to explore this simple and relevant architecture, and also, these students can explore and design a microcontroller at a low-level using real tool-flows and implement and test their hardware. In this work, we describe our experiences with undergraduate engineers building RISC-V architectures on an FPGA and then extending their experiences to implement an Arduino-like RISC-V tool-flow and the respective hardware and software to handle input-output ports, interrupts, hardware timers, and communication protocols. The microcontroller is implemented on an FPGA as a Senior Design project to test the viability of such efforts. In this work, we will explain how undergraduates can achieve these experiences including preparation for these projects, the tool-flows they use, the challenges in understanding and extending a RISC-V processor with microcontroller functionality, and a suggestion of how to integrate this learning into an existing curriculum, including a discussion on if we should include these deeper experiences in the Computer Engineering undergraduate curriculum. Full article
(This article belongs to the Special Issue RISC-V Architectures and Systems: Hardware and Software Perspectives)
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