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Electronics
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Detection of Hardware Attacks and Security-Oriented Design in IoT Systems
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Detection of Hardware Attacks and Security-Oriented Design in IoT Systems

A special issue of Electronics (ISSN 2079-9292). This special issue belongs to the section "Networks".

Deadline for manuscript submissions: closed (30 June 2023) | Viewed by 12401

Special Issue Editors

Dr. Xiaolong Guo

E-Mail Website
Guest Editor
Department of Electrical and Computer Engineering, Kansas State University, Manhattan, KS 66506, USA
Interests: hardware security; third-party IP protection; formal verification and program analysis; language-based security
Dr. Dean Sullivan

E-Mail Website
Guest Editor
Department of Electrical and Computer Engineering, University of New Hampshire, Durham, NH 03824, USA
Interests: architectural security

Special Issue Information

Dear Colleagues,

The growing capabilities of sensing, computing, and communication devices are leading to an explosion in the use of IoT devices. IoT applications follow stringent demands, such as timing and function correctness, disturbances’ resilience, data integrity and confidentiality, etc. Thus, the disturbance sources and attack surfaces are growing and becoming more diversified, while IoT systems are scaling up and becoming more heterogeneous. Due to the significant effects of security vulnerabilities and attacks, IoT system development and deployment are facing significant challenges, such as sensitive data leakage, malicious intrusions of power grid, car hijacking, etc. Further, as a type of infrastructure, hardware trustworthiness and security are of crucial significance to IoT systems. Therefore, the purpose of this Special Issue is to seek contributions that exploit hardware attacks, detect hardware-related anomalies, follow a security-oriented hardware design (or hardware and software co-design), and use automated tools in IoT systems. Topics of interest include but are not limited to the following IoT security areas:

  • Side-channel and fault attack, and resilience/countermeasures;
  • Intrusion and anomaly detection;
  • CPS security;
  • Smart grid security;
  • Hardware security and privacy;
  • Formal method-based security verification, program analysis, and fuzzing;
  • Security tool development;
  • Security-oriented hardware design, or hardware and software co-design;
  • Physical unclonable functions (PUFs), random number generators, cryptographic units, and key storage technologies;
  • IoT devices and protocol security;
  • Machine learning for IoT Security.

Dr. Xiaolong Guo
Dr. Dean Sullivan
Guest Editors

Manuscript Submission Information

Manuscripts should be submitted online at www.mdpi.com by registering and logging in to this website. Once you are registered, click here to go to the submission form. Manuscripts can be submitted until the deadline. All submissions that pass pre-check are peer-reviewed. Accepted papers will be published continuously in the journal (as soon as accepted) and will be listed together on the special issue website. Research articles, review articles as well as short communications are invited. For planned papers, a title and short abstract (about 100 words) can be sent to the Editorial Office for announcement on this website.

Submitted manuscripts should not have been published previously, nor be under consideration for publication elsewhere (except conference proceedings papers). All manuscripts are thoroughly refereed through a single-blind peer-review process. A guide for authors and other relevant information for submission of manuscripts is available on the Instructions for Authors page. Electronics is an international peer-reviewed open access semimonthly journal published by MDPI.

Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 2400 CHF (Swiss Francs). Submitted papers should be well formatted and use good English. Authors may use MDPI's English editing service prior to publication or during author revisions.

Published Papers (7 papers)

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Research

20 pages, 7301 KiB  
Article
Formal Analysis of Reentrancy Vulnerabilities in Smart Contract Based on CPN
by Yaqiong He, Hanjie Dong, Huaiguang Wu and Qianheng Duan
Electronics 2023, 12(10), 2152; https://doi.org/10.3390/electronics12102152 - 09 May 2023
Cited by 4 | Viewed by 2225
Abstract
A smart contract is a special form of computer program that runs on a blockchain and provides a new way to implement financial and business transactions in a conflict-free and transparent environment. In blockchain systems such as Ethereum, smart contracts can handle and [...] Read more.
A smart contract is a special form of computer program that runs on a blockchain and provides a new way to implement financial and business transactions in a conflict-free and transparent environment. In blockchain systems such as Ethereum, smart contracts can handle and autonomously transfer assets of considerable value to other parties. Hence, it is particularly important to ensure that smart contracts function as intended since bugs or vulnerabilities may lead, and indeed have led, to substantial economic losses and erosion of trust for blockchain. While a number of approaches and tools have been developed to find vulnerabilities, formal methods present the highest level of confidence in the security of smart contracts. In this paper, we propose a formal solution to model a smart contract based on colored Petri nets (CPNs). Herein, we focus on the most common type of security bugs in smart contract, i.e., reentrancy bugs, which led to a serious financial loss of around USD 34 million for the Cream Finance project in 2021. We present a hierarchical CPN modelling method to analyze potential security vulnerabilities at the contract’s source code level. Then, modeling analysis methods such as correlation matrix, state space report and state space graph generated via CPN Tools simulation are exploited for formal analysis of smart contracts. The example shows the full state space and wrong path in accordance with our expected results. Finally, the conclusion was verified on the Ethereum network based on the Remix platform. Full article
(This article belongs to the Special Issue Detection of Hardware Attacks and Security-Oriented Design in IoT Systems)
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11 pages, 723 KiB  
Article
Noise2Clean: Cross-Device Side-Channel Traces Denoising with Unsupervised Deep Learning
by Honggang Yu, Mei Wang, Xiyu Song, Haoqi Shan, Hongbing Qiu, Junyi Wang and Kaichen Yang
Electronics 2023, 12(4), 1054; https://doi.org/10.3390/electronics12041054 - 20 Feb 2023
Cited by 3 | Viewed by 1646
Abstract
Deep learning (DL)-based side-channel analysis (SCA) has posed a severe challenge to the security and privacy of embedded devices. During its execution, an attacker exploits physical SCA leakages collected from profiling devices to create a DL model for recovering secret information from victim [...] Read more.
Deep learning (DL)-based side-channel analysis (SCA) has posed a severe challenge to the security and privacy of embedded devices. During its execution, an attacker exploits physical SCA leakages collected from profiling devices to create a DL model for recovering secret information from victim devices. Despite this success, recent works have demonstrated that certain countermeasures, such as random delay interrupts or clock jitters, would make these attacks more complex and less practical in real-world scenarios. To address this challenge, we present a novel denoising scheme that exploits the U-Net model to pre-process SCA traces for “noises” (i.e., countermeasures) removal. Specifically, we first pre-train the U-Net model on the paired noisy-clean profiling traces to obtain suitable parameters. This model is then fine-tuned on the noisy-only traces collected from the attacking device. The well-trained model will be finally deployed on the attacking device to remove the noises (i.e., countermeasures) from the measured power traces. In particular, a new inductive transfer learning method is also utilized in our scheme to transfer knowledge learned from the source domain (i.e., profiling device) to the target domain (i.e., attacking device) to improve the model’s generalization ability. During our experimental evaluations, we conduct a detailed analysis of various countermeasures separately or combined and show that the proposed denoising model outperforms current state-of-the-art work by a large margin, e.g., a reduction of at least 30% in computation costs and 5× in guessing entropy. Full article
(This article belongs to the Special Issue Detection of Hardware Attacks and Security-Oriented Design in IoT Systems)
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14 pages, 1702 KiB  
Article
An Efficiency–Accuracy Balanced Power Leakage Evaluation Framework Utilizing Principal Component Analysis and Test Vector Leakage Assessment
by Zhen Zheng, Yingjian Yan, Yanjiang Liu, Linyuan Li and Yajing Chang
Electronics 2022, 11(24), 4191; https://doi.org/10.3390/electronics11244191 - 15 Dec 2022
Cited by 2 | Viewed by 1135
Abstract
The test vector leakage assessment (TVLA) is a widely used side-channel power leakage detection technology which requires evaluators to collect as many power traces as possible to ensure accuracy. However, as the total sample size of the power traces increases, the amount of [...] Read more.
The test vector leakage assessment (TVLA) is a widely used side-channel power leakage detection technology which requires evaluators to collect as many power traces as possible to ensure accuracy. However, as the total sample size of the power traces increases, the amount of redundant information will also increase, thus limiting the detection efficiency. To address this issue, we propose a principal component analysis (PCA)-TVLA-based leakage detection framework which realizes a more advanced balance of accuracy and efficiency. Before implementing TVLA to detect leakage, we project the original power data onto their most significant feature dimensions extracted by the PCA procedure and screen power traces according to the magnitude of their corresponding components in the variance of the projection vector. We verified the overall performance of the proposed framework by measuring the detection capability and efficiency with t-values and the required time, respectively. The results show that compared with similar existing schemes, under the best circumstances, the proposed framework decreases the t-value by 4.3% while saving time by 25.2% on the MCU platform and decreases the t-value by 2.4% while saving time by 38.0% on the FPGA platform. Full article
(This article belongs to the Special Issue Detection of Hardware Attacks and Security-Oriented Design in IoT Systems)
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17 pages, 797 KiB  
Article
A Non-Destructive Method for Hardware Trojan Detection Based on Radio Frequency Fingerprinting
by Siya Mi, Zechuan Zhang, Yu Zhang and Aiqun Hu
Electronics 2022, 11(22), 3776; https://doi.org/10.3390/electronics11223776 - 17 Nov 2022
Cited by 2 | Viewed by 1424
Abstract
Hardware Trojans (HTs) pose a security threat to the Internet of Things (IoT). Attackers can take control of devices in IoT through HTs, which seriously jeopardize the security of many systems in transportation, finance, healthcare, etc. Since subtle differences in the circuit are [...] Read more.
Hardware Trojans (HTs) pose a security threat to the Internet of Things (IoT). Attackers can take control of devices in IoT through HTs, which seriously jeopardize the security of many systems in transportation, finance, healthcare, etc. Since subtle differences in the circuit are reflected in far-field signals emitted by the system, the detection of HT status can be performed by monitoring the radio frequency fingerprinting (RFF) of the transmitting signals. For the detection of HTs, a non-destructive detection method based on RFF is proposed in this paper. Based on the proposed method, the detection of HTs can be achieved without integrating additional devices in the receiver, which reduces associated costs and energy consumption. QPSK and triangular-wave signals are measured and identified via experimentation, and the results validate the proposed method. For identifying the presence and operating state of Trojan, the average accuracy achieved measures as high as 98.7%. Notably, with regard to capturing the moment of Trojan activation in the AES encryption circuit, the accuracy of the proposed method is 100% and can provide warning of the threat in a timely manner. Full article
(This article belongs to the Special Issue Detection of Hardware Attacks and Security-Oriented Design in IoT Systems)
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17 pages, 2326 KiB  
Article
A High Flexible Shift Transformation Unit Design Approach for Coarse-Grained Reconfigurable Cryptographic Arrays
by Tongzhou Qu, Zibin Dai, Yanjiang Liu and Lin Chen
Electronics 2022, 11(19), 3144; https://doi.org/10.3390/electronics11193144 - 30 Sep 2022
Cited by 1 | Viewed by 1395
Abstract
Shift transformations are the fundamental operation of cryptographic algorithms, and the arithmetic unit implementing different types of shift transformations are utilized in the coarse-grain reconfigurable cryptographic architectures (CGRCA) to meet the different cryptographic algorithms. In this paper, a reconfigurable shift transformation unit (RSTU) [...] Read more.
Shift transformations are the fundamental operation of cryptographic algorithms, and the arithmetic unit implementing different types of shift transformations are utilized in the coarse-grain reconfigurable cryptographic architectures (CGRCA) to meet the different cryptographic algorithms. In this paper, a reconfigurable shift transformation unit (RSTU) is proposed to meet the complicated shift requirement of CGRCA, which achieves high flexibility and a good cost–performance ratio. The mathematical properties of shift transformation are analyzed, and several theorems are introduced to design a reconfigurable shifter. Furthermore, the reconfigurable data path of the proposed unit is presented to implement the random combination of shift operations in different granularity, and configuration word and routing algorithms are proposed to generate control information for RSTU. Moreover, the control information generation module is designed to invert the configuration word into the control information, according to the routing algorithms. As a proof-of-concept, the proposed RSTU is built using the CMOS 65 nm technology. The experimental results show that RSTU supports more shift operations, increases 18.2% speed at most, and reduces 13% area occupation, compared to the existing shifters. Full article
(This article belongs to the Special Issue Detection of Hardware Attacks and Security-Oriented Design in IoT Systems)
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9 pages, 1066 KiB  
Article
Hardware Trojan Detection Using Effective Property-Checking Method
by Dejian Li, Qizhi Zhang, Dongyan Zhao, Lei Li, Jiaji He, Yidong Yuan and Yiqiang Zhao
Electronics 2022, 11(17), 2649; https://doi.org/10.3390/electronics11172649 - 24 Aug 2022
Cited by 1 | Viewed by 1843
Abstract
Hardware Trojans refer to additional logic maliciously implanted by attackers in integrated circuits (ICs). Because of the potential security threat of hardware Trojans, they have attracted extensive attention to security issues. As a formal verification method, property checking has been proved to be [...] Read more.
Hardware Trojans refer to additional logic maliciously implanted by attackers in integrated circuits (ICs). Because of the potential security threat of hardware Trojans, they have attracted extensive attention to security issues. As a formal verification method, property checking has been proved to be a powerful solution for hardware Trojan detection. However, existing property-checking methods are limited by the unity of security properties and the model explosion problem of formal models. The limitations above hinder the practical applications of these methods. To alleviate these challenges, we propose an effective property-checking method for hardware Trojan detection. Specifically, we establish the formal model based on the principle of finite state machine (FSM), and the method can alleviate the model explosion problem. For property writing, we extract the core behavior characteristics of hardware Trojans and then generate properties for the verification of certain types of hardware Trojans. Experimental results demonstrate that our approach is applicable to detect information leakage and denial of service (DoS) hardware Trojans by verifying security properties. Full article
(This article belongs to the Special Issue Detection of Hardware Attacks and Security-Oriented Design in IoT Systems)
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21 pages, 4503 KiB  
Article
Evaluation on the Impact of Cache Parameter Selection in Access-Driven Cache Attacks
by Pengfei Guo, Yingjian Yan, Bin Ye, Chunsheng Zhu, Lichao Zhang, Ting Shen and Lin Chen
Electronics 2022, 11(15), 2340; https://doi.org/10.3390/electronics11152340 - 27 Jul 2022
Cited by 2 | Viewed by 1353
Abstract
Cache attacks exploit the hardware vulnerabilities inherent to modern processors and pose a new threat to Internet of Things (IoT) devices. Intuitively, different cache parameter configurations directly impact the attack effectiveness, but the current research on this issue is not systematic or comprehensive [...] Read more.
Cache attacks exploit the hardware vulnerabilities inherent to modern processors and pose a new threat to Internet of Things (IoT) devices. Intuitively, different cache parameter configurations directly impact the attack effectiveness, but the current research on this issue is not systematic or comprehensive enough. This paper’s primary focus is to evaluate how different cache parameter configurations affect access-driven attacks. We build a flexible and configurable simulation verification environment based on the Chipyard framework. To reduce the interference of other factors, we established a baseline for each category of parameter evaluation. We propose a novel evaluation model, called Key Score Scissors Differential (KSSD), for evaluating common private and shared cache parameters under the local and cross-core attack models, respectively; among these are private cache replacement policy, private cache capacity, cache line size, private cache associativity, shared cache capacity, and shared cache associativity. Ours is the first evaluation of the shared cache under a cross-core attack model. As a result of the evaluation, the quantitative metrics can provide a reliable indication of information leakage level under the current cache configuration, which is helpful for attackers, defenders, and evaluators. Furthermore, we provide detailed explanations and discussions of inconsistent findings by comparing our results with the existing literature. Full article
(This article belongs to the Special Issue Detection of Hardware Attacks and Security-Oriented Design in IoT Systems)
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