Research

Jump to: Review

9 pages, 5166 KiB

Open AccessCommunication

A Charge Sensitive Amplifier in a 28 nm CMOS Technology for Pixel Detectors at Future Particle Colliders

by Luigi Gaioni, Andrea Galliani and Gianluca Traversi

Electronics 2023, 12(9), 2054; https://doi.org/10.3390/electronics12092054 - 29 Apr 2023

Viewed by 1409

This paper is concerned with the design of a Charge Sensitive Amplifier (CSA) in a 28 nm CMOS technology. The CSA discussed in this work is conceived for High Energy Physics (HEP) experiments at next-generation colliders, where pixel detectors will be read out [...] Read more.

This paper is concerned with the design of a Charge Sensitive Amplifier (CSA) in a 28 nm CMOS technology. The CSA discussed in this work is conceived for High Energy Physics (HEP) experiments at next-generation colliders, where pixel detectors will be read out by specific front-end chips, typically including a CSA exploited for charge-to-voltage conversion of the signal delivered by the sensor. The main analog performance parameters of the CSA, also referred to as the pre-amplifier, are assessed here by means of specific Spectre simulations, which are meant to evaluate the behavior of the analog processor in terms of noise, linearity and capability to compensate for very large detector leakage currents. Noise simulations revealed an equivalent noise charge close to 75 electrons rms for typical operating conditions. Up to 50 nA sensor leakage current can be compensated for thanks to the CSA Keummenacher feedback network. The total current consumption of the CSA is close to 2.2 µA, which, together with a power supply of 0.9 V, translates to a power consumption of 2.0 µW. Full article

(This article belongs to the Special Issue Feature Papers in Microelectronics)

► Show Figures

Figure 1

23 pages, 8180 KiB

Open AccessArticle

Analytical Delay Modeling for a Sub-Threshold Cell Circuit with the Inverse Gaussian Distribution Function

by Jiuyue Wang, Yuping Wu, Xuelian Zhang, Zhiqiang Li and Lan Chen

Electronics 2023, 12(6), 1387; https://doi.org/10.3390/electronics12061387 - 14 Mar 2023

Viewed by 886

Abstract

Considering that power consumption (PC) is an extremely important indicator in digital circuit design, lower PC has always been our pursuit. PC and power supply voltage are positively correlated, and in this case, we must reduce the operating voltage of the circuit. However, [...] Read more.

Considering that power consumption (PC) is an extremely important indicator in digital circuit design, lower PC has always been our pursuit. PC and power supply voltage are positively correlated, and in this case, we must reduce the operating voltage of the circuit. However, as the voltage continues to decrease, various secondary effects and process variations become increasingly influential, making the delay distribution and its statistical characteristics more difficult to predict. In this paper, an inverse Gaussian distribution is used to model the propagation delay. Taking into account the local process variation, the multi-input delay analytical expression is derived according to the sub-threshold current formula to accurately predict the distribution and statistical characteristics of the delay, and the delay is obtained by calculation instead of Monte Carlo simulation, which greatly reduces the simulation time. The accuracy of the delay expression and delay distribution have been tested under 22 nm FDSOI technology and good results were obtained with operating voltages from 0.20 V to 0.30 V, in which the mean error of the delay is approx. 1.5%, the variance error is approx. 4.3%, and the error of the cumulative distribution function is approx. 2%. Full article

(This article belongs to the Special Issue Feature Papers in Microelectronics)

► Show Figures

Figure 1

15 pages, 4729 KiB

Open AccessArticle

Design and Performance Analysis of 32 × 32 Memory Array SRAM for Low-Power Applications

by Xingsi Xue, Aruru Sai Kumar, Osamah Ibrahim Khalaf, Rajendra Prasad Somineni, Ghaida Muttashar Abdulsahib, Anumala Sujith, Thanniru Dhanuja and Muddasani Venkata Sai Vinay

Electronics 2023, 12(4), 834; https://doi.org/10.3390/electronics12040834 - 07 Feb 2023

Cited by 21 | Viewed by 4994

Abstract

Computer memory comprises temporarily or permanently stored data and instructions, which are utilized in electronic digital computers. The opposite of serial access memory is Random Access Memory (RAM), where the memory is accessed immediately for both reading and writing operations. There has been [...] Read more.

Computer memory comprises temporarily or permanently stored data and instructions, which are utilized in electronic digital computers. The opposite of serial access memory is Random Access Memory (RAM), where the memory is accessed immediately for both reading and writing operations. There has been a vast technological improvement, which has led to tremendous information on the amount of complexity that can be designed on a single chip. Small feature sizes, low power requirements, low costs, and great performance have emerged as the essential attributes of any electronic component. Designers have been forced into the sub-micron realm for all these reasons, which places the leakage characteristics front and centre. Many electrical parts, especially digital ones, are made to store data, emphasising the need for memory. The largest factor in the power consumption of SRAM is the leakage current. In this article, a 1 KB memory array was created using CMOS technology and a supply voltage of 0.6 volts employing a 1-bit 6T SRAM cell. We developed this SRAM with a 1-bit, 32- × 1-bit, and 32 × 32 configuration. The array structure was implemented using a 6T SRAM cell with a minimum leakage current of 18.65 pA and an average delay of 19 ns. The array structure was implemented using a 6T SRAM cell with a power consumption of 48.22 μW and 385 μW for read and write operations. The proposed 32 × 32 memory array SRAM performed better than the existing 8T SRAM and 7T SRAM in terms of power consumption for read and write operations. Using the Cadence Virtuoso tool (Version IC6.1.8-64b.500.14) and 22 nm technology, the functionality of a 1 KB SRAM array was verified. Full article

(This article belongs to the Special Issue Feature Papers in Microelectronics)

► Show Figures

Figure 1

11 pages, 676 KiB

Open AccessArticle

Tunnel FET and MOSFET Hybrid Integrated 9T SRAM with Data-Aware Write Technique for Ultra-Low Power Applications

by Wenjuan Lu, Yixiao Lu, Lanzhi Dong, Chunyu Peng, Xiulong Wu, Zhiting Lin and Junning Chen

Electronics 2022, 11(20), 3392; https://doi.org/10.3390/electronics11203392 - 20 Oct 2022

Cited by 2 | Viewed by 1235

Abstract

In this paper, a Tunnel FETs (TFETs) and MOSFETs hybrid integrated 9T SRAM (HI-9T) with data-aware write technique is proposed. This structure solves the problem of excessive static power consumption caused by forward p-i-n current in the conventional 7T TFET SRAM (CV-7T), and [...] Read more.

In this paper, a Tunnel FETs (TFETs) and MOSFETs hybrid integrated 9T SRAM (HI-9T) with data-aware write technique is proposed. This structure solves the problem of excessive static power consumption caused by forward p-i-n current in the conventional 7T TFET SRAM (CV-7T), and the problem of weakened writing ability caused by the use of the TFET-stacked structure of the most advanced combined access 10T TFET SRAM (CA-10T). The simulation results demonstrate that the static power consumption of HI-9T is reduced by three orders of magnitude compared with CV-7T at a 0.6 V supply voltage and the ability to maintain data is more stable. Compared with CA-10T, the write margin (WM) of HI-9T is increased by about 2.4 times and the write latency is reduced by 54.8% at 0.5 V supply voltage. HI-9T still has good writing ability under the 0.6 V supply voltage and the CA-10T cannot write normally. Therefore, HI-9T has good overall performance and is more advantageous in ultra-low power applications. Full article

(This article belongs to the Special Issue Feature Papers in Microelectronics)

► Show Figures

Figure 1

7 pages, 1726 KiB

Open AccessCommunication

L-Band Wavelength-Selectable Erbium Laser with Stable Single-Frequency Oscillation

by Shang-En Hsieh, Ching-Hsuan Hsu, Chien-Hung Yeh, Syu-Yang Jiang, Yu-Ting Lai, Chi-Wai Chow and Shien-Kuei Liaw

Electronics 2022, 11(19), 2996; https://doi.org/10.3390/electronics11192996 - 21 Sep 2022

Cited by 6 | Viewed by 1191

Abstract

In this presentation, we demonstrate an erbium-doped fiber (EDF) laser by a compound-ring structure to reach the output performances of narrow linewidth, stable single-longitudinal-mode (SLM) and high optical signal to noise ratio (OSNR) in the L-band bandwidth of 1563.0 to 1613.0 nm. Based [...] Read more.

In this presentation, we demonstrate an erbium-doped fiber (EDF) laser by a compound-ring structure to reach the output performances of narrow linewidth, stable single-longitudinal-mode (SLM) and high optical signal to noise ratio (OSNR) in the L-band bandwidth of 1563.0 to 1613.0 nm. Based on the Vernier effect through the compound-ring design, the substantial multi-longitudinal-mode (MLM) noises can be mitigated fully. Furthermore, the relative optical output features of the fiber laser are also performed experimentally. Full article

(This article belongs to the Special Issue Feature Papers in Microelectronics)

► Show Figures

Figure 1

11 pages, 5203 KiB

Open AccessArticle

Design and Analysis of the Self-Biased PLL with Adaptive Calibration for Minimum of the Charge Pump Current Mismatch

by Xueming Wei, Renchuan Yin, Lingli Hou, Weilin Xu and Baolin Wei

Electronics 2022, 11(14), 2133; https://doi.org/10.3390/electronics11142133 - 07 Jul 2022

Viewed by 1282

Abstract

A digital adaptive mismatch calibration (DAMC) circuit is proposed to decrease the output jitter of phase-locked loop (PLL). After amplifying the phase error with a linear time amplifier (TA), the DAMC adopts a successive approximation pulse width calibration method to reduce the mismatch [...] Read more.

A digital adaptive mismatch calibration (DAMC) circuit is proposed to decrease the output jitter of phase-locked loop (PLL). After amplifying the phase error with a linear time amplifier (TA), the DAMC adopts a successive approximation pulse width calibration method to reduce the mismatch current of the charge pump. The PLL prototype is fabricated in a 40nm process, the static phase error of the proposed PLL can be reduced from 358 ps to 10 ps at a 50 MHz reference clock approximately, and the RMS jitter of the PLL output is reduced from 4.91 ps to 3.59 ps, and the extended DAMC area only occupies 1.3% of the whole PLL area. Full article

(This article belongs to the Special Issue Feature Papers in Microelectronics)

► Show Figures

Figure 1

11 pages, 5199 KiB

Open AccessArticle

Pre-Emphasis Pulse Design for Reducing Bit-Line Access Time in NAND Flash Memory

by Junnosuke Kondo and Toru Tanzawa

Electronics 2022, 11(13), 1926; https://doi.org/10.3390/electronics11131926 - 21 Jun 2022

Cited by 1 | Viewed by 1475

Abstract

This paper describes pre-emphasis (PE) pulses to reduce bit-line (BL) access time in NAND flash memory. Optimum PE pulse widths and resultant minimum BL delay times are investigated, where the BL delay is determined by the sense current at the input terminal of [...] Read more.

This paper describes pre-emphasis (PE) pulses to reduce bit-line (BL) access time in NAND flash memory. Optimum PE pulse widths and resultant minimum BL delay times are investigated, where the BL delay is determined by the sense current at the input terminal of a sensing circuit in contrast with the word-line (WL) delay that is determined by the WL voltage at the gate of a selected memory cell. Two BL models are used, namely, a single-line model (SLM) for the shielded BL read operation and a three-line model (TLM) for the all-BL read operation. Under the condition that the sense current delay is defined by the time when the sense current becomes stable between 110% and 90% of the cell current and the BL voltage delay is defined by the time when the BL voltage at the selected cell reaches a window between 110% and 90%, SPICE simulation results show that the sensed current delay and the BL voltage delay are reduced by 43% and 36% in the case of SLM and by 16% and 28% in the case of TLM, respectively. Thus, the key results are the following: (1) PE pulses are effective to reduce the sense current delay time for BL access, as well as the BL voltage delay time for both SLM and TLM; (2) the sensitivity of the PE pulse on the delay time is much larger for the sensed current delay than the BL voltage delay due to the absence of filtering with the RC delay element in BL delay; and (3) address-dependent PE pulse control can reduce the sense current delay significantly, especially for access to cells closely located to the sensing circuit. Full article

(This article belongs to the Special Issue Feature Papers in Microelectronics)

► Show Figures

Figure 1

Review

Jump to: Research

32 pages, 13331 KiB

Open AccessReview

Bias Temperature Instability of MOSFETs: Physical Processes, Models, and Prediction

by Jian Fu Zhang, Rui Gao, Meng Duan, Zhigang Ji, Weidong Zhang and John Marsland

Electronics 2022, 11(9), 1420; https://doi.org/10.3390/electronics11091420 - 28 Apr 2022

Cited by 8 | Viewed by 3779

Abstract

CMOS technology dominates the semiconductor industry, and the reliability of MOSFETs is a key issue. To optimize chip design, trade-offs between reliability, speed, power consumption, and cost must be carried out. This requires modeling and prediction of device instability, and a major source [...] Read more.

CMOS technology dominates the semiconductor industry, and the reliability of MOSFETs is a key issue. To optimize chip design, trade-offs between reliability, speed, power consumption, and cost must be carried out. This requires modeling and prediction of device instability, and a major source of instability is device aging, where defects gradually build up and eventually cause malfunction of circuits. This paper first gives an overview of the major aging processes and discusses their relative importance as CMOS technology developed. Attentions are then focused on the negative and positive bias temperature instabilities (NBTI and PBTI), mainly based on the early works of the authors. The aim is to present the As-grown-Generation (AG) model, which can be used not only to fit the test data but also to predict long-term BTI at low biases. The model is based on an in-depth understanding of the different types of defects and the experimental separation of their contributions to BTI. The new measurement techniques developed to enable this separation are reviewed. The physical processes responsible for BTI are explored, and the reasons for the failure of the early models in predicting BTI are discussed. Full article

(This article belongs to the Special Issue Feature Papers in Microelectronics)

► Show Figures

Figure 1

Journal Menu

Journal Browser

Feature Papers in Microelectronics

Share This Special Issue

Special Issue Editors

Special Issue Information

Keywords

Published Papers (8 papers)

Research

Review

Further Information

Guidelines

MDPI Initiatives

Follow MDPI