Research

17 pages, 2111 KiB

Open AccessArticle

An Experimental Electronic Board ADF339 for Analog and FPGA-Based Digital Filtration of Measurement Signals

by Cezary Pałczyński and Paweł Olejnik

Electronics 2024, 13(4), 805; https://doi.org/10.3390/electronics13040805 - 19 Feb 2024

Viewed by 544

This work introduces and examines a new programmable electronic system, Board ADF339, designed for filtering analog measurement signals of low frequencies. The system operates in a mixed mode in collaboration with a digital controller implemented on the myRIO-1900 FPGA module. It enables the [...] Read more.

This work introduces and examines a new programmable electronic system, Board ADF339, designed for filtering analog measurement signals of low frequencies. The system operates in a mixed mode in collaboration with a digital controller implemented on the myRIO-1900 FPGA module. It enables the digital selection of the type and frequency settings of the UAF42 integrated circuit. In the technical implementation section, electronic filter and phase shifter circuit diagrams are presented, along with the digital counterpart of the analog filter. Tests of this system were conducted on signals generated using a function generator, which was followed by the filtration of signals occurring in real laboratory setups. A series of real responses from three different laboratory systems and a measurement system utilizing LabVIEW FPGA virtual instruments are demonstrated. After computing SNR indicators for noisy waveforms, the application scope and usability of the board are highlighted. Full article

(This article belongs to the Special Issue FPGAs Based Hardware Design)

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18 pages, 8903 KiB

Open AccessArticle

ZX Fusion: A ZX Spectrum Implementation on an FPGA with Modern Peripherals

by Gustavo Jacinto and Rui Policarpo Duarte

Electronics 2024, 13(2), 450; https://doi.org/10.3390/electronics13020450 - 22 Jan 2024

Viewed by 2444

Abstract

The ZX Spectrum was a popular 8-bit home computer by Sinclair Research in the 1980s. Even though some of these computers may still work, the audio tapes, the TV with an analog tuner, and the micro-switch joystick that were used with the original [...] Read more.

The ZX Spectrum was a popular 8-bit home computer by Sinclair Research in the 1980s. Even though some of these computers may still work, the audio tapes, the TV with an analog tuner, and the micro-switch joystick that were used with the original ZX Spectrum are outdated and hard to find in good working order or to replicate. As many other old closed systems are also very difficult to update to support modern peripherals there is a necessity to provide a methodology to adapt such systems to support new peripherals while being compatible with existing software. This implementation is a means by which to validate the methodology before applying it to a physical system. The work proposed in this paper focused on recreating a ZX Spectrum+/48K computer and interfacing it with modern peripherals on an FPGA. This was accomplished by adding a co-processor to assist with the control of the more complex peripherals. Otherwise, the original system would require complex architectural changes and would perform poorly due to the low performance of the Z80 CPU. This work distanced itself from previous works on emulating a ZX Spectrum, as it focused on the use of different upgraded peripherals and the use of a NIOS II soft processor as a co-processor to manage the SD card accesses and save-state functionality. A demonstration of the proposed modernized architecture was made by successfully running a diagnostics ROM and playing original ZX Spectrum games from an SD card for games with a PS/2 keyboard and a pair of joysticks. Full article

(This article belongs to the Special Issue FPGAs Based Hardware Design)

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32 pages, 3584 KiB

Open AccessArticle

Design and Assurance of Safety-Critical Systems with Artificial Intelligence in FPGAs: The Safety ArtISt Method and a Case Study of an FPGA-Based Autonomous Vehicle Braking Control System

by Antonio V. Silva Neto, Henrique L. Silva, João B. Camargo, Jr., Jorge R. Almeida, Jr. and Paulo S. Cugnasca

Electronics 2023, 12(24), 4903; https://doi.org/10.3390/electronics12244903 - 06 Dec 2023

Cited by 1 | Viewed by 1000

Abstract

With the advancements in utilizing Artificial Intelligence (AI) in embedded safety-critical systems based on Field-Programmable Gate Arrays (FPGAs), assuring that these systems meet their safety requirements is of paramount importance for their revenue service. Based on this context, this paper has two main [...] Read more.

With the advancements in utilizing Artificial Intelligence (AI) in embedded safety-critical systems based on Field-Programmable Gate Arrays (FPGAs), assuring that these systems meet their safety requirements is of paramount importance for their revenue service. Based on this context, this paper has two main objectives. The first of them is to present the Safety ArtISt method, developed by the authors to guide the lifecycle of AI-based safety-critical systems, and emphasize its FPGA-oriented tasks and recommended practice towards safety assurance. The second one is to illustrate the application of Safety ArtISt with an FPGA-based braking control system for autonomous vehicles relying on explainable AI generated with High-Level Synthesis. The results indicate that Safety ArtISt played four main roles in the safety lifecycle of AI-based systems for FPGAs. Firstly, it provided guidance in identifying the safety-critical role of activities such as sensitivity analyses for numeric representation and FPGA dimensioning to achieve safety. Furthermore, it allowed building qualitative and quantitative safety arguments from analyses and physical experimentation with actual FPGAs. It also allowed the early detection of safety issues—thus reducing project costs—and, ultimately, it uncovered relevant challenges not discussed in detail when designing safety-critical, explainable AI for FPGAs. Full article

(This article belongs to the Special Issue FPGAs Based Hardware Design)

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13 pages, 485 KiB

Open AccessArticle

A Parameterized Parallel Design Approach to Efficient Mapping of CNNs onto FPGA

by Ning Mao, Haigang Yang and Zhihong Huang

Electronics 2023, 12(5), 1106; https://doi.org/10.3390/electronics12051106 - 23 Feb 2023

Cited by 3 | Viewed by 1239

Abstract

In recent years, Convolution Neural Networks (CNNs) have been widely applied to some artificial intelligence (AI) systems such as computer vision. Among many existing hardware accelerators, FPGA is regarded as a suitable platform for the implementation of CNNs because of its high energy [...] Read more.

In recent years, Convolution Neural Networks (CNNs) have been widely applied to some artificial intelligence (AI) systems such as computer vision. Among many existing hardware accelerators, FPGA is regarded as a suitable platform for the implementation of CNNs because of its high energy efficiency and flexible reconfigurability. In this paper, a parameterized design approach is proposed to explore the maximum parallelism that could be possibly implemented in mapping a CNN algorithm onto targeted FPGA resources. Four types of parallelism are employed in our parameterized design to fully exploit the processing resources available in FPGA. Meanwhile, a hardware library consisting of a set of modules is established to accommodate various CNN models. Further, an algorithm is proposed to find the optimal level of parallelism dedicated to a constrained amount of resources. As a case study, the typical LeNet-5 is implemented on Xilinx Zynq7020. Compared with the existing works using the high-level synthesis design flow, our design obtains higher FPS and lower latency under the premise of using fewer LUTs and FFs. Full article

(This article belongs to the Special Issue FPGAs Based Hardware Design)

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19 pages, 5645 KiB

Open AccessArticle

A Methodology for Accelerating FPGA Fault Injection Campaign Using ICAP

by Frederico Ferlini, Felipe Viel, Laio Oriel Seman, Hector Pettenghi, Eduardo Augusto Bezerra and Valderi Reis Quietinho Leithardt

Electronics 2023, 12(4), 807; https://doi.org/10.3390/electronics12040807 - 06 Feb 2023

Cited by 2 | Viewed by 1658

Abstract

The increasing complexity of System-on-Chip (SoC) and the ongoing technology miniaturization on Integrated Circuit (IC) manufacturing processes makes modern SoCs more susceptible to Single-Event Effects (SEE) caused by radiation, even at sea level. To provide realistic estimates at a low cost, efficient analysis [...] Read more.

The increasing complexity of System-on-Chip (SoC) and the ongoing technology miniaturization on Integrated Circuit (IC) manufacturing processes makes modern SoCs more susceptible to Single-Event Effects (SEE) caused by radiation, even at sea level. To provide realistic estimates at a low cost, efficient analysis techniques capable of replicating SEEs are required. Among these methods, fault injection through emulation using Field-Programmable Gate Array (FPGA) enables campaigns to be run on a Circuit Under Test (CUT). This paper investigates the use of an FPGA architecture to speed up the execution of fault campaigns. As a result, a new methodology for mapping the CUT occupation on the FPGA is proposed, significantly reducing the total number of faults to be injected. In addition, a fault injection technique/flow is proposed to demonstrate the benefits of cutting-edge approaches. The presented technique emulates Single-Event Transient (SET) in all combinatorial elements of the CUT using the Internal Configuration Access Port (ICAP) of Xilinx FPGAs. Full article

(This article belongs to the Special Issue FPGAs Based Hardware Design)

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16 pages, 5908 KiB

Open AccessArticle

Memory-Tree Based Design of Optical Character Recognition in FPGA

by Ke Yu, Minguk Kim and Jun Rim Choi

Electronics 2023, 12(3), 754; https://doi.org/10.3390/electronics12030754 - 02 Feb 2023

Cited by 2 | Viewed by 3043

Abstract

As one of the fields of Artificial Intelligence (AI), Optical Character Recognition (OCR) systems have wide application in both industrial production and daily life. Conventional OCR systems are commonly designed and implement data computation on the basis of microprocessors; the performance of the [...] Read more.

As one of the fields of Artificial Intelligence (AI), Optical Character Recognition (OCR) systems have wide application in both industrial production and daily life. Conventional OCR systems are commonly designed and implement data computation on the basis of microprocessors; the performance of the processor relates to the effect of the computation. However, due to the “Memory-wall” problem and Von Neumann bottlenecks, the drawbacks of traditional processor-based computing for OCR systems are gradually becoming apparent. In this paper, an approach based on the Memory-Centric Computing and “Memory-Tree” algorithm has been proposed to perform hardware optimization of traditional OCR systems. The proposed algorithm was first designed in software implementation using C/C++ and OpenCV to verify the feasibility of the idea and then the RTL conversion of the algorithm was done using the Xilinx Vitis High Level Synthesis (HLS) tool to implement the hardware. This work chose Xilinx Alveo U50 FPGA Accelerator to complete the hardware design, which can be connected to the x86 CPU in the PC by PCIe to form heterogeneous computing. The results of the hardware implementation show that the system this work designed can recognize characters of English capital letters and numbers within 34.24 us. The power of FPGA is 18.59 W, which saves 77.87% of energy consumption compared to the 84 W of the processor in PC. Full article

(This article belongs to the Special Issue FPGAs Based Hardware Design)

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27 pages, 6514 KiB

Open AccessArticle

A Deterministic Branch Prediction Technique for a Real-Time Embedded Processor Based on PicoBlaze Architecture

by Ehsan Ali and Wanchalerm Pora

Electronics 2022, 11(21), 3438; https://doi.org/10.3390/electronics11213438 - 24 Oct 2022

Viewed by 1752

Abstract

This paper proposes a new deterministic branch prediction unit to achieve a uniformly timed instruction set architecture (ISA). The deterministic ISA is achieved by utilizing two address buses in conjunction with dual-port block RAMs that are common in commercial FPGAs. The goal is [...] Read more.

This paper proposes a new deterministic branch prediction unit to achieve a uniformly timed instruction set architecture (ISA). The deterministic ISA is achieved by utilizing two address buses in conjunction with dual-port block RAMs that are common in commercial FPGAs. The goal is to remove mandatory branch and load delays to achieve a uniform one clock cycle per every instruction. To demonstrate the concept, the proposed architecture is applied to the Xilinx PicoBlaze firm core. The result is a new soft core named DAP-Zipi8 that reduces the clock per instruction (CPI) metric of PicoBlaze from two to one at the expense of extra logic and a longer critical path. The increased critical path reduces maximum achievable clock speed from 357.509 MHz to 224.022 MHz. Merging the gain in CPI with the loss in maximum clock frequency still improves overall processor performance by 18.28–19.49%. The high-performance deterministic DAP-Zipi8 is a viable choice for hard RTES applications. Full article

(This article belongs to the Special Issue FPGAs Based Hardware Design)

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14 pages, 4069 KiB

Open AccessArticle

Scalable Hardware Efficient Architecture for Parallel FIR Filters with Symmetric Coefficients

by Jinghao Ye, Masao Yanagisawa and Youhua Shi

Electronics 2022, 11(20), 3272; https://doi.org/10.3390/electronics11203272 - 11 Oct 2022

Cited by 2 | Viewed by 1243

Abstract

Symmetric convolutions can be utilized for potential hardware resource reduction. However, they have not been realized in state-of-the-art transposed block FIR designs. Therefore, we explore the feasibility of symmetric convolution in transposed parallel FIRs and propose a scalable hardware efficient parallel architecture. The [...] Read more.

Symmetric convolutions can be utilized for potential hardware resource reduction. However, they have not been realized in state-of-the-art transposed block FIR designs. Therefore, we explore the feasibility of symmetric convolution in transposed parallel FIRs and propose a scalable hardware efficient parallel architecture. The proposed design inserts delay elements after multipliers for temporal reuse of intermediate tap products. By doing this, the number of required multipliers can be reduced by half. As a result, we can achieve up to 3.2× and 1.64× area efficiency improvements over the modern transposed block method on reconfigurable and fixed designs, respectively. These results confirm the effectiveness of the proposed STB-FIR architecture for hardware-efficient, high-speed signal processing. Full article

(This article belongs to the Special Issue FPGAs Based Hardware Design)

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