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Analog IC Design—Analog and RF Interface for Electronic Systems
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Analog IC Design—Analog and RF Interface for Electronic Systems

A topical collection in Electronics (ISSN 2079-9292). This collection belongs to the section "Circuit and Signal Processing".

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Editors

Prof. Dr. Andrea Boni

E-Mail Website
Guest Editor
Department of Engineering and Architecture, University of Parma, 43124 Parma, Italy
Interests: electronics engineering; analog integrated circuits; CMOS; low-power analog circuits; analog circuit design; analog–digital conversion; energy harvesting; analog in-memory computing; low-power RF receivers; bandgap references
Special Issues, Collections and Topics in MDPI journals
Dr. Michele Caselli

E-Mail Website
Guest Editor
Department of Electrical Engineering (ESAT), KU Leuven / imec vzw (IMEC), Kapeldreef 75, B-3001 Leuven, Belgium
Interests: CMOS; microelectronics; circuit simulation; cadence; analog electronics; circuit analysis; electronics; digital electronics; VHDL programming; electrical and electronics engineering

Topical Collection Information

Dear Colleagues,

Any analog and RF interface circuit acts as a mandatory bridge between an outer and an inner environment, composed by digital circuits and systems devoted to computing and storage.

Analog interface circuits are integrated in almost all consumer, industrial, automotive, and medical devices with sensing capability, whereas RF interfaces enable device-to-device connections or connection to a local-area network or the internet. Even if nowadays, radio communication systems are mostly digital, they still need to be interfaced with antennas and, therefore, dedicated circuits such as low-noise amplifiers and RF power amplifiers are mandatory.

Special mention must be made of circuits used to link the analog and digital domains, such as the A/D and D/A converters, which have experienced impressive performance improvements in terms of speed, resolution, silicon area, and power consumption in recent decades. Usually, these interfaces are integrated in dedicated ICs or co-integrated with digital circuits composing mixed-signal systems with increased complexity.

In summary, the digital computation and storage capability embedded in electronic devices are strictly correlated with the world of analog and RF interfaces.

This Special Issue focuses on the analysis, design, and implementation of analog and RF interface circuits, integrated in CMOS or BiCMOS silicon technologies. 

Prof. Dr. Andrea Boni
Dr. Michele Caselli
Guest Editors

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Keywords

  • A/D and D/A converter
  • front-end circuits for sensor interfaces (industrial, biochemical, medical, etc.)
  • ultralow-power sensor interfaces for wireless devices
  • analog and RF interfaces for IoT devices
  • low noise and offset amplifier
  • interface circuits for automotive systems
  • power amplifiers and drivers
  • RF circuits: LNAs and power amplifiers

Published Papers (18 papers)

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2023

Jump to: 2022, 2021

27 pages, 2768 KiB  
Article
Switching Capacitor Filter with Multiple Functions, Adjustable Bandwidth in the Range of 5 Hz–10 kHz
by Fan He, Yubo Yuan, Jinjin Xiao, Zehao Han, Yingchun Fu and Shuilong Huang
Electronics 2023, 12(23), 4862; https://doi.org/10.3390/electronics12234862 - 01 Dec 2023
Viewed by 895
Abstract
This article proposes a second-order switch-capacitor filter that integrates low-pass, high-pass, band-pass, band-stop, and all-pass, and achieves flexible bandwidth adjustment of the filter through clock rate and capacitance ratio. The final filter design consists of two completely independent second-order switch-capacitor filter channels, and [...] Read more.
This article proposes a second-order switch-capacitor filter that integrates low-pass, high-pass, band-pass, band-stop, and all-pass, and achieves flexible bandwidth adjustment of the filter through clock rate and capacitance ratio. The final filter design consists of two completely independent second-order switch-capacitor filter channels, and a 4-order Butterworth low-pass filter is designed through two-stage cascades. The two completely independent second-order switch-capacitor filters are integrated on a single chip and manufactured using the Huahong BCD350GE high-voltage 24 V process. The measurement results indicate that the proposed switch-capacitor filter achieves various functional filtering characteristics and achieves a bandwidth of 5 Hz to 10 kHz. The chip area is 5.1 × 3.1 mm2, powered by a dual power supply of ± 5 V, and the power consumption is 80 mW. Full article
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19 pages, 38379 KiB  
Article
Design of a Wide-Range and High-Precision Analog Front-End Circuit for Multi-Parameter Sensors
by Yating Yang, Zheng Li, Mingyang Liu, Wei Liu, Zhenming Li, Ying Hou, Xin Liu, Xiaosong Wang and Yu Liu
Electronics 2023, 12(13), 2962; https://doi.org/10.3390/electronics12132962 - 05 Jul 2023
Cited by 1 | Viewed by 1631
Abstract
This article presents a wide-range and high-precision analog front-end circuit for multi-parameter sensors that can handle sensor outputs of different types (R, C, V). A rail-to-rail baseline compensation method has been proposed, which further incorporates a fine offset elimination of 0.6 mV/step. Additionally, [...] Read more.
This article presents a wide-range and high-precision analog front-end circuit for multi-parameter sensors that can handle sensor outputs of different types (R, C, V). A rail-to-rail baseline compensation method has been proposed, which further incorporates a fine offset elimination of 0.6 mV/step. Additionally, self-zeroing and correlated double-sampling techniques are integrated to reduce low-frequency noise and offset, prevent sensor signal saturation, and enhance the precision of the analog front-end circuit. By incorporating variable components in the sensor signal acquisition circuit and integrating them with the baseline compensation circuit, the applicability range of the sensor has been expanded (R: 7 Ω–1.7 MΩ, C: 50 fF–35 pF, V: 0.05–1.7 V). Test results show all interface circuits exhibit significant total conversion gains (C: 45 mV/fF, R: 14.5 mV/Ω, V: 144 V/V), achieving high precision. Meanwhile, a coefficient of determination (R2) greater than 0.998 indicates high conversion linearity of the circuit. Full article
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2022

Jump to: 2023, 2021

10 pages, 3188 KiB  
Article
Integrated 0.35-µm CMOS Control Circuits for High-Performance Voltage Mode DC–DC Boost Converter
by Chan-Soo Lee, Munkhsuld Gendensuren, Bayarsaikan Dansran, Bierng-Chearl Ahn and Seong-Gon Choi
Electronics 2023, 12(1), 133; https://doi.org/10.3390/electronics12010133 - 28 Dec 2022
Cited by 3 | Viewed by 3036
Abstract
The integrated DC–DC converter is appropriate for use in many domains, namely, display, cellular, and portable applications. This paper presents an integrated control circuit for a monolithic voltage mode DC–DC boost converter for display driver applications. The control circuits consist of a transconductance [...] Read more.
The integrated DC–DC converter is appropriate for use in many domains, namely, display, cellular, and portable applications. This paper presents an integrated control circuit for a monolithic voltage mode DC–DC boost converter for display driver applications. The control circuits consist of a transconductance amplifier, a comparator, and an oscillator. The boost converter consists of an inductor, two MOSFET, and an output RC filter. The control circuits are designed for fast transient response and low output ripple. The transconductance amplifier, comparator, and oscillator in the control circuit are designed to operate at a supply voltage of 3.3 V and an operating frequency of 5.5 MHz. The transconductance amplifier consists of an operational amplifier and an RC filter in the feedback path. The RC filter has a pole with a sufficient phase margin for high stability. The control circuits are realized in a 0.35-μm CMOS process together with the DC–DC converter. The fabricated DC–DC converter was evaluated by experiment and simulation. Testing of the proposed control circuits shows that the output transient time can be controlled within 7 μs, and the output voltage is accurately controlled with a ripple ratio of 3%. Full article
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11 pages, 6129 KiB  
Article
A Wireless Data Transfer by Using a Patch Antenna for Biomedical Applications
by Gyung-Su Byun
Electronics 2022, 11(24), 4197; https://doi.org/10.3390/electronics11244197 - 15 Dec 2022
Cited by 2 | Viewed by 1406
Abstract
In this paper, a 20 GHz wireless data transfer (WDT) interface for implantable applications is proposed. The proposed WDT utilizes a small-form factor off-chip antenna to transfer data through a human body. By using the implantable antenna, the biomedical WDT system occupies a [...] Read more.
In this paper, a 20 GHz wireless data transfer (WDT) interface for implantable applications is proposed. The proposed WDT utilizes a small-form factor off-chip antenna to transfer data through a human body. By using the implantable antenna, the biomedical WDT system occupies a smaller chip size, which is suitable for future biomedical applications. The proposed WDT system with a small-form factor patch antenna and near-threshold VCO operates at 20 GHz, has a data rate of 1.8 Gb/s and consumes only a low power of 5.4 pJ/b. Full article
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12 pages, 1574 KiB  
Article
A 320 μW Multi-Band Receiver with N-Path Switched-Capacitor Networks
by Lei Lei, Fang Han, Zicheng Liu, Quanwen Qi, Xinghua Wang and Weijiang Wang
Electronics 2022, 11(24), 4111; https://doi.org/10.3390/electronics11244111 - 09 Dec 2022
Viewed by 1021
Abstract
This paper presents a multi-band ultra-low power (ULP) receiver with N-Path Switched-Capacitor (NPSC) networks in 90 nm CMOS process. The NPSC is integrated into the feedback loop of the low noise amplifier (LNA) to flexibly provide narrowband input matching at multiple sub-GHz Industrial, [...] Read more.
This paper presents a multi-band ultra-low power (ULP) receiver with N-Path Switched-Capacitor (NPSC) networks in 90 nm CMOS process. The NPSC is integrated into the feedback loop of the low noise amplifier (LNA) to flexibly provide narrowband input matching at multiple sub-GHz Industrial, Scientific, and Medical (ISM) bands by adjusting the switching frequency. Moreover, the LNA with an NPSC network is utilized to suppress the out-of-band signal at the input and output of the LNA, simultaneously. In order to achieve an ultra-low power consumption, a sub-threshold LNA and four passive NPSC mixers are implemented in this receiver. The ULP receiver achieves a measured gain of 40±2 dB in ISM bands (430/860/915/960 MHz). The measured noise figure and out-of-band IIP3 are 10±0.5 dB and −0.3±2 dBm, respectively. The ULP receiver chip consumes 320 μW at 0.4 V power supply and occupies a chip area of 0.31 mm2. Full article
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16 pages, 883 KiB  
Article
A 177 ppm RMS Error-Integrated Interface for Time-Based Impedance Spectroscopy of Sensors
by Antonio Vincenzo Radogna, Simonetta Capone, Luca Francioso, Pietro Aleardo Siciliano and Stefano D’Amico
Electronics 2022, 11(22), 3807; https://doi.org/10.3390/electronics11223807 - 19 Nov 2022
Cited by 1 | Viewed by 1198
Abstract
This paper presents an integrated circuit for time-based electrical impedance spectroscopy (EIS) of sensors. The circuit exploits maximum-length sequences (MLS) in order to perform a broadband excitation of the sensors under test. Therefore, the measured time-domain EIS is obtained by cross-correlating the input [...] Read more.
This paper presents an integrated circuit for time-based electrical impedance spectroscopy (EIS) of sensors. The circuit exploits maximum-length sequences (MLS) in order to perform a broadband excitation of the sensors under test. Therefore, the measured time-domain EIS is obtained by cross-correlating the input with the output of the analog front end (AFE). Unlike the conventional digital approach, the cross-correlation operation is performed in the analog domain. This leads to a lower RMS error in the measured time-domain EIS since the signal processing is not affected by the quantization noise of the analog-to-digital converter (ADC). It also relaxes the sampling frequency of the ADC leading, along with the lack of random access memory (RAM) usage, to a reduced circuit complexity. Theoretical concepts about the circuit’s design and operation are presented, with an emphasis on the thermal noise phenomenon. The simulated performances are shown by testing a sensor’s equivalent model composed of a 50 kΩ resistor in parallel with a 100 pF capacitor. A time-based EIS output of 255 points was obtained with a maximum tested frequency of 500 kHz and a simulated RMS error of 0.0177% (or 177 ppm). Full article
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17 pages, 5910 KiB  
Article
Reset Noise Sampling Feedforward Technique (RNSF) for Low Noise MEMS Capacitive Accelerometer
by Xinquan Lai, Yuheng Wang, Qinqin Li and Kashif Habib
Electronics 2022, 11(17), 2693; https://doi.org/10.3390/electronics11172693 - 27 Aug 2022
Cited by 3 | Viewed by 1460
Abstract
The reset noise sampling feedforward (RNSF) technique is proposed in this paper to reduce the noise floor of the readout circuit for micro-electromechanically systems (MEMS) capacitive accelerometer. Because of the technology-imposed size restriction on the sensing element, the sensing capacitance and the capacitance [...] Read more.
The reset noise sampling feedforward (RNSF) technique is proposed in this paper to reduce the noise floor of the readout circuit for micro-electromechanically systems (MEMS) capacitive accelerometer. Because of the technology-imposed size restriction on the sensing element, the sensing capacitance and the capacitance variation are reduced to the femto-farad level. As a result, the reset noise from the parasitic capacitance, which is pico-farad level, becomes significant. In this work, the RNSF technique focuses on the suppression of the parasitic-capacitance-induced noise, thereby improving the noise performance of MEMS capacitive accelerometer. The simulation results show that the RNSF technique effectively suppresses the thermal noise from the parasitic capacitance. Compared with the traditional readout circuit, the noise floor of the readout circuit with the RNSF technique is reduced by 9 dBV. The presented circuit based on the RNSF technique is fabricated by a commercial 0.18-μm BCD process and tested with a femto-farad MEMS capacitive accelerometer. The physical measurement results show that, compared with the readout circuit without the RNSF technique, the RNSF technique reduces the noise floor of the readout circuit for MEMS capacitive accelerometer from −72 dBV to −80 dBV. Compared with other similar works, the proposed readout circuit achieves better FoM (FoM=(power×noise floor)/system bandwidth=490 μW·μg/Hz) among the switched-capacitor readout circuits. Full article
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11 pages, 7046 KiB  
Article
A 1.2 V 0.4 mW 20~200 MHz DLL Based on Phase Detector Measuring the Delay of VCDL
by Sang-Hyun Cho and Young-Kyun Cho
Electronics 2022, 11(15), 2434; https://doi.org/10.3390/electronics11152434 - 04 Aug 2022
Viewed by 1805
Abstract
A delay locked loop (DLL) based on a Phase Detector, which Measures the Delay of the Voltage-controlled delay line (PD-MDV), which is tVCDL, with efficient and stable locking performance was proposed. In contrast to conventional phase detectors, the PD-MDV measures t [...] Read more.
A delay locked loop (DLL) based on a Phase Detector, which Measures the Delay of the Voltage-controlled delay line (PD-MDV), which is tVCDL, with efficient and stable locking performance was proposed. In contrast to conventional phase detectors, the PD-MDV measures tVCDL more accurately; thus, it can always generate the correct up/down (UP/DN) pulses. The proposed technique prevents becoming stuck in the fastest operation, in which UP pulses continue to appear even when tVCDL < tREF, where tREF is the reference time, which is an input of the DLL. In the reverse case, the PD-MDV prohibits DN pulses from continuing to appear under the condition tVCDL > tREF, thereby freeing the DLL from harmonic locking and becoming stuck in the slowest operation. The proposed phase detection scheme was verified under various conditions, including process corners, temperature variations, and abrupt changes in tREF. The proposed 1.2 V, 20~200 MHz DLL with the PD-MDV was designed using the 65 nm process, with a power consumption of 0.4 mW at 200 MHz. Full article
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12 pages, 4963 KiB  
Article
A 500 kHz to 150 MHz Multi-Output Clock Generator Using Analog PLL and Open-Loop Fractional Divider with 0.13 μm CMOS
by Junting Jin, Yuhua Jin and Yebing Gan
Electronics 2022, 11(15), 2347; https://doi.org/10.3390/electronics11152347 - 27 Jul 2022
Cited by 1 | Viewed by 2052
Abstract
Clocks are widely used in multimedia and electronic devices, and they usually have different frequency demands. This paper presents the design of a multi-output clock generator using an analog integer-N phase-locked loop (PLL) and open-loop fractional dividers. The PLL based on a three-stage [...] Read more.
Clocks are widely used in multimedia and electronic devices, and they usually have different frequency demands. This paper presents the design of a multi-output clock generator using an analog integer-N phase-locked loop (PLL) and open-loop fractional dividers. The PLL based on a three-stage ring voltage-controlled oscillator (VCO) is used to transform the lower frequency reference into a high-frequency intermediate clock (600 MHz–900 MHz). Then, relying on the open-loop fractional divider, a wide frequency range of 500 kHz to 150 MHz can be generated. Due to the open-loop control characteristic, the clock generator has instantaneous frequency switching capability. In addition, phase-adjusting circuits added to the divider greatly improved the jitter performance of the output clock; its RMS jitter is 5.2 ps. This work was conducted with 0.13 μm CMOS technology. The open-loop divider occupies an area of 0.032 mm2 and consumes 7.7 mW from a 1.2 V supply. Full article
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24 pages, 3727 KiB  
Article
Low-Phase-Noise CMOS Relaxation Oscillators for On-Chip Timing of IoT Sensing Platforms
by Francesco Gagliardi, Giuseppe Manfredini, Andrea Ria, Massimo Piotto and Paolo Bruschi
Electronics 2022, 11(11), 1794; https://doi.org/10.3390/electronics11111794 - 06 Jun 2022
Cited by 5 | Viewed by 2607
Abstract
The design of low-phase-noise fully integrated frequency references is often a critical aspect in the development of low-cost integrated circuits for communication interfaces, sensing platforms, and biomedical applications. This work first discusses relaxation oscillator topologies and design approaches aimed at minimizing the phase [...] Read more.
The design of low-phase-noise fully integrated frequency references is often a critical aspect in the development of low-cost integrated circuits for communication interfaces, sensing platforms, and biomedical applications. This work first discusses relaxation oscillator topologies and design approaches aimed at minimizing the phase noise; then, a single-comparator low-phase-noise RC relaxation oscillator is proposed, featuring a novel comparator self-threshold-adjustment technique. The oscillator was designed for a 10 MHz oscillation frequency. Electrical simulations performed on a 0.18 μm CMOS design confirmed that the proposed technique effectively rejects the flicker component of the comparator noise, allowing for a 152 dBc/Hz figure of merit at a 1 kHz offset frequency. The standard deviation of the jitter accumulated across 10k oscillation cycles is lower than 4 ns. The simulated current consumption of the circuit is equal to 50.8 μA with a 1.8 V supply voltage. The temperature sensitivity of the oscillation frequency is also notably low, as its worst-case value across process corners is equal to −20.8 ppm/°C from −55 °C to 125 °C. Full article
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16 pages, 12385 KiB  
Article
Receiver Analog Front-End Cascading Transimpedance Amplifier and Continuous-Time Linear Equalizer for Signals of 5 to 30 Gb/s
by Pragada Venkata Satya Challayya Naidu and Chih-Wen Lu
Electronics 2022, 11(10), 1546; https://doi.org/10.3390/electronics11101546 - 12 May 2022
Cited by 1 | Viewed by 2759
Abstract
A 5–30 Gb/s receiver analog front-end (AFE) cascading transimpedance amplifier (TIA) and continuous-time linear equalizer (CTLE) were implemented using a Taiwan Semiconductor 180 nm process. The system comprises a two-stage differential input pair CTLE, TIA, and a differential termination resistor Rm. [...] Read more.
A 5–30 Gb/s receiver analog front-end (AFE) cascading transimpedance amplifier (TIA) and continuous-time linear equalizer (CTLE) were implemented using a Taiwan Semiconductor 180 nm process. The system comprises a two-stage differential input pair CTLE, TIA, and a differential termination resistor Rm. A source-degenerated transconductance stage was adopted in the CTLE, and source follower and shunt feedback resistor stages were adopted in the TIA. The proposed CTLE could achieve high frequencies by altering the tail current with fixed degenerate capacitance CS and resistance RS. The proposed AFE achieved high bandwidth, and the use of a feedback resistor Rf and inductor Lf improved its high-frequency performance. Simulation results revealed that the CTLE can compensate for 16 dB of channel loss at a 3 GHz Nyquist frequency and can open closed eyes in a 6 Gb/s non-return-to-zero signal with a bit error rate of 0.16 × 10−12 for a 231 − 1 pseudorandom binary sequence input. The AFE could compensate for 12 dB of channel loss at a 15 GHz Nyquist frequency and can open closed eyes in a 30 Gb/s PAM4 signal from a pseudorandom binary sequence input; it consumed 27 mW of power at 1.8 V. Full article
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11 pages, 4557 KiB  
Article
Low Phase-Noise, 2.4 and 5.8 GHz Dual-Band Frequency Synthesizer with Class-C VCO and Bias-Controlled Charge Pump for RF Wireless Charging System in 180 nm CMOS Process
by Jongwan Jo, David Kim, Arash Hejazi, YoungGun Pu, Yeonjae Jung, Hyungki Huh, Seokkee Kim, Joon-Mo Yoo and Kang-Yoon Lee
Electronics 2022, 11(7), 1118; https://doi.org/10.3390/electronics11071118 - 01 Apr 2022
Cited by 3 | Viewed by 2707
Abstract
This paper presents an integer-N phase-locked loop (PLL) for an RF wireless charging system. To improve the phase-noise characteristics under low power, a constant amplitude control class-C voltage-controlled oscillator (VCO) with a DC-DC converter, and a bias-controlled charge pump with a feedback loop [...] Read more.
This paper presents an integer-N phase-locked loop (PLL) for an RF wireless charging system. To improve the phase-noise characteristics under low power, a constant amplitude control class-C voltage-controlled oscillator (VCO) with a DC-DC converter, and a bias-controlled charge pump with a feedback loop are proposed. The frequency range of the VCO is 4.5–6.1 GHz, the target frequency of the proposed PLL is 2.4 and 5.8 GHz in the industry–science–medical band. It is designed with a same phase margin and bandwidth using one loop filter. The proposed PLL consumes less than 8 mW from a 1.8 V power supply with a settling time of fewer than 20 μs and an area of 1200 μm × 800 μm in the 180 nm CMOS process. For a carrier frequency offset of 1 MHz, the measured phase noise is −118.5 dBc/Hz at 2.4 GHz and −116.6 dBc/Hz at 5.8 GHz. Its FoM including the phase noise is −197 dB at 2.4 GHz and −202.8 GHz at 5.8 GHz, outperforming other PLLs designed in the 180 nm CMOS process. Full article
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18 pages, 7575 KiB  
Article
CMOS Interface Circuits for High-Voltage Automotive Signals
by Andrea Boni, Michele Caselli, Alessandro Magnanini and Matteo Tonelli
Electronics 2022, 11(6), 971; https://doi.org/10.3390/electronics11060971 - 21 Mar 2022
Viewed by 3055
Abstract
The acquisition of high-voltage signals from sensors and actuators in an internal-combustion engine is often required for diagnostic purposes or in the case of conversion to alternative fuels, such as hydrogen, natural gas, or biogas. The integration of electronic interfaces and acquisition circuits [...] Read more.
The acquisition of high-voltage signals from sensors and actuators in an internal-combustion engine is often required for diagnostic purposes or in the case of conversion to alternative fuels, such as hydrogen, natural gas, or biogas. The integration of electronic interfaces and acquisition circuits in a single device provides benefits in terms of component-count reduction and performance. Nonetheless, the high voltage level of the involved signals makes on-chip design challenging. Additionally, the circuits should be compatible with the CMOS technology, with limited use of high-voltage options and a minimum number of off-chip components. This paper describes the design and the implementation in 350 nm CMOS technology of electronic interfaces and acquisition circuits for typical high-voltage signals of automotive context. In particular, a novel co-design of dedicated voltage clamps with electro-static discharge (ESD) protections is described. The proposed circuits require only a single off-chip resistor, and they are suitable for the acquisition of signals with peak voltages up to 400 V. The measured performance of the silicon prototypes, in the [−40 °C, +125 °C] temperature range, make the proposed electronic interfaces suitable for the automotive domain. Full article
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2021

Jump to: 2023, 2022

16 pages, 5114 KiB  
Article
A Low-Voltage, Ultra-Low-Power, High-Gain Operational Amplifier Design for Portable Wearable Devices
by Na Bai, Xiaolong Li and Yaohua Xu
Electronics 2022, 11(1), 74; https://doi.org/10.3390/electronics11010074 - 27 Dec 2021
Cited by 2 | Viewed by 5963
Abstract
Based on the SMIC 0.13 um CMOS technology, this paper uses a 0.8 V supply voltage to design a low-voltage, ultra-low-power, high-gain, two-stage, fully differential operational amplifier. Through the simulation analysis, when the supply voltage is 0.8 V, the design circuit meets the [...] Read more.
Based on the SMIC 0.13 um CMOS technology, this paper uses a 0.8 V supply voltage to design a low-voltage, ultra-low-power, high-gain, two-stage, fully differential operational amplifier. Through the simulation analysis, when the supply voltage is 0.8 V, the design circuit meets the ultra-low power consumption and also has the characteristic of high gain. The five-tube, fully differential, and common-source amplifier circuits provide the operational amplifier with high gain and large swing. Unlike the traditional common-mode feedback, this paper uses the output of the common-mode feedback as the bias voltage of the five-tube operational transconductance amplifier load, which reduces the design cost of the circuit; the structure involves self-cascoding composite MOS, which makes the common-mode feedback loop more sensitive. The frequency compensation circuit adopts Miller compensation technology with zero-pole separation, which increases the stability of the circuit. The input of the circuit uses the current mirror. A small reference current is chosen to reduce power consumption. A detailed performance simulation analysis of this operational amplifier circuit is carried out on the Cadence spectre platform. The open-loop gain of this operational amplifier is 74.1 dB, the phase margin is 61°, the output swing is 0.7 V, the common-mode rejection ratio is 109 dB, and the static power consumption is only 11.2 uW. Full article
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14 pages, 574 KiB  
Article
A High-Gain CNTFET-Based LNA Developed Using a Compact Design-Oriented Device Model
by Paolo Crippa, Giorgio Biagetti, Claudio Turchetti, Laura Falaschetti, Davide Mencarelli, George Deligeorgis and Luca Pierantoni
Electronics 2021, 10(22), 2835; https://doi.org/10.3390/electronics10222835 - 18 Nov 2021
Cited by 2 | Viewed by 1903
Abstract
Recently, carbon nanotube field-effect transistors (CNTFETs) have attracted wide attention as promising candidates for components in the next generation of electronic devices. In particular CNTFET-based RF devices and circuits show superior performance to those built with silicon FETs since they are able to [...] Read more.
Recently, carbon nanotube field-effect transistors (CNTFETs) have attracted wide attention as promising candidates for components in the next generation of electronic devices. In particular CNTFET-based RF devices and circuits show superior performance to those built with silicon FETs since they are able to obtain higher power-gain and cut-off frequency at lower power dissipation. The aim of this paper is to present a compact, design-oriented model of CNTFETs that is able to ease the development of a complete amplifier. As a case study, the detailed design of a high-gain CNTFET-based broadband inductorless LNA is presented. Full article
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9 pages, 25568 KiB  
Article
A 9-Bit 1-GS/s Hybrid-Domain Pseudo-Pipelined SAR ADC Based on Variable Gain VTC and Segmented TDC
by Suping Bai, Zhi Wan, Peiyuan Wan, Hongda Zhang, Yongkuo Ma, Xiaoyu Zhang, Xu Liu and Zhijie Chen
Electronics 2021, 10(21), 2650; https://doi.org/10.3390/electronics10212650 - 29 Oct 2021
Cited by 2 | Viewed by 1788
Abstract
This paper presents a 9-bit 1 GS/s successive approximation register (SAR) analog-to-digital converter (ADC). In this hybrid architecture, the pseudo-pipeline operation is realized, which increases the sampling rate effectively. The ADC adopts two key technologies: the variable gain voltage-to-time converter (VTC), which ensures [...] Read more.
This paper presents a 9-bit 1 GS/s successive approximation register (SAR) analog-to-digital converter (ADC). In this hybrid architecture, the pseudo-pipeline operation is realized, which increases the sampling rate effectively. The ADC adopts two key technologies: the variable gain voltage-to-time converter (VTC), which ensures the linearity is not sacrificed; the segmented time-to-digital converter (STDC), which further improves the linearity of time domain quantization. The prototype ADC is simulated in a standard 65-nm CMOS process with an active area of 0.038 mm2. The simulated SNDR and SFDR are 44.3 and 58 dB with a sampling rate of 1 GS/s. The FoMW and FoMS are 24.7 fJ/conv-step and 150.7 dB, respectively. Full article
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19 pages, 2988 KiB  
Article
On the VCO/Frequency Divider Interface in Cryogenic CMOS PLL for Quantum Computing Applications
by Gabriele Gira, Elena Ferraro and Mattia Borgarino
Electronics 2021, 10(19), 2404; https://doi.org/10.3390/electronics10192404 - 01 Oct 2021
Cited by 2 | Viewed by 2981
Abstract
The availability of quantum microprocessors is mandatory, to efficiently run those quantum algorithms promising a radical leap forward in computation capability. Silicon-based nanostructured qubits appear today as a very interesting approach, because of their higher information density, longer coherence times, fast operation gates, [...] Read more.
The availability of quantum microprocessors is mandatory, to efficiently run those quantum algorithms promising a radical leap forward in computation capability. Silicon-based nanostructured qubits appear today as a very interesting approach, because of their higher information density, longer coherence times, fast operation gates, and compatibility with the actual CMOS technology. In particular, thanks to their phase noise properties, the actual CMOS RFIC Phase-Locked Loops (PLL) and Phase-Locked Oscillators (PLO) are interesting circuits to synthesize control signals for spintronic qubits. In a quantum microprocessor, these circuits should operate close to the qubits, that is, at cryogenic temperatures. The lack of commercial cryogenic Design Kits (DK) may make the interface between the Voltage Controlled Oscillator (VCO) and the Frequency Divider (FD) a serious issue. Nevertheless, currently this issue has not been systematically addressed in the literature. The aim of the present paper is to investigate the VCO/FD interface when the temperature drops from room to cryogenic. To this purpose, physical models of electronics passive/active devices and equivalent circuits of VCO and the FD were developed at room and cryogenic temperatures. The modeling activity has led to design guidelines for the VCO/FD interface, useful in the absence of cryogenic DKs. Full article
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12 pages, 7824 KiB  
Article
VLSI Architectures of a Wiener Filter for Video Coding
by Walid Walid, Giorgio Armanno, Sandro Di Paola, Massimo Ruo Roch, Guido Masera and Maurizio Martina
Electronics 2021, 10(16), 1961; https://doi.org/10.3390/electronics10161961 - 14 Aug 2021
Cited by 2 | Viewed by 2057
Abstract
In the modern age, the use of video has become fundamental in communication and this has led to its use through an increasing number of devices. The higher resolution required for images and videos leads to more memory space and more efficient data [...] Read more.
In the modern age, the use of video has become fundamental in communication and this has led to its use through an increasing number of devices. The higher resolution required for images and videos leads to more memory space and more efficient data compression, obtained by improving video coding techniques. For this reason, the Alliance for Open Media (AOMedia) developed a new open-source and royalty-free codec, named AOMedia Video 1 (AV1). This work focuses on the Wiener filter, a specific loop restoration tool of the AV1 video coding format, which features a significant amount of computational complexity. A new hardware architecture implementing the separable symmetric normalized Wiener filter is presented. Furthermore, the paper details possible optimizations starting from the basic architecture. These optimizations allow the Wiener filter to achieve a 100× reduction in processing time, compared to existing works, and 5× improvement in megasamples per second. Full article
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