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Advances on Analog-to-Digital and Digital-to-Analog Converters

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A special issue of Electronics (ISSN 2079-9292). This special issue belongs to the section "Circuit and Signal Processing".

Deadline for manuscript submissions: closed (31 March 2022) | Viewed by 19557

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Special Issue Editors

Prof. Dr. Kamal El-Sankary

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Guest Editor

Electrical & Computer Engineering Department, Dalhousie University, C367, Halifax, NS, Canada
Interests: microelectronics; analog; mixed-signal; digital and RF integrated circuits design in nanoscale CMOS technologies; and embedded systems design
Special Issues, Collections and Topics in MDPI journals

Dr. Karama M. AL-Tamimi

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Guest Editor

Research Associate at Mixed-Signal Laboratory, Dalhousie University, Halifax, NS, Canada
Interests: time domain data converters; low power computation in CMOS; biomedical sensors; analog computing for machine learning

Special Issue Information

Dear Colleagues,

Driven by silicon foundries’ scaling efforts to enable massive distribution of integrated systems with sensing, communication and power management capabilities (i.e., the Internet-of-Things (IoTs) sensing nodes), data converters have received special attention among the most critical integrated circuit blocks owing to their link between the real-world analog environment and digital processing units.

Implementing data converters in nanoscale in CMOS technologies poses several challenges, including a dramatic drop in the available power supply headroom, inferior noise performance, ultra-low low power requirement, and challenges in designing main conventional main blocks, such as operational amplifiers and comparators.

To fully benefit from this downscaling, the above challenges need to be addressed through holistic approaches that embrace scaling-friendly CMOS process. Addressing these challenges implies redefining the way in which data converters are currently designed.

The scope of this Special Issue is to focus and report on the development of emerging techniques to design high performance analog to digital and digital to analog converts in nano-scale technologies.

Specifically, the research portfolio for this issue includes research work related to advances on Analog-to-Digital and Digital-to-Analog Converters. The topics of primary research include but are not limited to:

Nanoscale ultra-low power analog to digital and (ADCs) and analog to digital converters DACs;
Digital calibration techniques for data converters;
Higher spurs free dynamic range (SFDR) DACs;
ADC-based front-end sensors;
Time domain techniques for ultra-low voltage and power consumption;
Hybrid time/voltage data converters;
High resolution sigma delta modulators.

Prof. Dr. Kamal El-Sankary
Dr. Karama M. AL-Tamimi
Guest Editors

Manuscript Submission Information

Manuscripts should be submitted online at www.mdpi.com by registering and logging in to this website. Once you are registered, click here to go to the submission form. Manuscripts can be submitted until the deadline. All submissions that pass pre-check are peer-reviewed. Accepted papers will be published continuously in the journal (as soon as accepted) and will be listed together on the special issue website. Research articles, review articles as well as short communications are invited. For planned papers, a title and short abstract (about 100 words) can be sent to the Editorial Office for announcement on this website.

Submitted manuscripts should not have been published previously, nor be under consideration for publication elsewhere (except conference proceedings papers). All manuscripts are thoroughly refereed through a single-blind peer-review process. A guide for authors and other relevant information for submission of manuscripts is available on the Instructions for Authors page. Electronics is an international peer-reviewed open access semimonthly journal published by MDPI.

Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 2400 CHF (Swiss Francs). Submitted papers should be well formatted and use good English. Authors may use MDPI's English editing service prior to publication or during author revisions.

Published Papers (7 papers)

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Research

13 pages, 2980 KiB

Open AccessArticle

Modelling a New Multifunctional High Accuracy Analogue-to-Digital Converter with an Increased Number of Inputs

by Zynoviy Mychuda, Igor Zhuravel, Lesia Mychuda, Adam Szcześniak and Zbigniew Szcześniak

Electronics 2022, 11(11), 1677; https://doi.org/10.3390/electronics11111677 - 25 May 2022

Cited by 2 | Viewed by 1175

Abstract

This paper presents a multi-input analogue-to-digital functional converter manufactured using switched capacitors. A new method of multifunctional analogue-to-digital processing was tested, which allowed the number of inputs to be increased to 10 without compromising accuracy. An algorithm was developed, and the converter’s operation was modelled based on this method. It was found that error values are not significantly affected by the number of input voltages. The value of the lowest input voltage has a decisive influence on the conversion time. The examined multi-input analogue-to-digital functional converter performs multiplication, division, exponentiation, and root extraction operations. The exponent of the power and the degree of the root corresponds to the number of inputs of the converter. Full article

(This article belongs to the Special Issue Advances on Analog-to-Digital and Digital-to-Analog Converters)

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16 pages, 1732 KiB

Open AccessArticle

Mathematical Modelling of the Influence of Parasitic Capacitances of the Components of the Logarithmic Analogue-to-Digital Converter (LADC) with a Successive Approximation on Switched Capacitors for Increasing Accuracy of Conversion

by Zynoviy Mychuda, Igor Zhuravel, Lesia Mychuda, Adam Szcześniak, Zbigniew Szcześniak and Hanna Yelisieieva

Electronics 2022, 11(9), 1485; https://doi.org/10.3390/electronics11091485 - 06 May 2022

Cited by 4 | Viewed by 1191

Abstract

This paper presents an analysis of the influence of parasitic inter-electrode capacitances of the components of logarithmic analogue-to-digital converters with successive approximation with a variable logarithm base. Mathematical models of converter errors were developed and analyzed taking into account the parameters of modern components. It has been shown that to achieve satisfactory accuracy for the 16 bit LADC, the capacitance of the capacitor cell must not be less than 10 nF; for the 12 bit LADC, 1 nF is sufficient. Full article

(This article belongs to the Special Issue Advances on Analog-to-Digital and Digital-to-Analog Converters)

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10 pages, 1078 KiB

Open AccessArticle

A 28 nm CMOS 10 bit 100 MS/s Asynchronous SAR ADC with Low-Power Switching Procedure and Timing-Protection Scheme

by Fang Tang, Qiyun Ma, Zhou Shu, Yuanjin Zheng and Amine Bermak

Electronics 2021, 10(22), 2856; https://doi.org/10.3390/electronics10222856 - 19 Nov 2021

Cited by 3 | Viewed by 1997

Abstract

This paper presents a 10 bit 100 MS/s asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) without calibration for industrial control system (ICS) applications. Several techniques are adopted in the proposed switching procedure to achieve better linearity, power and area efficiency. A single-side-fixed technique is utilized to reduce the number of capacitors; a parallel split capacitor array in combination with a partially thermometer coded technique can minimize the switching energy, improve speed, and decrease differential non-linearity (DNL). In addition, a compact timing-protection scheme is proposed to ensure the stability of the asynchronous SAR ADC. The proposed ADC is fabricated in a 28 nm CMOS process with an active area of 0.026 mm

^{2}

. At 100 MS/s, the ADC achieves a signal-to-noise-and-distortion ratio (SNDR) of 51.54 dB and a spurious free dynamic range (SFDR) of 55.12 dB with the Nyquist input. The measured DNL and integral non-linearity (INL) without calibration are +0.37/−0.44 and +0.48/−0.63 LSB, respectively. The power consumption is 1.1 mW with a supply voltage of 0.9 V, leading to a figure of merit (FoM) of 35.6 fJ/conversion-step. Full article

(This article belongs to the Special Issue Advances on Analog-to-Digital and Digital-to-Analog Converters)

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15 pages, 5840 KiB

Open AccessArticle

A Pipelined Noise-Shaping SAR ADC Using Ring Amplifier

by Juyong Lee, Seungjun Lee, Kihyun Kim and Hyungil Chae

Electronics 2021, 10(16), 1968; https://doi.org/10.3390/electronics10161968 - 15 Aug 2021

Cited by 2 | Viewed by 4335

Abstract

In this study, a pipelined noise-shaping successive-approximation register analog-to-digital converter (PLNS-SAR ADC) structure was proposed to achieve high resolution and to be free from comparator design requirements. The inter-stage amplifier and integrator of the PLNS-SAR ADC were implemented through a ring amplifier with high gain and speed. The ring amplifier was designed to improve power efficiency and be tolerant to process–voltage–temperature (PVT) variation, and uses a single loop common-mode feedback (CMFB) circuit. By processing residual signals with a single ring amplifier, power efficiency can be maximized, and a low-power system with 30% lower power consumption than that of a conventional PLNS-SAR ADC is implemented. With a high-gain ring amplifier, noise leakage is greatly suppressed, and a structure can be implemented that is tolerant of mismatches between the analog loop and digital correction filters. The measured signal to noise distortion ratio (SNDR) is 70 dB for a 5.15 MHz bandwidth (BW) at a 72 MS/s sampling rate (Fs) with an oversampling ratio (OSR) of 7, and the power consumption is 2.4 mW. The

{FoM}_{S, SNDR}

(= SNDR +

{10 \log}_{10}

BW/Power) is 163.5 dB. The proposed structure in this study can achieve high resolution and wide BW with good power efficiency, without a filter calibration process, through the use of a ring amplifier in the PLNS-SAR ADC. Full article

(This article belongs to the Special Issue Advances on Analog-to-Digital and Digital-to-Analog Converters)

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14 pages, 6313 KiB

Open AccessArticle

A Single-Amplifier Dual-Residue Pipelined-SAR ADC

by Min-Jae Seo

Electronics 2021, 10(4), 421; https://doi.org/10.3390/electronics10040421 - 09 Feb 2021

Cited by 3 | Viewed by 3265

Abstract

This work presents a 12 bit 200 MS/s dual-residue pipelined successive approximation registers (SAR) analog-to-digital converter (ADC) with a single open-loop residue amplifier (RA). By using the inherent characteristics of the SAR conversion scheme, the proposed ADC sequentially generates two residue levels from the single RA, which eliminates the need for inter-stage gain-matching calibration. To convert the sequentially generated the two residues, a capacitive interpolating SAR ADC (I-SAR ADC) is also proposed. The I-SAR ADC is very compact because it consists of the one comparator, a CDAC, and control logic like a conventional SAR ADC. In addition, the I-SAR ADC needs no static power dissipation for the residue interpolation. A prototype ADC fabricated in a 40 nm CMOS technology occupies an active area of 0.026 mm². At a 200 MS/s sampling-rate with the Nyquist input, the ADC achieves an SNDR (Signal-to-Noise distortion ratio) of 62.1 dB and 67.1 dB SFDR (Spurious-Free Dynamic Range), respectively. The total power consumed is 3.9 mW under a 0.9 V supply. Without any inter-stage mismatch calibration, the ADC achieve Walden Figure-of-Merit (FoM) of 19.0 fJ/conversion-step. Full article

(This article belongs to the Special Issue Advances on Analog-to-Digital and Digital-to-Analog Converters)

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16 pages, 2034 KiB

Open AccessArticle

Reference Power Supply Connection Scheme for Low-Power CMOS Image Sensors Based on Incremental Sigma-Delta Converters

by Luis Miguel Carvalho Freitas and Fernando Morgado-Dias

Electronics 2021, 10(3), 299; https://doi.org/10.3390/electronics10030299 - 27 Jan 2021

Cited by 3 | Viewed by 2630

Abstract

Modern Complementary Metal-Oxide-Semiconductor (CMOS) image sensors, aimed to target low-noise and fast digital outputs, are fundamentally based on column-parallel structures, jointly designed with oversampling column converters. The typical choice for the employed column converters is the incremental sigma-delta structures, which intrinsically perform the correlated multiple sampling, creating an averaging effect over the system thermal noise when used in conjunction with 4T-pinned pixels. However, these types of column converters are known to be power-hungry, especially if the imaging device needs to target high frame rate levels as well. In this sense, the aim of this paper was to address the excess of power dissipation problem that arises from image sensors while employing oversampling high-order incremental converters, by means of using a different connection scheme to supply and to drive the required reference signals across the image sensor on-chip column converters. The proposed connection scheme revealed to be fully functional with no unwanted artifacts in the imager output response, allowing it to avoid 20% to 50% of the power dissipation, relative to the classical on-chip references generation and driving method. Furthermore, this solution allows for a much less complicated and less crowded printed circuit board (PCB) system. Full article

(This article belongs to the Special Issue Advances on Analog-to-Digital and Digital-to-Analog Converters)

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15 pages, 6455 KiB

Open AccessArticle

A 12-bit 40-MS/s SAR ADC with Calibration-Less Switched Capacitive Reference Driver

by Hyungyu Ju, Sewon Lee and Minjae Lee

Electronics 2020, 9(11), 1854; https://doi.org/10.3390/electronics9111854 - 05 Nov 2020

Cited by 2 | Viewed by 3292

Abstract

This paper presents a switched capacitive reference driver (SCRD) with a low-energy switching scheme. In order to reduce the performance degradation resulting from a signal-dependent voltage drop in a capacitive reference driver (CRD) without increasing the capacitance (C_REF) of a CRD, the proposed SCRD utilizes the CRD for LSB conversion cycles. In MSB conversion cycles, a supply voltage is used as a reference voltage to save on area and power consumption. As such, the proposed SCRD significantly relaxes the required C_REF, and does not necessitate bit weight calibration or compensation requiring an auxiliary capacitor-based digital-to-analog converter (CDAC). To evaluate the proposed SCRD, a prototype 12-bit 40-MS/s SAR ADC is fabricated in a 65 nm CMOS process. With near Nyquist frequency, the measured spurious-free dynamic range (SFDR) of the SAR ADC with the SCRD is 80.6 dB, which is about a 16 dB improvement from the SFDR of a SAR ADC with a CRD only. Full article

(This article belongs to the Special Issue Advances on Analog-to-Digital and Digital-to-Analog Converters)

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