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Chips, Volume 2, Issue 1 (March 2023) – 4 articles

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26 pages, 3789 KiB  
Review
Bandpass Sigma–Delta Modulation: The Path toward RF-to-Digital Conversion in Software-Defined Radio
by Jose M. de la Rosa
Chips 2023, 2(1), 44-69; https://doi.org/10.3390/chips2010004 - 02 Mar 2023
Viewed by 2594
Abstract
This paper reviews the state of the art on bandpass ΣΔ modulators (BP-ΣΔMs) intended to digitize radio frequency (RF) signals. A priori, this is the most direct way to implement software-defined radio (SDR) systems since the analog/digital interface is [...] Read more.
This paper reviews the state of the art on bandpass ΣΔ modulators (BP-ΣΔMs) intended to digitize radio frequency (RF) signals. A priori, this is the most direct way to implement software-defined radio (SDR) systems since the analog/digital interface is placed closer to the antenna, thus reducing the analog circuitry and doing most of the signal processing in the digital domain. In spite of their higher programmability and scalability, RF BP-ΣΔM analog-to-digital converters (ADCs) require more energy to operate in the GHz range as compared with their low-pass (LP) counterparts. This makes conventional direct conversion receivers (DCRs) the commonplace approach due to their overall smaller energy consumption. This paper surveys some circuits and systems techniques which can make RF ADCs and SDR-based transceivers more efficient and feasible to be embedded in mobile terminals. Full article
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13 pages, 3582 KiB  
Article
Methodology for a Low-Power and Low-Circuit-Area 15-Bit SAR ADC Using Split-Capacitor Mismatch Compensation and a Dynamic Element Matching Algorithm
by William Bontems and Daniel Dzahini
Chips 2023, 2(1), 31-43; https://doi.org/10.3390/chips2010003 - 27 Feb 2023
Viewed by 2316
Abstract
This paper presents a design methodology for a low-power, low-chip-area, and high-resolution successive approximations register (SAR) analog-to-digital converter (ADC). The proposed method includes a segmented capacitive DAC (C-DAC) to reduce the power consumption and the total area. An embedded self-calibration algorithm based on [...] Read more.
This paper presents a design methodology for a low-power, low-chip-area, and high-resolution successive approximations register (SAR) analog-to-digital converter (ADC). The proposed method includes a segmented capacitive DAC (C-DAC) to reduce the power consumption and the total area. An embedded self-calibration algorithm based on a set of trimming capacitors was applied alongside a dynamic element matching (DEM) procedure to control the inherent linearity issues caused by the process mismatch. The SAR ADC and each additional algorithm were modeled in MATLAB to show their efficiency. Finally, a simple methodology was developed to allow for the fast estimation of signal-to-noise ratios (SNRs) without any FFT calculation. Full article
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11 pages, 4822 KiB  
Article
An Interface Platform for Robotic Neuromorphic Systems
by Nicola Russo, Haochun Huang, Eugenio Donati, Thomas Madsen and Konstantin Nikolic
Chips 2023, 2(1), 20-30; https://doi.org/10.3390/chips2010002 - 01 Feb 2023
Cited by 1 | Viewed by 2324
Abstract
Neuromorphic computing is promising to become a future standard in low-power AI applications. The integration between new neuromorphic hardware and traditional microcontrollers is an open challenge. In this paper, we present an interface board and a communication protocol that allows communication between different [...] Read more.
Neuromorphic computing is promising to become a future standard in low-power AI applications. The integration between new neuromorphic hardware and traditional microcontrollers is an open challenge. In this paper, we present an interface board and a communication protocol that allows communication between different devices, using a microcontroller unit (Arduino Due) in the middle. Our compact printed circuit board (PCB) links different devices as a whole system and provides a power supply for the entire system using batteries as the power supply. Concretely, we have connected a Dynamic Vision Sensor (DVS128), SpiNNaker board and a servo motor, creating a platform for a neuromorphic robotic system controlled by a Spiking Neural Network, which is demonstrated on the task of intercepting incoming objects. The data rate of the implemented interface board is 24.64 k symbols/s and the latency for generating commands is about 11ms. The complete system is run only by batteries, making it very suitable for robotic applications. Full article
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19 pages, 1733 KiB  
Article
Hybrid Inverter-Based Fully Differential Operational Transconductance Amplifiers
by Luís Henrique Rodovalho, Pedro Toledo, Farzad Mir and Farshad Ebrahimi
Chips 2023, 2(1), 1-19; https://doi.org/10.3390/chips2010001 - 06 Jan 2023
Cited by 2 | Viewed by 2559
Abstract
Inverter-based Operational Transconductance Amplifiers (OTAs) are versatile and friendly scalable analog circuit blocks. Especially for the new CMOS technological nodes, several recent applications have been extensively using them, ranging from Analog Front End (AFE) to analog-to-digital converters (ADC). This work tracks down the [...] Read more.
Inverter-based Operational Transconductance Amplifiers (OTAs) are versatile and friendly scalable analog circuit blocks. Especially for the new CMOS technological nodes, several recent applications have been extensively using them, ranging from Analog Front End (AFE) to analog-to-digital converters (ADC). This work tracks down the current advances in inverter-based OTAs design, comparing their basic fully differential structures, such as Nauta (N), Barthelemy (B), Vieru (V) and Mafredini (M) ones, and, in addition, mixing them up to propose new fully differential single-ended and two-stage hybrid versions. The new herein-proposed fully differential hybrid OTAs are the composition of Barthelemy/Nauta (B/N), Barthelemy/Manfredini (B/M), Nauta/Vieru (N/V), and Manfredini/Vieru (M/V) OTAs. All OTAs were designed using the same Global Foundries 180 nm open-source PDK and their performances are compared for post-layout simulations. Full article
(This article belongs to the Special Issue State-of-the-Art in Integrated Circuit Design)
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