Chips

15 pages, 3368 KiB

Open AccessArticle

A CMOS Voltage Reference with Output Voltage Doubling Using Modified 2T Topology

by Junyao Li and Pak Kwong Chan

Chips 2022, 1(3), 218-232; https://doi.org/10.3390/chips1030015 - 15 Dec 2022

Viewed by 2547

This paper presents an ultra-low power CMOS voltage reference which operates in the subthreshold region. Modified from the conventional 2T circuit, the proposed circuit is capable of generating higher output voltage by using the resistor subdivision. The design comprises a negative-threshold native NMOS [...] Read more.

This paper presents an ultra-low power CMOS voltage reference which operates in the subthreshold region. Modified from the conventional 2T circuit, the proposed circuit is capable of generating higher output voltage by using the resistor subdivision. The design comprises a negative-threshold native NMOS transistor as the current generator, a high-threshold PMOS transistor as the active load and an active voltage doubling network to generate the reference voltage. Implemented in TSMC 40 nm CMOS technology, the proposed circuit operates at a minimum supply of 0.65 V and consumes 5.5 nA. Under one sample simulation, the obtained T.C. is 16.64 ppm/°C and the nominal

V_{r e f}

is 489.6 mV (75.3% of

V_{d d m i n}

) for the temperature range from −20 °C to 80 °C. For Monte-Carlo simulation of 200 samples at room temperature, the average output voltage is 488 mV and the average T.C. is 29.6 ppm/°C whilst with the standard deviation of 13.26 ppm/°C. Finally, at room temperature, the proposed voltage reference has achieved a process sensitivity (σ/μ) of 3.9%, a line sensitivity of 0.51%/V and a power supply rejection of −45.5 dB and −76.3 dB at 100 kHz and 100 MHz. Compared to the representative prior-art works realized in the same technology and a similar supply current, the proposed circuit has offered the best 1-sampe T.C., the best average T.C. in multiple samples, the highest output voltage, the maximum output voltage per minimum supply voltage and the lowest process sensitivity in the output,

V_{r e f}

. Full article

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8 pages, 796 KiB

Open AccessCommunication

FPGA Prototyping of Web Service Using REST and SOAP Packages

by Chee Er Chang, Azhar Kassim Mustapha and Faisal Mohd-Yasin

Chips 2022, 1(3), 210-217; https://doi.org/10.3390/chips1030014 - 05 Dec 2022

Viewed by 1951

Abstract

This Communication reports on FPGA prototyping of an embedded web service that sends XML messages under two different packages, namely Simple Object Access Protocol (SOAP) and Representational State Transfer (REST). The request and response messages are communicated through a 100 Mbps local area [...] Read more.

This Communication reports on FPGA prototyping of an embedded web service that sends XML messages under two different packages, namely Simple Object Access Protocol (SOAP) and Representational State Transfer (REST). The request and response messages are communicated through a 100 Mbps local area network between a Spartan-3E FPGA board and washing machine simulator. The performances of REST-based and SOAP-based web services implemented on reconfigurable hardware are then compared. In general, the former performs better than the latter in terms of FPGA resource utilization (~12% less), message length (~57% shorter), and processing time (~4.5 μs faster). This work confirms the superiority of REST over SOAP for data transmission using reconfigurable computing, which paves the way for adoption of these low-cost systems for web services of consumer electronics such as home appliances. Full article

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19 pages, 14639 KiB

Open AccessArticle

Multi-Physics Fields Simulations and Optimization of Solder Joints in Advanced Electronic Packaging

by Boyan Yu and Yisai Gao

Chips 2022, 1(3), 191-209; https://doi.org/10.3390/chips1030013 - 17 Nov 2022

Cited by 1 | Viewed by 1803

Abstract

The endurability of solder joints in the ball-grid array (BGA) packaging is crucial to the functioning of the microelectronic system. To improve electronic packaging reliability, this paper is dedicated to numerically optimize solder joint array configuration and study the influence of multi-physical fields [...] Read more.

The endurability of solder joints in the ball-grid array (BGA) packaging is crucial to the functioning of the microelectronic system. To improve electronic packaging reliability, this paper is dedicated to numerically optimize solder joint array configuration and study the influence of multi-physical fields on solder joint reliability. The uniqueness of this study is that on the basis of temperature field and stress field, the electric field is added to realize the coupling simulation of three physical fields. In addition, the “Open Angle” is mathematically defined to describe the array configuration, and it was used to reveal the influence factors of solder joint fatigue, including stress, temperature, and current density. In the single solder joint model, the impacts of geometric shape and working conditions on the maximum value and distribution of these evaluation factors (stress, temperature, and current density) were investigated. Overall, the numerical investigation gives the optimal configuration, geometric shape, and working condition of solder joints, which benefits the design of endurable and efficient BGA packaging. Full article

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16 pages, 2527 KiB

Open AccessArticle

An Adaptive Downsampling FPGA-Based TDC Implementation for Time Measurement Improvement

by Evangelos Dikopoulos, Michael Birbas and Alexios Birbas

Chips 2022, 1(3), 175-190; https://doi.org/10.3390/chips1030012 - 08 Nov 2022

Cited by 2 | Viewed by 2284

Abstract

In this work, we present a compact “adaptive downsampling” method that mitigates the nonlinearity problems associated with FPGA-based TDCs that utilize delay lines. Additionally, this generic method allows for trade-offs between resolution, linearity, and resource utilization. Since nonlinearity is one of the predominant [...] Read more.

In this work, we present a compact “adaptive downsampling” method that mitigates the nonlinearity problems associated with FPGA-based TDCs that utilize delay lines. Additionally, this generic method allows for trade-offs between resolution, linearity, and resource utilization. Since nonlinearity is one of the predominant issues regarding delay lines in FPGA-based TDCs, combined with the fact that delay lines are utilized for a wide range of TDC architectures (not limited to the delay-line TDC), other implementations (e.g., Vernier or wave union TDCs), also in different FPGA devices, can directly benefit from the proposed adaptive method, with no need for either custom routing or complex tuning of the converter. Furthermore, implementation-related challenges regarding clock skew, measurement uncertainty, and the placement of the TDC are discussed and we also propose an experimental setup that utilizes only FPGA resources in order to characterize the converter. Although the TDC in this work was implemented in a Xilinx Virtex-6 device and was characterized under different operational modes, we successfully optimized the converter’s nonlinearity and resource utilization while retaining single-shot precision. The best performing (in terms of linearity) implementation reached

D N L_{r m s}

and

I N L_{r m s}

values of 0.30 LSB and 0.45 LSB, respectively, and the single-shot precision (

σ

) was 9.0 ps. Full article

(This article belongs to the Special Issue Smart IC Design and Sensing Technologies)

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3 pages, 210 KiB

Open AccessEditorial

Special Issue “Smart IC Design and Sensing Technologies”

by George Floros and Athanasios Tziouvaras

Chips 2022, 1(3), 172-174; https://doi.org/10.3390/chips1030011 - 20 Oct 2022

Viewed by 1349

Abstract

Smart sensing technologies and their inherent data-processing techniques have drawn considerable research and industrial attention in recent years. Recent developments in nanometer CMOS technologies have shown great potential to deal with the increasing demand of processing power that arises in these sensing technologies, [...] Read more.

Smart sensing technologies and their inherent data-processing techniques have drawn considerable research and industrial attention in recent years. Recent developments in nanometer CMOS technologies have shown great potential to deal with the increasing demand of processing power that arises in these sensing technologies, from IoT applications to complicated medical devices. Moreover, circuit implementation, which could be based on a full analog or digital approach or, in most cases, on a mixed-signal approach, possesses a fundamental role in exploiting the full capabilities of sensing technologies. In addition, all circuit design methodologies include the optimization of several performance metrics, such as low power, low cost, small area, and high throughput, which impose critical challenges in the field of sensor design. This Special Issue aims to highlight advances in the development, modeling, simulation, and implementation of integrated circuits for sensing technologies, from the component level to complete sensing systems. Full article

(This article belongs to the Special Issue Smart IC Design and Sensing Technologies)

22 pages, 1695 KiB

Open AccessPerspective

The Integrated Circuit Industry at a Crossroads: Threats and Opportunities

by Salvatore Pennisi

Chips 2022, 1(3), 150-171; https://doi.org/10.3390/chips1030010 - 06 Oct 2022

Cited by 3 | Viewed by 7728

Abstract

With the outbreak of the COVID-19 pandemic, the persistent chip shortage, war in Ukraine, and U.S.–China tensions, the semiconductor industry is at a critical stage. Only if it is capable of major changes, will it be able to sustain itself and continue to [...] Read more.

With the outbreak of the COVID-19 pandemic, the persistent chip shortage, war in Ukraine, and U.S.–China tensions, the semiconductor industry is at a critical stage. Only if it is capable of major changes, will it be able to sustain itself and continue to provide solutions for ongoing exponential technology growth. However, the war has undermined, perhaps definitively, a global order that urged the integration of markets above geopolitical divergences. Now that the trend seems to be reversed, the extent to which the costs of this commercial and technological decoupling can be absorbed and legitimized will have to be understood. Full article

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29 pages, 2028 KiB

Open AccessReview

An Overview of State-of-the-Art D-Band Radar System Components

by Pascal Stadler, Hakan Papurcu, Tobias Welling, Simón Tejero Alfageme and Nils Pohl

Chips 2022, 1(3), 121-149; https://doi.org/10.3390/chips1030009 - 21 Sep 2022

Cited by 6 | Viewed by 4115

Abstract

In this article, a literature study has been conducted including 398 radar circuit elements from 311 recent publications (mostly between 2010 and 2022) that have been reported mainly in the F-, D- and G-Band (80–200 GHz). This study is intended to give a [...] Read more.

In this article, a literature study has been conducted including 398 radar circuit elements from 311 recent publications (mostly between 2010 and 2022) that have been reported mainly in the F-, D- and G-Band (80–200 GHz). This study is intended to give a state-of-the-art comparison on the performance of the different technologies—RFCMOS, SiGe/BiCMOS and III–V semiconductor composites—regarding the most crucial circuit parameters of Voltage-Controlled Oscillators (VCO), Power Amplifiers (PA), Phase Shifters (PS), Low-Noise Amplifiers (LNA) and Mixers. The most common topologies of each circuit element as well as the differences between the technolgies will futher be laid out while reasoning their benefits. Since not all devices were derived solely from single device publications, necessary steps to yield as fairly a comparison as possible were taken. Results include the area and power efficiency in RFCMOS, superior noise and power performance in III–V semiconductors and a continuous compromise between efficiency and performance in SiGe. The most rarely published devices, being Mixers and PSs, in the given frequency range have also been identified to give incentive for further developments. Full article

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Chips, Volume 1, Issue 3 (December 2022) – 7 articles

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