# Finite Control Set Model Predictive Control (FCS-MPC) for Enhancing the Performance of a Single-Phase Inverter in a Renewable Energy System (RES)

^{1}

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## Abstract

**:**

## 1. Introduction

## 2. Control Strategies for Multilevel Inverter

#### 2.1. Conventional Modulation Strategies

#### 2.2. Model Predictive Control

_{0}and input voltage V

_{dc}, as these variables are the only parameters that can be measured. The consideration of measurements and switching states is of utmost importance when formulating equations. The mathematical and logical treatment of the latter can be accomplished within the framework of discrete time S. The model of the MLI is contingent upon the input DC-link voltage, capacitor voltages, and switching states. Once the prediction model is determined, it can be incorporated as the cost function [23]. The incorporation of weighting elements is crucial in the formulation of the cost function. The design of these entities is heuristically determined by analyzing the behavior of the goal variables. Additionally, the incorporation of additional control objectives, such as the reduction of switching frequency can be considered. Lastly, the FCS-MPC scheme is used to select and implement the best switching state for the inverter which is determined by the optimal cost function [24].

## 3. Single Phase Five-Level T-Type Topology

_{dc}, six switches S

_{1}–S

_{6}, and two bidirectional switches. An LC filter consisting of L

_{f}and C

_{f}is connected at the output terminal of the inverter to improve the output quality. The current flowing through the load R is i

_{g}. The structure of the T-type topology is given in the below Figure 4. The topology can produce five levels with a peak equal to the DC source magnitude. The switches S

_{1}, S

_{2}, S

_{3,}and S

_{4}block the voltage V

_{dc}, and the bidirectional switches S

_{5}and S

_{6}block 2 × 0.5V

_{dc}= V

_{dc}each. The upper and lower DC-link capacitors are designated as C

_{dc1}and C

_{dc2}. The topology can be extended to three or five phases with a common DC-link and similar operating principle. The switching states of the topology are given in Table 2 and visualized in Figure 5. The capacitors are charged and discharged and the states given in the table are represented by ↑ (charging) or ↓ (discharging). This affects the balance of the DC-link neutral point and must be considered in modulation, otherwise output and switch stresses will be drastically affected.

## 4. Implementation of FCS-MPC on Single Phase Five-Level T-Type Topology

#### 4.1. Implementation of FCS-MPC

_{c}

_{1,2}is the capacitor current, C

_{1,2}are the DC-link capacitance magnitudes, and v

_{c}

_{1,2}are the DC-link capacitor voltages. Now the filter inductor current i

_{f}can be represented as:

_{f}, v

_{cf}, and i

_{o}are the filter capacitor magnitude, filter capacitor voltage, and load current, respectively. Now the filter inductor current can be derived using the following relation:

_{i}and L

_{f}are the inverter terminal voltage and filter inductor magnitude respectively. The above equations need to be discretized using Euler’s forward transform to facilitate digital controller operation. Therefore, the sampling time needs to be selected in accordance with the digital controller’s capabilities and performance requirements. Similarly, the static switching model of the inverter structure can be formulated with the positive load terminal voltage v

_{a}as:

_{b}as:

_{1}through S

_{6}represent the switching functions of the six switches under all conditions, and the cost function needs to be determined. By careful selection of states, neutral-point balancing is ensured without the need for real-time balancing control in the FCS-MPC algorithm [13]. The system block diagram is depicted in Figure 7.

#### 4.2. Cost Function and Flowchart

_{s}and st is the switching transition which is given by

Algorithm 1 Algorithm for implementing the cost function. |

Start |

1. Initialize counter i = 0 |

2. Continuously measure the v_{c}_{1,2}, i_{f}, v_{cf} and v_{i} |

3. Compute Equations (4) and (5) |

4. Evaluate Equation (6) to compute the cost function g based on the values of Vc* and Vc. |

5. Use optimization techniques to find the optimal switching state that minimizes g. |

6. Iterate for switching states T_{1}–T_{9} and check whether the optimal state is obtained or not. |

7. If yes, continue with step 7; else repeat step 6. |

8. Apply switching state with minimum g. |

9. S (k) = S_{g_optimum} |

End |

_{1}–S

_{6}is depicted in Figure 9. The figure indicates that S

_{5}and S

_{6}have substantially lower switching losses than other switches. Therefore, the frequency penalization weighing factor w is to be applied only on switches S

_{1}through S

_{4}. Previously, several works have investigated weighing factor tuning against varied objectives. Auto-tuning and factor elimination of weighing factors have been observed in works such as [15]. Optimal weighing factor determination can be solved online or offline.

_{1}–S

_{4}only, the computational load is reduced. Figure 10 shows the transient response of FCS-MPC without weighing factor with a 100% variation of reference voltage. Then, a frequency penalization factor of 0.5 per unit is employed. The resulting loss distribution and dynamic response are given in Figure 11 and Figure 12 respectively. Evidently, the average losses are reduced for S

_{1}to S

_{6}.

## 5. Hardware Implementation

#### 5.1. Components Used

- Embedded Controller: A 32-bit digital signal processor TI-C2000-F28379D has been used here as it can work at a sample time appropriate for real-time FCS-MPC computation on the prototype. The controller can be programmed through Code-Composer Studio© or through code generation. For rapid development and verification, code generation is applied in this work using MATLAB R2022b-Simulink Embedded Coder. The code generation process involves a dynamic model of the system using compatible blocks in Simulink. The code generation process allows real-time tuning in external mode as well as calibration of sensor modules to allow shorter development durations. Since FCS-MPC works without a modulator, the PWM modules of the controller cannot be employed for the gating signals. GPIO pins are used for the gating signals which do not have an inherent deadband feature unlike the epwm module, hence hardware deadband through gate drivers has been provided;
- Gate Driver Unit: Gate drivers based on the TLP250 optocoupler and isolated power supply IC (integrated circuit) are provided to drive the gate of the MOSFET used in the prototype. These drivers can amplify the 3.3 V signals provided by the controller as well as provide isolation. A special configuration with resistor R
_{1}= 100 Ω, R_{2}= 5 Ω has been used to provide the hardware deadband which prevents the shoot-through of complementary MOSFET pairs. Since the MOSFET switching time decreases with increasing gate resistance, a fast-switching diode D_{1}(1N914) which can pass the switching signals with low propagation delay has been incorporated in the circuit as shown in Figure 14a. This configuration provides increased turn-on time and decreased turn-off time, hence preventing the overlap between the higher and lower side MOSFETs as shown in Figure 14b. The prototype of the gate driver unit used in this experiment is shown in Figure 14c. Six such gate driver units are used in the inverter and one MCWI03-48S15 isolated power ICs are employed in each unit; - DC-link capacitors: Two DC-link capacitors are used in the converter for the purpose of dc-bus. The capacitors facilitate the energy storage to allow DC power from the DC source to be converted to pulsating AC power. The capacitor needs to transmit only a fraction of the load current. The capacitors used are of magnitude 1000 µF and rated 250 V;
- Output Filter: For the five-level inverter, the filter inductor sizing can be performed as$${L}_{f}\ge \frac{{V}_{DC}}{16\times {f}_{sw}\times \u2206{I}_{p-p}}$$
_{DC}, f_{sw}, and ∆I_{(p−p)}are the dc-bus voltage, switching frequency, and allowed peak-to-peak current ripple respectively. Considering a bus voltage of 400 V, average switching frequency of 10 kHz, and current ripple of 1 A, the minimum inductance is 2.5 mH. A 2.8 mH inductor is chosen to meet the design criterion.

_{crss}of 2000 Hz, we obtain a minimal capacitance of 2.26 µF. However, a capacitor valued at 3.3 µF of Bipolar film type has been selected.

- 5.
- Bleeder resistor selection: To initiate the converter operation, the DC-link capacitors are charged by a single regulated DC power supply. The regulation of the power supply eliminates the need for any pre-charging resistors. However, once the converter operation is terminated, the dc-bus capacitances must be discharged for safety concerns. Bleeder resistors are placed in parallel with the capacitors C
_{dc1}and C_{dc2}; - 6.
- to facilitate their discharging. The magnitudes of these resistors are 510 kΩ each. Six resistors, in parallel combinations of three series resistors are each placed in parallel with each dc-bus capacitor;
- 7.
- Current and Voltage Sensors: The converter needs two current sensors to measure the filter and load current, as well as three voltage sensors for the measurement of filter, load, and capacitor voltages. The current sensors are designed using the ACS712 hall-effect current sensor IC. The filter capacitor for the current sense is chosen as 100 nF. For the voltage sensor, non-inverting operational amplifiers (OP-AMPs) are employed to provide step-down gain, offset and isolation. It has three stages namely, the gain stage, the positive offset stage, and the isolation stage. General-purpose Op-Amps are used for designing the voltage sensors which are powered by a ±15 V supply. The gain stage steps the high voltage to a range between 0–1.65 V. The offset stage adds a positive bias such that the reading is positive for even the negative values for measured voltage. The final isolation stage facilitates galvanic isolation between the MCU ground and the measurement ground through an isolation amplifier. Thus, a value from −300 V to +300 V is scaled to 0 to 3.3 V for data acquisition by the MCU;
- 8.
- EMI capacitors: EMI (electromagnetic interference) capacitors are needed to alleviate high-frequency noise due to the dv/dt and di/dt transitions which can affect converter output and the gating signals. The capacitors are placed across every leg. Six 150 nF 630V-rated, Film Bipolar capacitors are employed for this purpose;
- 9.
- MOSFET: K2371 MOSFET is used as the switching device for the power stage. The MOSFET can block a voltage of 500 V and transmit a current up to 25 A.

#### 5.2. Hardware Setup

#### 5.3. Hardware Result

_{1}, S

_{2}, S

_{3}, S

_{4}, S

_{5}and S

_{6}are given in Figure 19. Note that the inclusion of the switching constraint limits the switching frequency below 10 kHz. The pulse peak is 15 V. The waveform has been recorded on the digital storage oscilloscope. The inverter has been tested with and without the output filter. The inverter output voltage without the LC filter is shown in Figure 20, having a peak voltage of 150 V. The lack of an LC filter gives rise to a pulsed waveform with significant ripples as visible in Figure 20a with its zoomed view in Figure 20b. The switch S

_{1}undergoes an open circuit fault, but the converter recovers the output although with reduced peak voltage. Fault-tolerant operation is given in Figure 20c. To improve the quality of the output voltage, an LC filter has been connected to the output terminal. The load voltage with the inclusion of an LC filter is shown in Figure 21a,b. Evidently, the load voltage is close to 110 V rms and 60 Hz, thus the standard operation of the inverter is achieved. The FFT window and spectrum of the inverter with LC filter are given in Figure 21c. The THD is 3.92% which meets IEEE-519 standards [31]. Figure 21d lists the harmonic content distribution. Visibly, the concentration of harmonic content is equally distributed across all frequencies, which is the expected result in FCS-MPC unlike SPWM, in which the harmonic magnitudes are concentrated across particular frequencies.

## 6. Conclusions

## 7. Future Work

- Optimizing the sample time, switching frequency, and dynamic response through an application-centric approach and varied mission profiles;
- More precise reliability computation methods while incorporating failure mechanisms and destructive tests under emulated real-environment conditions;
- Real-time optimization of weighing factors and novel optimization algorithms to solve the non-linear problem of state selection;
- Integration with wide-bandgap components and faster processors;
- Design of gate drivers and deadband compensation considering wide-bandgap and FCS-MPC.

## Author Contributions

## Funding

## Data Availability Statement

## Conflicts of Interest

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**Figure 3.**Block diagram of an FCS-MPC [21].

**Figure 5.**Different switching states of the topology. (

**a**) T

_{1}; (

**b**) T

_{2}; (

**c**) T

_{3}; (

**d**) T

_{4}; (

**e**) T

_{5}; (

**f**) T

_{6}; (

**g**) T

_{7}; (

**h**) T

_{8}; (

**i**) T

_{9}.

**Figure 13.**Load voltage under different loading conditions. (

**a**) Uniform load; (

**b**) dynamic loading with load changing from R/2 to R; (

**c**) dynamic loading with load changing from R to R/2; (

**d**) harmonic profile of the output load voltage.

**Figure 14.**Hardware deadband implementation: (

**a**) Block diagram representation; (

**b**) deadband realization; (

**c**) hardware of the gate driver unit.

**Figure 19.**Switching signals to all the switches: (

**a**) S

_{1}gating; (

**b**) S

_{2}gating; (

**c**) S

_{3}gating; (

**d**) S

_{4}gating; (

**e**) S

_{5}gating; (

**f**) S

_{6}gating.

**Figure 20.**Inverter output voltage. (

**a**) Without LC filter; (

**b**) without LC filter (zoomed view); (

**c**) post-fault transition.

**Figure 21.**Load voltage. (

**a**) With LC filter; (

**b**) with LC filter (zoomed view); (

**c**) with FFT spectrum; (

**d**) harmonic content.

**Figure 22.**Output load voltage under dynamic loading conditions. Load voltage under different loading conditions. (

**a**) Uniform load; (

**b**) dynamic loading with load changing from R/2 to R; (

**c**) dynamic loading with load changing from R to R/2.

Description | [25] | [26] | [27] | [28] | [29] | Proposed |
---|---|---|---|---|---|---|

Topology | T-type double H-bridge | Transformerless T--Type NPC | Full-bridge | NPC | T-type | T-type |

Control Approach | NLC | Combined SVM and hysteresis current control | Dead-beat based FCS-MPC | Artificial neural network-based FCS-MPC | Hybrid ZVS boundary condition mode | FCS-MPC |

Number of Switch Count | 9 | 4 | 4 | 4 | 6 | 6 |

Number of DC Sources | 3 | 1 | 1 | 1 | 1 | 1 |

Number of Output Level | 15 | 3 | 3 | 3 | 3 | 5 |

Complexity | Depends on the output level | Difficult | Difficult | Complex | Complex | Easy |

Switching Frequency Control | Fixed switching frequency | Fixed switching frequency | Fixed switching frequency | Switching frequency control varies over time and is uncontrollable | Switching frequency control can be added | Switching frequency control can be added |

Amplitude | S_{1} | S_{2} | S_{3} | S_{4} | S_{5} | S_{6} | C_{dc1} | C_{dc2} | State |
---|---|---|---|---|---|---|---|---|---|

V_{dc} | on | off | off | on | off | off | no effect | no effect | T_{1} |

0.5 V_{dc} | on | off | off | off | off | on | ↑ | ↓ | T_{2} |

off | off | off | on | on | off | ↓ | ↑ | T_{3} | |

Zero | off | off | off | off | on | on | no effect | no effect | T_{4} |

off | on | off | on | off | off | no effect | no effect | T_{5} | |

on | off | on | off | off | off | no effect | no effect | T_{6} | |

−0.5 V_{dc} | off | off | on | off | on | off | ↓ | ↑ | T_{7} |

off | on | off | off | off | on | ↑ | ↓ | T_{8} | |

−V_{dc} | off | on | on | off | off | off | no effect | no effect | T_{9} |

Specification | Value |
---|---|

Sampling Time | 10 µs |

Load R | 60 Ω |

LC Filter L_{f} C_{f} | 3 mH, 15 µF |

DC Source V_{dc} | 700 V |

Fundamental frequency | 60 Hz |

MOSFET | C2M0025120D |

Ambient temperature | 55 °C |

Equipment/Components | Quantity | Specification |
---|---|---|

Digital Signal Processor | 1 | TI, 32-bit, C2000-F28379D |

Gate Driver unit | 6 | TLP 250H, MCWI03-48S15 |

Oscilloscope | 1 | Tektronix MDO3024 |

DC Link Capacitor C_{dc1} and C_{dc2} | 2 | 1000 µF, 250 V |

Output Filter (Inductor) L_{f} | 1 | 2.8 mH |

Output Filter (Capacitor) C_{f} | 1 | 3.3 µF, Bipolar film-type |

Voltage sensor unit | 3 | Op-Amp |

Current sensor unit | 2 | ACS712-IC |

Laptop | 1 | HP, Victus |

DC power supply | 1 | GWINSTEK, GPS-4303 |

DC power supply | 1 | CHROMA, 62100H |

MOSFET | 8 | K2371 |

Parameters | Specification |
---|---|

Fundamental frequency | 60 Hz |

DC Bus voltage | 155 V (Chroma 62100H) |

Load R | 60 Ω |

Load voltage objective | 110 V rms |

Sample Time | 10 µS |

Weighing factor w | 0.1 |

Parameters | Value |
---|---|

Load R | 60 Ω |

Loading conditions. | Uniform load Dynamic load (R/2-R, R-R/2) |

Inverter output voltage | 150 V (peak voltage) |

Load voltage | 110 V (constant), 60 Hz |

THD | 3.92% |

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## Share and Cite

**MDPI and ACS Style**

Lin, C.-H.; Farooqui, S.A.; Liu, H.-D.; Huang, J.-J.; Fahad, M.
Finite Control Set Model Predictive Control (FCS-MPC) for Enhancing the Performance of a Single-Phase Inverter in a Renewable Energy System (RES). *Mathematics* **2023**, *11*, 4553.
https://doi.org/10.3390/math11214553

**AMA Style**

Lin C-H, Farooqui SA, Liu H-D, Huang J-J, Fahad M.
Finite Control Set Model Predictive Control (FCS-MPC) for Enhancing the Performance of a Single-Phase Inverter in a Renewable Energy System (RES). *Mathematics*. 2023; 11(21):4553.
https://doi.org/10.3390/math11214553

**Chicago/Turabian Style**

Lin, Chang-Hua, Shoeb Azam Farooqui, Hwa-Dong Liu, Jian-Jang Huang, and Mohd Fahad.
2023. "Finite Control Set Model Predictive Control (FCS-MPC) for Enhancing the Performance of a Single-Phase Inverter in a Renewable Energy System (RES)" *Mathematics* 11, no. 21: 4553.
https://doi.org/10.3390/math11214553