Electronics

20 pages, 1249 KiB

Open AccessArticle

An Image Compression Method for Video Surveillance System in Underground Mines Based on Residual Networks and Discrete Wavelet Transform

by Fan Zhang, Zhichao Xu, Wei Chen, Zizhe Zhang, Hao Zhong, Jiaxing Luan and Chuang Li

Electronics 2019, 8(12), 1559; https://doi.org/10.3390/electronics8121559 - 17 Dec 2019

Cited by 12 | Viewed by 3444

Abstract

Video surveillance systems play an important role in underground mines. Providing clear surveillance images is the fundamental basis for safe mining and disaster alarming. It is of significance to investigate image compression methods since the underground wireless channels only allow low transmission bandwidth. [...] Read more.

Video surveillance systems play an important role in underground mines. Providing clear surveillance images is the fundamental basis for safe mining and disaster alarming. It is of significance to investigate image compression methods since the underground wireless channels only allow low transmission bandwidth. In this paper, we propose a new image compression method based on residual networks and discrete wavelet transform (DWT) to solve the image compression problem. The residual networks are used to compose the codec network. Further, we propose a novel loss function named discrete wavelet similarity (DW-SSIM) loss to train the network. Because the information of edges in the image is exposed through DWT coefficients, the proposed network can learn to preserve the edges better. Experiments show that the proposed method has an edge over the methods being compared in regards to the peak signal-to-noise ratio (PSNR) and structural similarity (SSIM), particularly at low compression ratios. Tests on noise-contaminated images also demonstrate the noise robustness of the proposed method. Our main contribution is that the proposed method is able to compress images at relatively low compression ratios while still preserving sharp edges, which suits the harsh wireless communication environment in underground mines. Full article

(This article belongs to the Special Issue Deep Learning Applications with Practical Measured Results in Electronics Industries)

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17 pages, 4777 KiB

Open AccessArticle

Angle of Arrival Passive Location Algorithm Based on Proximal Policy Optimization

by Yao Zhang, Zhongliang Deng and Yuhui Gao

Electronics 2019, 8(12), 1558; https://doi.org/10.3390/electronics8121558 - 17 Dec 2019

Cited by 10 | Viewed by 3561

Abstract

Location technology is playing an increasingly important role in urban life. Various active and passive wireless positioning technologies for mobile terminals have attracted research attention. However, positioning signals experience serious interference in high-density residential areas or in the interior of large buildings. The [...] Read more.

Location technology is playing an increasingly important role in urban life. Various active and passive wireless positioning technologies for mobile terminals have attracted research attention. However, positioning signals experience serious interference in high-density residential areas or in the interior of large buildings. The main type of interference is that caused by non-line-of-sight (NLOS) propagation. In this paper, we present a new method for optimizing the angle of arrival (AOA) measurement to obtain high accuracy location results based on proximal policy optimization (PPO). PPO is a new family of policy gradient methods for reinforcement learning, which can be used to adjust the sampling data under different environments using stochastic gradient ascent. Therefore, PPO can correct the NLOS propagation errors to produce a clear AOA measurement data set without building an offline fingerprinting database. Then, we used the least square method to calculate the location. The simulation result shows that the AOA passive location algorithm based on PPO produced more accurate location information. Full article

(This article belongs to the Section Microwave and Wireless Communications)

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15 pages, 6378 KiB

Open AccessArticle

Tri-polarized Sparse Array Design for Mutual Coupling Reduction in Direction Finding and Polarization Estimation

by Shuli Shi, Yougen Xu, Junpeng Zhuang, Kang Zhao, Yulin Huang and Zhiwen Liu

Electronics 2019, 8(12), 1557; https://doi.org/10.3390/electronics8121557 - 17 Dec 2019

Cited by 5 | Viewed by 2539

Abstract

Multi-polarized antenna arrays have the ability to provide both the direction and polarization information of the incident signals, which is important in radar, sonar, wireless communication, remote sensing, and so on. In this paper, a diversely polarized linear array of sparsely located but [...] Read more.

Multi-polarized antenna arrays have the ability to provide both the direction and polarization information of the incident signals, which is important in radar, sonar, wireless communication, remote sensing, and so on. In this paper, a diversely polarized linear array of sparsely located but identically oriented tri-polarized vector antennas (VAs) is designed for estimating the direction-of-arrival (DOA) and polarization parameters of the incident signals in the presence of antenna mutual coupling (MC). In order to reduce the inter-VA MC, a new type of sparse array geometry is proposed, wherein the minimum inter-VA spacing is constrained to be no less than one signal wavelength. Considering the intra-VA MC effect, a full-wave electromagnetic simulation is introduced to fit the manifold vector of an isolated VA. Based on the sparse VA array, a polarimetric subspace scheme is proposed for DOA and polarization estimation. When the knowledge about the intra-VA MC is a priori unavailable, an algebraic polarimetric blind scheme is also provided for DOA estimation. Computer simulations and real-world experiments (using an S-band 24-channel tri-polarized array system) validate the efficacy of the designed array geometry along with the parameter estimation methods. Full article

(This article belongs to the Special Issue Recent Advances in Array Antenna and Array Signal Processing)

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19 pages, 9486 KiB

Open AccessArticle

Pure Sinusoidal Output Single-Phase Current-Source Inverter with Minimized Switching Losses and Reduced Output Filter Size

by Eka Rakhman Priandana and Toshihiko Noguchi

Electronics 2019, 8(12), 1556; https://doi.org/10.3390/electronics8121556 - 17 Dec 2019

Cited by 5 | Viewed by 3732

Abstract

This paper proposes a novel single-phase current-source inverter that generates a pure sinusoidal waveform with minimized switching losses and using a small-size output filter capacitor. The proposed method is investigated by incorporating a conventional multilevel current-source inverter with a linear amplifier. The conventional [...] Read more.

This paper proposes a novel single-phase current-source inverter that generates a pure sinusoidal waveform with minimized switching losses and using a small-size output filter capacitor. The proposed method is investigated by incorporating a conventional multilevel current-source inverter with a linear amplifier. The conventional multilevel technique uses fundamental switching frequency instead of using high-switching frequency modulation for the H-bridge circuit. The linear amplifier such as class-A or class-D types has a function to reform the staircase waveform generated by the multilevel inverter into a pure sinusoidal by using superimposition technique. As a result, pure sinusoidal output current is generated with a small ripple and the system only requires a small output filter capacitor for smoothing the waveform. Based on the simulation and experimental results, the proposed system presents not only the optimal configuration, but also an option as to whether to obtain excellent power efficiency or very low output harmonic. Implications of the results and future research directions are also presented. Full article

(This article belongs to the Special Issue Multilevel Converters)

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36 pages, 13854 KiB

Open AccessArticle

TLS-VaD: A New Tool for Developing Centralized Link-Scheduling Algorithms on the IEEE802.15.4e TSCH Network

by Iman Hedi Santoso, Kalamullah Ramli and Suryadi M.T.

Electronics 2019, 8(12), 1555; https://doi.org/10.3390/electronics8121555 - 17 Dec 2019

Viewed by 3123

Abstract

A simulator plays an important role in network protocol research, as it enables researchers to develop protocols more flexibly. Many simulators have been developed to support research in this field, including NS-2, NS-3, OPNET, OMNeT, and Cooja. Although, as a research support tools, [...] Read more.

A simulator plays an important role in network protocol research, as it enables researchers to develop protocols more flexibly. Many simulators have been developed to support research in this field, including NS-2, NS-3, OPNET, OMNeT, and Cooja. Although, as a research support tools, NS3 and Cooja have already been equipped with an Internet of things (IoT) module, their support for research on IoT centralized scheduling is still limited. Therefore, this study is aimed to develop a tool for IoT centralized scheduling research, where the IoT technology is based on the IEEE802.15.4e time synchronized channel hopping (TSCH) standard. The tool is called the TSCH Link-Scheduling visualization and data processing (TLS-VaD). The results of validity tests show that TLS-VaD works well; therefore, this tool can be used in the performance measurement of centralized scheduling algorithms on TSCH networks. As an example of the application, this research used TLS-VaD to test the performance of three scheduling algorithms: Iman Ramli Bursty Transmission Scheduling Algorithm (IRByTSA), first top scheduling algorithm (FTSA), and first leaf scheduling algorithm (FLSA). The test results using TLS-VaD shows that IRByTSA had better performance compared to FLSA and FTSA, because it saved more power and was able to generate scheduling decisions relatively quickly. Full article

(This article belongs to the Special Issue IoT Services, Applications, Platform, and Protocols)

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13 pages, 2544 KiB

Open AccessArticle

Simultaneous Decoding of Eccentricity and Direction Information for a Single-Flicker SSVEP BCI

by Jingjing Chen, Alexander Maye, Andreas K. Engel, Yijun Wang, Xiaorong Gao and Dan Zhang

Electronics 2019, 8(12), 1554; https://doi.org/10.3390/electronics8121554 - 17 Dec 2019

Cited by 16 | Viewed by 2742

Abstract

The feasibility of a steady-state visual evoked potential (SSVEP) brain–computer interface (BCI) with a single-flicker stimulus for multiple-target decoding has been demonstrated in a number of recent studies. The single-flicker BCIs have mainly employed the direction information for encoding the targets, i.e., different [...] Read more.

The feasibility of a steady-state visual evoked potential (SSVEP) brain–computer interface (BCI) with a single-flicker stimulus for multiple-target decoding has been demonstrated in a number of recent studies. The single-flicker BCIs have mainly employed the direction information for encoding the targets, i.e., different targets are placed at different spatial directions relative to the flicker stimulus. The present study explored whether visual eccentricity information can also be used to encode targets for the purpose of increasing the number of targets in the single-flicker BCIs. A total number of 16 targets were encoded, placed at eight spatial directions, and two eccentricities (2.5° and 5°) relative to a 12 Hz flicker stimulus. Whereas distinct SSVEP topographies were elicited when participants gazed at targets of different directions, targets of different eccentricities were mainly represented by different signal-to-noise ratios (SNRs). Using a canonical correlation analysis-based classification algorithm, simultaneous decoding of both direction and eccentricity information was achieved, with an offline 16-class accuracy of 66.8 ± 16.4% averaged over 12 participants and a best individual accuracy of 90.0%. Our results demonstrate a single-flicker BCI with a substantially increased target number towards practical applications. Full article

(This article belongs to the Special Issue The Challenges in Brain-Computer Interface (BCI) - toward Practical BCI)

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9 pages, 8860 KiB

Open AccessArticle

Simulation and Result Analysis of Split Gate Resurf Stepped Oxide UMOFSET with Floating Electrode for Improved Performance

by Runze Chen, Lixin Wang, Naixia Jiu, Hongkai Zhang and Min Guo

Electronics 2019, 8(12), 1553; https://doi.org/10.3390/electronics8121553 - 17 Dec 2019

Cited by 2 | Viewed by 3596

Abstract

In this study, a split-gate resurf stepped oxide with a floating electrode (FSGRSO) UMOSFET has been proposed. The source in the trench is divided into two electrodes, namely: the upper electrode and the lower electrode. The upper one is the floating electrode, which [...] Read more.

In this study, a split-gate resurf stepped oxide with a floating electrode (FSGRSO) UMOSFET has been proposed. The source in the trench is divided into two electrodes, namely: the upper electrode and the lower electrode. The upper one is the floating electrode, which redistributes the electric potential vertically, and improves the breakdown voltage and figure of merit (FOM). The breakdown (BV) and FOM of the FSGRSO UMOSFET have been improved up to 27.3% and 62.7%, respectively, compared with the SGRSO UMOSFET, according to the simulation results. Full article

(This article belongs to the Section Microelectronics)

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29 pages, 1433 KiB

Open AccessArticle

A Lightweight Blockchain Based Framework for Underwater IoT

by Md Ashraf Uddin, Andrew Stranieri, Iqbal Gondal and Venki Balasurbramanian

Electronics 2019, 8(12), 1552; https://doi.org/10.3390/electronics8121552 - 16 Dec 2019

Cited by 44 | Viewed by 6532

Abstract

The Internet of Things (IoT) has facilitated services without human intervention for a wide range of applications, including underwater monitoring, where sensors are located at various depths, and data must be transmitted to surface base stations for storage and processing. Ensuring that data [...] Read more.

The Internet of Things (IoT) has facilitated services without human intervention for a wide range of applications, including underwater monitoring, where sensors are located at various depths, and data must be transmitted to surface base stations for storage and processing. Ensuring that data transmitted across hierarchical sensor networks are kept secure and private without high computational cost remains a challenge. In this paper, we propose a multilevel sensor monitoring architecture. Our proposal includes a layer-based architecture consisting of Fog and Cloud elements to process and store and process the Internet of Underwater Things (IoUT) data securely with customized Blockchain technology. The secure routing of IoUT data through the hierarchical topology ensures the legitimacy of data sources. A security and performance analysis was performed to show that the architecture can collect data from IoUT devices in the monitoring region efficiently and securely. Full article

(This article belongs to the Special Issue Blockchain and IoT Enabled Smart Grids)

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16 pages, 1714 KiB

Open AccessArticle

A 3GSps 12-bit Four-Channel Time-Interleaved Pipelined ADC in 40 nm CMOS Process

by Jianwen Li, Xuan Guo, Jian Luan, Danyu Wu, Lei Zhou, Yinkun Huang, Nanxun Wu, Hanbo Jia, Xuqiang Zheng, Jin Wu and Xinyu Liu

Electronics 2019, 8(12), 1551; https://doi.org/10.3390/electronics8121551 - 16 Dec 2019

Cited by 8 | Viewed by 3428

Abstract

This paper presents a four-channel time-interleaved 3GSps 12-bit pipelined analog-to-digital converter (ADC). The combination of master clock sampling and delay-adjusting is adopted to remove the time skew due to channel mismatches. An early comparison scheme is used to minimize the non-overlapping time, where [...] Read more.

This paper presents a four-channel time-interleaved 3GSps 12-bit pipelined analog-to-digital converter (ADC). The combination of master clock sampling and delay-adjusting is adopted to remove the time skew due to channel mismatches. An early comparison scheme is used to minimize the non-overlapping time, where a custom-designed latch is developed to replace the typical non-overlapping clock generator. By using the dither capacitor to generate an equivalent direct current input, a zero-input-based calibration is developed to correct the capacitor mismatch and inter-stage gain error. Fabricated in a 40 nm CMOS process, the ADC achieves a signal-to-noise-and-distortion ratio (SNDR) of 57.8 dB and a spurious free dynamic range (SFDR) of 72 dB with a 23 MHz input tone. It can achieve an SNDR above 52.3 dB and an SFDR above 61.5 dB across the entire first Nyquist zone. The differential and integral nonlinearities are −0.93/+0.73 least significant bit (LSB) and −2.8/+4.3 LSB, respectively. The ADC consumes 450 mW powered at 1.8V, occupies an active area of 3 mm × 1.3 mm. The calculated Walden figure of merit reaches 0.44 pJ/step. Full article

(This article belongs to the Section Circuit and Signal Processing)

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11 pages, 2743 KiB

Open AccessArticle

Device Design Assessment of GaN Merged P-i-N Schottky Diodes

by Yuliang Zhang, Xing Lu and Xinbo Zou

Electronics 2019, 8(12), 1550; https://doi.org/10.3390/electronics8121550 - 16 Dec 2019

Cited by 8 | Viewed by 5459

Abstract

Device characteristics of GaN merged P-i-N Schottky (MPS) diodes were evaluated and studied via two-dimensional technology computer-aided design (TCAD) after calibrating model parameters and critical electrical fields with experimental proven results. The device’s physical dimensions and drift layer concentration were varied to study [...] Read more.

Device characteristics of GaN merged P-i-N Schottky (MPS) diodes were evaluated and studied via two-dimensional technology computer-aided design (TCAD) after calibrating model parameters and critical electrical fields with experimental proven results. The device’s physical dimensions and drift layer concentration were varied to study their influence on the device’s performance. Extending the inter-p-GaN region distance or the Schottky contact portion could enhance the forward conduction capability; however, this leads to compromised electrical field screening effects from neighboring PN junctions, as well as reduced breakdown voltage. By reducing the drift layer background concentration, a higher breakdown voltage was expected for MPSs, as a larger portion of the drift layer itself could be depleted for sustaining vertical reverse voltage. However, lowering the drift layer concentration would also result in a reduction in forward conduction capability. The method and results of this study provide a guideline for designing MPS diodes with target blocking voltage and forward conduction at a low bias. Full article

(This article belongs to the Special Issue Nitride Semiconductors Revolution: Material, Devices and Applications)

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4 pages, 142 KiB

Open AccessEditorial

Cooperative, Connected and Automated Mobility (CCAM): Technologies and Applications

by Joaquim Ferreira

Electronics 2019, 8(12), 1549; https://doi.org/10.3390/electronics8121549 - 16 Dec 2019

Cited by 2 | Viewed by 2521

Abstract

The advent of cooperative connected and automated mobility (CCAM) has the potential to fundamentally change the mobility paradigm towards mobility as a service, contributing to more safe, efficient and comfortable transportation systems [...] Full article

(This article belongs to the Special Issue Cooperative Connected and Automated Mobility (CCAM): Technologies and Applications)

16 pages, 4109 KiB

Open AccessArticle

Design and Development of MIMO Antennas for WiGig Terminals

by Sultan Shoaib, Nosherwan Shoaib, Riqza Y. Y. Khattak, Imran Shoaib, Masood Ur Rehman and Xiaodong Yang

Electronics 2019, 8(12), 1548; https://doi.org/10.3390/electronics8121548 - 16 Dec 2019

Cited by 7 | Viewed by 3785

Abstract

This article presents a design for high-gain MIMO antennas with compact geometry. The proposed design is composed of four antennas in MIMO configuration, wherein, each antenna is made up of small units of microstrip patches. The overall geometry is printed on the top [...] Read more.

This article presents a design for high-gain MIMO antennas with compact geometry. The proposed design is composed of four antennas in MIMO configuration, wherein, each antenna is made up of small units of microstrip patches. The overall geometry is printed on the top layer of the substrate, i.e., Rogers RT-5880 with permittivity of 2.2, permeability of 1.0, dielectric loss of 0.0009, and depth of 0.508 mm. The proposed design covers an area of 29.5 × 61.4 mm², wherein each antenna covers an area of 11.82 × 25.28 mm². The dimensions of the microstrip lines in each MIMO element were optimized to achieve a good impedance matching. The design is resonating at 61 GHz, with a wide practical bandwidth of more than 7 GHz, thereby covering IEEE 802.11ad WiGig (58–65 GHz). The average value of gain ranges from 9.45 to 13.6 dBi over the entire frequency bandwidth whereas, the average value of efficiency ranges from 55.5% to 84.3%. The proposed design attains a compact volume, wide bandwidth, and good gain and efficiency performances, which makes it suitable for WiGig terminals. Full article

(This article belongs to the Section Microwave and Wireless Communications)

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12 pages, 938 KiB

Open AccessArticle

Floating Active Inductor Based Trans-Impedance Amplifier in 0.18 μm CMOS Technology for Optical Applications

by Xiangyu Chen and Yasuhiro Takahashi

Electronics 2019, 8(12), 1547; https://doi.org/10.3390/electronics8121547 - 15 Dec 2019

Cited by 9 | Viewed by 3982

Abstract

In this paper, a transimpedance amplifier (TIA) based on floating active inductors (FAI) is presented. Compared with conventional TIAs, the proposed TIA has the advantages of a wider bandwidth, lower power dissipation, and smaller chip area. The schematics and characteristics of the FAI [...] Read more.

In this paper, a transimpedance amplifier (TIA) based on floating active inductors (FAI) is presented. Compared with conventional TIAs, the proposed TIA has the advantages of a wider bandwidth, lower power dissipation, and smaller chip area. The schematics and characteristics of the FAI circuit are explained. Moreover, the proposed TIA employs the combination of capacitive degeneration, the broadband matching network, and the regulated cascode input stage to enhance the bandwidth and gain. This turns the TIA design into a fifth-order low pass filter with Butterworth response. The TIA is implemented using 0.18

μ

m Rohm CMOS technology and consumes only 10.7 mW with a supply voltage of 1.8 V. When used with a 150 fF photodiode capacitance, it exhibits the following characteristics: gain of 41 dB

Ω

and −3 dB frequency of 10 GHz. This TIA occupies an area of 180

μ

m × 118

μ

m. Full article

(This article belongs to the Section Circuit and Signal Processing)

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19 pages, 7058 KiB

Open AccessArticle

A Smart IoT Device for Detecting and Responding to Earthquakes

by Jangsoo Lee, Irshad Khan, Seonhwa Choi and Young-Woo Kwon

Electronics 2019, 8(12), 1546; https://doi.org/10.3390/electronics8121546 - 15 Dec 2019

Cited by 33 | Viewed by 11837

Abstract

The advancement of hardware and software technologies makes it possible to use smartphones or Internet of things for monitoring environments in realtime. In recent years, much effort has been made to develop a smartphone based earthquake early warning system, where low-cost acceleration sensors [...] Read more.

The advancement of hardware and software technologies makes it possible to use smartphones or Internet of things for monitoring environments in realtime. In recent years, much effort has been made to develop a smartphone based earthquake early warning system, where low-cost acceleration sensors inside a smartphones are used for capturing earthquake signals. However, because a smartphone comes with a powerful CPU, spacious memory, and several sensors, it is waste of such resources to use it only for detecting earthquakes. Furthermore, because a smartphone is mostly in use during the daytime, the acquired data cannot be used for detecting earthquakes due to human activities. Therefore, in this article, we introduce a stand-alone device equipped with a low-cost acceleration sensor and least computing resources to detect earthquakes. To that end, we first select an appropriate acceleration sensor by assessing the performance and accuracy of four different sensors. Then, we design and develop an earthquake alert device. To detect earthquakes, we employ a simple machine learning technique which trains an earthquake detection model with daily motions, noise data recorded in buildings, and earthquakes recorded in the past. Furthermore, we evaluate the four acceleration sensors by recording two realistic earthquakes on a shake-table. In the experiments, the results show that the developed earthquake alert device can successfully detect earthquakes and send a warning message to nearby devices, thereby enabling proactive responses to earthquakes. Full article

(This article belongs to the Special Issue IoT Services, Applications, Platform, and Protocols)

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17 pages, 3675 KiB

Open AccessArticle

A Two Stage Intrusion Detection System for Industrial Control Networks Based on Ethernet/IP

by Wenbin Yu, Yiyin Wang and Lei Song

Electronics 2019, 8(12), 1545; https://doi.org/10.3390/electronics8121545 - 15 Dec 2019

Cited by 13 | Viewed by 3575

Abstract

Standard Ethernet (IEEE 802.3 and the TCP/IP protocol suite) is gradually applied in industrial control system (ICS) with the development of information technology. It breaks the natural isolation of ICS, but contains no security mechanisms. An improved intrusion detection system (IDS), which is [...] Read more.

Standard Ethernet (IEEE 802.3 and the TCP/IP protocol suite) is gradually applied in industrial control system (ICS) with the development of information technology. It breaks the natural isolation of ICS, but contains no security mechanisms. An improved intrusion detection system (IDS), which is strongly correlated to specific industrial scenarios, is necessary for modern ICS. On one hand, this paper outlines three kinds of attack models, including infiltration attacks, creative forging attacks, and false data injection attacks. On the other hand, a two stage IDS is proposed, which contains a traffic prediction model and an anomaly detection model. The traffic prediction model, which is based on the autoregressive integrated moving average (ARIMA), can forecast the traffic of the ICS network in the short term and detect infiltration attacks precisely according to the abnormal changes in traffic patterns. Furthermore, the anomaly detection model, using a one class support vector machine (OCSVM), is able to detect malicious control instructions by analyzing the key field in Ethernet/IP packets. The confusion matrix is selected to testify to the effectiveness of the proposed method, and two other innovative IDSs are used for comparison. The experiment results show that the proposed two stage IDS in this paper has an outstanding performance in detecting infiltration attacks, forging attacks, and false data injection attacks compared with other IDSs. Full article

(This article belongs to the Special Issue Advanced Cybersecurity Services Design)

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12 pages, 1677 KiB

Open AccessArticle

A Novel Video Face Verification Algorithm Based on TPLBP and the 3D Siamese-CNN

by Yu Wang, Shuyang Ma and Xuanjing Shen

Electronics 2019, 8(12), 1544; https://doi.org/10.3390/electronics8121544 - 14 Dec 2019

Cited by 3 | Viewed by 2676

Abstract

In order to reduce the computational consumption of the training and the testing phases of video face recognition methods based on a global statistical method and a deep learning network, a novel video face verification algorithm based on a three-patch local binary pattern [...] Read more.

In order to reduce the computational consumption of the training and the testing phases of video face recognition methods based on a global statistical method and a deep learning network, a novel video face verification algorithm based on a three-patch local binary pattern (TPLBP) and the 3D Siamese convolutional neural network is proposed in this paper. The proposed method takes the TPLBP texture feature which has excellent performance in face analysis as the input of the network. In order to extract the inter-frame information of the video, the texture feature maps of the multi-frames are stacked, and then a shallow Siamese 3D convolutional neural network is used to realize dimension reduction. The similarity of high-level features of the video pair is solved by the shallow Siamese 3D convolutional neural network, and then mapped to the interval of 0 to 1 by linear transformation. The classification result can be obtained with the threshold of 0.5. Through an experiment on the YouTube Face database, the proposed algorithm got higher accuracy with less computational consumption than baseline methods and deep learning methods. Full article

(This article belongs to the Section Computer Science & Engineering)

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9 pages, 2578 KiB

Open AccessArticle

Optimum Receiver-Side Tuning Capacitance for Capacitive Wireless Power Transfer

by Sungryul Huh and Dukju Ahn

Electronics 2019, 8(12), 1543; https://doi.org/10.3390/electronics8121543 - 13 Dec 2019

Cited by 2 | Viewed by 2983

Abstract

This paper reveals the optimum capacitance value of a receiver-side inductor-capacitor (LC) network to achieve the highest efficiency in a capacitive power-transfer system. These findings break the usual convention of a capacitance value having to be chosen such that complete LC resonance happens [...] Read more.

This paper reveals the optimum capacitance value of a receiver-side inductor-capacitor (LC) network to achieve the highest efficiency in a capacitive power-transfer system. These findings break the usual convention of a capacitance value having to be chosen such that complete LC resonance happens at the operating frequency. Rather, our findings in this paper indicate that the capacitance value should be smaller than the value that forms the exact LC resonance. These analytical derivations showed that as the ratio of inductor impedance divided by plate impedance increased, the optimum Rx capacitance decreased. This optimum capacitance maximized the TX-to-RX transfer efficiency of a given set of system conditions, such as matching inductors and coupling plates. Full article

(This article belongs to the Special Issue Wireless Power/Data Transfer, Energy Harvesting System Design)

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15 pages, 4767 KiB

Open AccessArticle

Unified Power Flow Controller Based on Autotransformer Structure

by Hyun-Jun Lee, Dae-Shik Lee and Young-Doo Yoon

Electronics 2019, 8(12), 1542; https://doi.org/10.3390/electronics8121542 - 13 Dec 2019

Cited by 8 | Viewed by 3764

Abstract

This paper proposes a new unified power flow controller (UPFC) topology. A single phase of them system with the proposed topology consists of an N:2 transformer with a center tap at the low-voltage side and a power converter module comprising full- and half-bridge [...] Read more.

This paper proposes a new unified power flow controller (UPFC) topology. A single phase of them system with the proposed topology consists of an N:2 transformer with a center tap at the low-voltage side and a power converter module comprising full- and half-bridge converters. A three-phase system can be implemented with three devices. While the conventional UPFC topology uses two three-phase transformers, which are called series and parallel transformers, the proposed topology utilizes three single-phase transformers to implement a three-phase UPFC system. By using an autotransformer structure, the power rating of the transformers and the voltage rating of switches in the power converter module can be significantly decreased. As a result, it is possible to reduce the installation spaces and costs compared with the conventional UPFC topology. In addition, by adopting a full- and half-bridge converter structure, the proposed topology can be easily implemented with conventional power devices and control techniques. The techniques used to control the proposed topology are described in this paper. The results obtained from simulations and experiments verify the effectiveness of the proposed UPFC topology. Full article

(This article belongs to the Special Issue High Power Electric Traction Systems)

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19 pages, 5013 KiB

Open AccessFeature PaperArticle

A Wireless Sensors Network for Monitoring the Carasau Bread Manufacturing Process

by Matteo Baire, Andrea Melis, Matteo B. Lodi, Pierluigi Tuveri, Chiara Dachena, Marco Simone, Alessandro Fanti, Giorgio Fumera, Tonino Pisanu and Giuseppe Mazzarella

Electronics 2019, 8(12), 1541; https://doi.org/10.3390/electronics8121541 - 13 Dec 2019

Cited by 34 | Viewed by 5191

Abstract

This work copes with the design and implementation of a wireless sensors network architecture to automatically and continuously monitor, for the first time, the manufacturing process of Sardinian Carasau bread. The case of a traditional bakery company facing the challenge of the Food-Industry [...] Read more.

This work copes with the design and implementation of a wireless sensors network architecture to automatically and continuously monitor, for the first time, the manufacturing process of Sardinian Carasau bread. The case of a traditional bakery company facing the challenge of the Food-Industry 4.0 competitiveness is investigated. The process was analyzed to identify the most relevant variables to be monitored during the product manufacturing. Then, a heterogeneous, multi-tier wireless sensors network was designed and realized to allow the real-time control and the data collection during the critical steps of dough production, sheeting, cutting and leavening. Commercial on-the-shelf and cost-effective integrated electronics were employed, making the proposed approach of interest for many practical cases. Finally, a user-friendly interface was provided to enhance the understanding, control and to favor the process monitoring. With the wireless senors network (WSN) we designed, it is possible to monitor environmental parameters (temperature, relative humidity, gas concentrations); cinematic quantities of the belts; and, through a dedicated image processing system, the morphological characteristics of the bread before the baking. The functioning of the WSN was demonstrated and a statistical analysis was performed on the variables monitored during different seasons. Full article

(This article belongs to the Special Issue Application of Wireless Sensor Networks in Monitoring)

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10 pages, 2190 KiB

Open AccessArticle

A Miniaturized Wideband Bandpass Filter Using Quarter-Wavelength Stepped-Impedance Resonators

by Liqin Liu, Ping Zhang, Min-Hang Weng, Chin-Yi Tsai and Ru-Yuan Yang

Electronics 2019, 8(12), 1540; https://doi.org/10.3390/electronics8121540 - 13 Dec 2019

Cited by 14 | Viewed by 2983

Abstract

In this paper, we present a simple method to design a miniaturized wideband bandpass filter with suppression of the third harmonic, using only two quarter-wavelength stepped-impedance resonators (SIRs). The resonant modes of the quarter-wavelength SIR, depending on the impedance ratio (K) and electrical [...] Read more.

In this paper, we present a simple method to design a miniaturized wideband bandpass filter with suppression of the third harmonic, using only two quarter-wavelength stepped-impedance resonators (SIRs). The resonant modes of the quarter-wavelength SIR, depending on the impedance ratio (K) and electrical length ratio (α), are discussed first. As to setting the resonant frequency of the SIR for the lower band edge of the required band, the size parameters of two quarter-wavelength SIRs can be determined by selecting the desired impedance ratio (K) and length ratio (α). By using the opposite directional arrangement of two SIRs with direct taped input/output ports, the wideband response can be formed. A filter example is shown in this study to address this simple design procedure. The measured results of the fabricated filter have a wide passband response from 3.3 to 5.8 GHz, with an insertion loss of 1.5 dB, a return loss of 20 dB, an extended bandwidth ration of 55%, a low-average group delay of less than 0.75 ns, and a stopband from 6 to 12 GHz, with an attenuation level of 20 dB. Due to the similar 0° feeding, a transmission zero at 8.3 GHz appears near the band edge; thus, improving the band selectivity. The proposed filter can have a very simple structure and a miniature size. Simulated results and measured results are in good agreement. Full article

(This article belongs to the Special Issue Filter Design Solutions for RF systems)

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18 pages, 403 KiB

Open AccessArticle

Using Approximate Computing and Selective Hardening for the Reduction of Overheads in the Design of Radiation-Induced Fault-Tolerant Systems

by Alexander Aponte-Moreno, Felipe Restrepo-Calle and Cesar Pedraza

Electronics 2019, 8(12), 1539; https://doi.org/10.3390/electronics8121539 - 13 Dec 2019

Cited by 3 | Viewed by 2729

Abstract

Fault mitigation techniques based on pure software, known as software-implemented hardware fault tolerance (SIHFT), are very attractive for use in COTS (commercial off-the-shelf) microprocessors because they do not require physical modification of the system. However, these techniques cause software overheads that may affect [...] Read more.

Fault mitigation techniques based on pure software, known as software-implemented hardware fault tolerance (SIHFT), are very attractive for use in COTS (commercial off-the-shelf) microprocessors because they do not require physical modification of the system. However, these techniques cause software overheads that may affect the efficiency and costs of the overall system. This paper presents a design method of radiation-induced fault-tolerant microprocessor-based systems with lower execution time overheads. For this purpose, approximate computing and selective fault mitigation software-based techniques are used; thus it can be used in COTS devices. The proposal is validated through a case study for the TI MSP430 microcontroller. Results show that the designer can choose among a wide spectrum of design configurations, exploring different trade-offs between reliability, performance, and accuracy of results. Full article

(This article belongs to the Special Issue Approximate Computing: Design, Acceleration, Validation and Testing of Circuits, Architectures and Algorithms in Future Systems)

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15 pages, 14027 KiB

Open AccessFeature PaperArticle

A Feature Integrated Saliency Estimation Model for Omnidirectional Immersive Images

by Pramit Mazumdar, Kamal Lamichhane, Marco Carli and Federica Battisti

Electronics 2019, 8(12), 1538; https://doi.org/10.3390/electronics8121538 - 13 Dec 2019

Cited by 6 | Viewed by 2619

Abstract

Omnidirectional, or 360°, cameras are able to capture the surrounding space, thus providing an immersive experience when the acquired data is viewed using head mounted displays. Such an immersive experience inherently generates an illusion of being in a virtual environment. The popularity of [...] Read more.

Omnidirectional, or 360°, cameras are able to capture the surrounding space, thus providing an immersive experience when the acquired data is viewed using head mounted displays. Such an immersive experience inherently generates an illusion of being in a virtual environment. The popularity of 360° media has been growing in recent years. However, due to the large amount of data, processing and transmission pose several challenges. To this aim, efforts are being devoted to the identification of regions that can be used for compressing 360° images while guaranteeing the immersive feeling. In this contribution, we present a saliency estimation model that considers the spherical properties of the images. The proposed approach first divides the 360° image into multiple patches that replicate the positions (viewports) looked at by a subject while viewing a 360° image using a head mounted display. Next, a set of low-level features able to depict various properties of an image scene is extracted from each patch. The extracted features are combined to estimate the 360° saliency map. Finally, bias induced during image exploration and illumination variation is fine-tuned for estimating the final saliency map. The proposed method is evaluated using a benchmark 360° image dataset and is compared with two baselines and eight state-of-the-art approaches for saliency estimation. The obtained results show that the proposed model outperforms existing saliency estimation models. Full article

(This article belongs to the Special Issue Digital Media Processing for Immersive Communications)

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9 pages, 2194 KiB

Open AccessArticle

Performance of Dual-Band Short-Wave Infrared InGaAs Focal-Plane Arrays with Interference Narrow-Band Filter

by Honghai Deng, Zhiliang Wang, Haibao Shao, Yi Li, Xue Li and Haimei Gong

Electronics 2019, 8(12), 1537; https://doi.org/10.3390/electronics8121537 - 13 Dec 2019

Cited by 3 | Viewed by 2593

Abstract

In this work, we fabricated dual-band 800 × 2 short-wave infrared (SWIR) indium gallium arsenide (InGaAs) focal-plane arrays (FPAs) using N-InP/i-In_0.53Ga_0.47As/N-InP double-heterostructure materials, which are often applied in ocean-color remote sensing. Using narrow-band interference-filter integration, our detector-adopted planner structure [...] Read more.

In this work, we fabricated dual-band 800 × 2 short-wave infrared (SWIR) indium gallium arsenide (InGaAs) focal-plane arrays (FPAs) using N-InP/i-In_0.53Ga_0.47As/N-InP double-heterostructure materials, which are often applied in ocean-color remote sensing. Using narrow-band interference-filter integration, our detector-adopted planner structure produced two detection channels with center wavelengths of 1.24 and 1.64 μm, and a full-width half-maximum (FWHM) of 0.02 μm for both channels. The photoelectric characteristics of the spectral response, modulation transfer function (MTF), and detectability of the detector were further analyzed. Our FPAs showed good MTF uniformity with pixel operability as high as 100% for each 800 × 1 linear array. Peak detectivity reached 4.39 × 1012 and 5.82 × 1012 cm·Hz1/2/W at 278 K, respectively, and response nonuniformity was ideal at 2.48% and 2.61%, respectively. As a final step, dual-band infrared detection imaging was successfully carried out in push-broom mode. Full article

(This article belongs to the Special Issue Optical Imaging Instrumentation)

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13 pages, 4465 KiB

Open AccessArticle

Autonomous Driving in Roundabout Maneuvers Using Reinforcement Learning with Q-Learning

by Laura García Cuenca, Enrique Puertas, Javier Fernandez Andrés and Nourdine Aliane

Electronics 2019, 8(12), 1536; https://doi.org/10.3390/electronics8121536 - 13 Dec 2019

Cited by 43 | Viewed by 7374

Abstract

Navigating roundabouts is a complex driving scenario for both manual and autonomous vehicles. This paper proposes an approach based on the use of the Q-learning algorithm to train an autonomous vehicle agent to learn how to appropriately navigate roundabouts. The proposed learning algorithm [...] Read more.

Navigating roundabouts is a complex driving scenario for both manual and autonomous vehicles. This paper proposes an approach based on the use of the Q-learning algorithm to train an autonomous vehicle agent to learn how to appropriately navigate roundabouts. The proposed learning algorithm is implemented using the CARLA simulation environment. Several simulations are performed to train the algorithm in two scenarios: navigating a roundabout with and without surrounding traffic. The results illustrate that the Q-learning-algorithm-based vehicle agent is able to learn smooth and efficient driving to perform maneuvers within roundabouts. Full article

(This article belongs to the Special Issue Autonomous Vehicles Technology)

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19 pages, 7323 KiB

Open AccessArticle

Predictive Control Method Based on Adjacent Vector Confinement Technique for a Three-Phase AC-DC Matrix Converter with High Efficiency

by Eun-Su Jun, Hoang-Long Dang and Sangshin Kwak

Electronics 2019, 8(12), 1535; https://doi.org/10.3390/electronics8121535 - 12 Dec 2019

Cited by 1 | Viewed by 2437

Abstract

A model predictive current control method is proposed to reduce switching losses in an AC-DC matrix converter. In the proposed control strategy, several vectors are selected from among all possible switching vectors for a given location of the input current reference. The switching [...] Read more.

A model predictive current control method is proposed to reduce switching losses in an AC-DC matrix converter. In the proposed control strategy, several vectors are selected from among all possible switching vectors for a given location of the input current reference. The switching vector that minimizes the cost function is applied to the converter in the next sampling period. The principle of the proposed method involves clamping the selected switches to stop performing the switching operation to minimize the number of switchings in every sampling cycle. The total efficiency of the AC-DC matrix converter under the proposed strategy is 91.2% whereas that of the conventional strategy is 89.7%. In addition, unity-power-factor operation is guaranteed and smooth and sinusoidal waveforms are achieved. Finally, simulation and experimental results are demonstrated to confirm the validity of the proposed control strategy. Full article

(This article belongs to the Special Issue High Power Electric Traction Systems)

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18 pages, 3999 KiB

Open AccessArticle

Unified Predictive Current Control of PMSMs with Parameter Uncertainty

by Peng Tang, Yuehong Dai and Zhaoyang Li

Electronics 2019, 8(12), 1534; https://doi.org/10.3390/electronics8121534 - 12 Dec 2019

Cited by 7 | Viewed by 2242

Abstract

Predictive current control (PCC) applied on permanent magnet synchronous motors (PMSMs) has been developed into mainly three methods: the conventional finite-control-set PCC, the double voltage vectors PCC, and deadbeat PCC. However, each approach has its particular calculation way for voltage vectors selection and [...] Read more.

Predictive current control (PCC) applied on permanent magnet synchronous motors (PMSMs) has been developed into mainly three methods: the conventional finite-control-set PCC, the double voltage vectors PCC, and deadbeat PCC. However, each approach has its particular calculation way for voltage vectors selection and respective execution duration. This paper, based on the deadbeat idea, presents a unified predictive current control scheme of PMSMs. Under this scheme, the prior three classes are able to be clearly unified into one frame with lower calculation effort. Furthermore, to cope with problem of parameter mismatch in dq-axis current predictive model, a integrated identification method is proposed. Firstly, data selectors are designed to reject abnormal data of sampling signals, and then the interval-varying multi-innovation least squares algorithm is combined with forgetting factor (V-FF-MILS) to approximate the error terms caused by electromagnetic parameters error. The estimated results are online fed to the model of PMSM to enhance its accuracy. Finally, the processor in loop (PIL) simulation results verify that the proposed integrated scheme has advantages in current control of PMSMs with large-scale parameter uncertainty. Full article

(This article belongs to the Special Issue Advanced Control Systems for Electric Drives)

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11 pages, 2648 KiB

Open AccessArticle

Efficient FPGA-Based Architecture of the Overlap-Add Method for Short-Time Fourier Analysis/Synthesis

by Mohammed Bahoura

Electronics 2019, 8(12), 1533; https://doi.org/10.3390/electronics8121533 - 12 Dec 2019

Cited by 10 | Viewed by 4485

Abstract

This paper proposes a simple and efficient FPGA-based architecture of the overlapping/windowing and overlap-add methods for real-time FFT/IFFT-based signal processing algorithms. The analyzed signal is divided into short-time overlapping frames that are windowed before applying Fourier analysis/synthesis. Then, the original signal is reconstructed [...] Read more.

This paper proposes a simple and efficient FPGA-based architecture of the overlapping/windowing and overlap-add methods for real-time FFT/IFFT-based signal processing algorithms. The analyzed signal is divided into short-time overlapping frames that are windowed before applying Fourier analysis/synthesis. Then, the original signal is reconstructed from the windowed (modified) frames using the overlap-add (OLA) technique. The proposed architecture was implemented on Field Programmable Gate Array (FPGA) using a high-level programming tool in MATLAB/SIMULINK environment. Its performance was evaluated on artificial and actual signals using objective metrics. Full article

(This article belongs to the Section Circuit and Signal Processing)

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16 pages, 5316 KiB

Open AccessFeature PaperArticle

Accurate Landing of Unmanned Aerial Vehicles Using Ground Pattern Recognition

by Jamie Wubben, Francisco Fabra, Carlos T. Calafate, Tomasz Krzeszowski, Johann M. Marquez-Barja, Juan-Carlos Cano and Pietro Manzoni

Electronics 2019, 8(12), 1532; https://doi.org/10.3390/electronics8121532 - 12 Dec 2019

Cited by 55 | Viewed by 7026

Abstract

Over the last few years, several researchers have been developing protocols and applications in order to autonomously land unmanned aerial vehicles (UAVs). However, most of the proposed protocols rely on expensive equipment or do not satisfy the high precision needs of some UAV [...] Read more.

Over the last few years, several researchers have been developing protocols and applications in order to autonomously land unmanned aerial vehicles (UAVs). However, most of the proposed protocols rely on expensive equipment or do not satisfy the high precision needs of some UAV applications such as package retrieval and delivery or the compact landing of UAV swarms. Therefore, in this work, a solution for high precision landing based on the use of ArUco markers is presented. In the proposed solution, a UAV equipped with a low-cost camera is able to detect ArUco markers sized

56 \times 56

cm from an altitude of up to 30 m. Once the marker is detected, the UAV changes its flight behavior in order to land on the exact position where the marker is located. The proposal was evaluated and validated using both the ArduSim simulation platform and real UAV flights. The results show an average offset of only 11 cm from the target position, which vastly improves the landing accuracy compared to the traditional GPS-based landing, which typically deviates from the intended target by 1 to 3 m. Full article

(This article belongs to the Special Issue Unmanned Aerial Vehicles: Platforms, Applications, Security and Services)

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12 pages, 3994 KiB

Open AccessArticle

SEE Sensitivity Evaluation for Commercial 16 nm SRAM-FPGA

by Chang Cai, Shuai Gao, Peixiong Zhao, Jian Yu, Kai Zhao, Liewei Xu, Dongqing Li, Ze He, Guangwen Yang, Tianqi Liu and Jie Liu

Electronics 2019, 8(12), 1531; https://doi.org/10.3390/electronics8121531 - 12 Dec 2019

Cited by 10 | Viewed by 3306

Abstract

Radiation effects can induce severe and diverse soft errors in digital circuits and systems. A Xilinx commercial 16 nm FinFET static random-access memory (SRAM)-based field-programmable gate array (FPGA) was selected to evaluate the radiation sensitivity and promote the space application of FinFET ultra [...] Read more.

Radiation effects can induce severe and diverse soft errors in digital circuits and systems. A Xilinx commercial 16 nm FinFET static random-access memory (SRAM)-based field-programmable gate array (FPGA) was selected to evaluate the radiation sensitivity and promote the space application of FinFET ultra large-scale integrated circuits (ULSI). Picosecond pulsed laser and high energy heavy ions were employed for irradiation. Before the tests, SRAM-based configure RAMs (CRAMs) were initialized and configured. The 100% embedded block RAMs (BRAMs) were utilized based on the Vivado implementation of the compiled hardware description language. No hard error was observed in both the laser and heavy-ion test. The thresholds for laser-induced single event upset (SEU) were ~3.5 nJ, and the SEU cross-sections were correlated positively to the laser’s energy. Multi-bit upsets were measured in heavy-ion and high-energy laser irradiation. Moreover, latch-up and functional interrupt phenomena were common, especially in the heavy-ion tests. The single event effect results for the 16 nm FinFET process were significant, and some radiation tolerance strategies were required in a radiation environment. Full article

(This article belongs to the Special Issue Extreme-Environment Electronics: Challenges and Solutions)

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11 pages, 714 KiB

Open AccessArticle

Improved RMS Delay Spread Estimation for mmWave Channels Using Savitzky–Golay Filters

by Jiří Miloš, Jiří Blumenstein, Aleš Prokeš, Tomáš Mikulášek and Christoph Mecklenbräuker

Electronics 2019, 8(12), 1530; https://doi.org/10.3390/electronics8121530 - 12 Dec 2019

Cited by 1 | Viewed by 2568

Abstract

In this paper, a novel method for improving the estimation accuracy of the root mean square (RMS) delay spread from the magnitude of the Channel Transfer Function (CTF) is presented. We utilize the level crossing rate metric in the frequency domain, which is [...] Read more.

In this paper, a novel method for improving the estimation accuracy of the root mean square (RMS) delay spread from the magnitude of the Channel Transfer Function (CTF) is presented. We utilize the level crossing rate metric in the frequency domain, which is based on scalar power measurement. The Savitzky–Golay (S-G) filtering method is used to improve the fidelity of the channel delay spread estimator. The presented concept is simple to implement and inexpensive. The proposed method is tested on the CTF magnitude data measured in the mmWave frequency band at low Signal-to-Noise Ratio (SNR). Full article

(This article belongs to the Section Microwave and Wireless Communications)

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