# Chiplet Multi-Objective Optimization Algorithm Based on Communication Consumption and Temperature

^{1}

^{2}

^{3}

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## Abstract

**:**

## 1. Introduction

## 2. Related Works

## 3. Chiplet Multi-Objective Optimization Method

#### 3.1. Thermal Module Establishment

#### 3.2. Chiplet Multi-Objective Optimization Algorithm Description

#### 3.2.1. Topology Generation

#### 3.2.2. The Number and Location of the Initial Nodes

Algorithm 1 Initial node generation |

Input: topology length N1, width N2. chiplet length L0, width W0. |

Output: number of schemes, M. Initial node matrix, initial_node []. |

1.int x = ceil ((N1 − L0 + 1)/2); |

2.int y = ceil ((N2 − W0 + 1)/2); |

3.int M = x × y; |

4.int k = 0; |

5.for (int i = 0; i < x; i++) |

6.{ |

7. for (int j = 0; j < y; j++) |

8. { |

9. initial_node[k] = i + j × N1; |

10. k++; |

11. } |

12.} |

#### 3.2.3. Selecting Mapping Area

Algorithm 2 Next chiplet selection |

Input: topology length N1, width N2 chiplet length L, width W. mapping flag matrix, mflag []. counting matrix, count []. |

Output: selection flag matrix, sflag []. |

1.for (int k = 0; k < L × W; k++) |

2. { |

3. for (int w = 0; w < W; w++) |

4. { |

5. for (int l = 0; l < L; l++) |

6. { |

7. if (mflag [k + l + w × N1]) == −1 && |

8. L1 <= (N1 − k % N1) && W <= N2 − floor (k/N1)) |

9. count[k]++; |

10. } |

11. } |

12. } |

13.for (int k = 0; k < L × W; k++) |

14. { |

15. if (count[k] == L1 × W1) |

16. { |

17. sflag[k1] = 1; |

18. } |

19. } |

#### 3.2.4. Computing Heuristic Information and Mapping Chiplets

_{i,j}is the Manhattan distance between chiplet_i and chiplet_j. C

_{i,j}is the communication consumption between chiplet_i and chiplet_j, and E

_{bit}is the energy consumed to transmit 1 Mb data per unit distance between chiplets [30]. P

_{j}is the power of chiplet_j.

Algorithm 3 Heuristic information caculation |

Input: chiplet number NR; mapping flag matrix mapflag[]; distance matrix D[][]; mapping matrix map[]; the number of node being mapped k; weighing factor α;maximum and minimum heuristic factors, ${\eta}_{i\mathrm{min}}^{1}$, ${\eta}_{i\mathrm{max}}^{1}$, ${\eta}_{i\mathrm{min}}^{2}$, ${\eta}_{i\mathrm{max}}^{2}$; output: optimal node node; |

1.for(int i = 0; i < NR; i++) |

2.{ |

3. for(int j = i + 1; j < NR; j++) |

4. { |

5. if(mapflag[i]== −2&&mapflag[j]== −2) |

6. comcost+=D[i][j] × cost[i][j] × 0.186; |

7. } |

8.} |

9. for( int i = 0; i < NR; i++) |

10.{ |

11. if( i ! = k&&map[i]== −2) |

12. { |

13. temcost+=power[mapp[i]]/D[map[i]]D[map[k]]; |

14. } |

15.} |

16. cost = α* (comcost − ${\eta}_{i\mathrm{min}}^{1}$${\eta}_{i\mathrm{min}}^{1}$)/(${\eta}_{i\mathrm{max}}^{1}$ − ${\eta}_{i\mathrm{min}}^{1}$) + (1 − α) × (temcost − ${\eta}_{i\mathrm{min}}^{2}$)/ |

17. (${\eta}_{i\mathrm{max}}^{2}$ − ${\eta}_{i\mathrm{min}}^{2}$); |

18.if(cost < cost_min) |

19.{ |

20. cost_min = cost; |

21. node = i; |

22.} |

_{1}(Figure 6a) and node n

_{2}(Figure 6b), the heuristic information ${\eta}_{0}$ and ${\eta}_{0}^{\prime}$ are equal. Suppose chip_4 employs the mapping scheme depicted in Figure 6a and in this case chiplet_1 (the next chiplet to be mapped) is mapped in the remaining nodes. In Figure 6c, calculate the minimum of the heuristic information in the remaining nodes when mapping chiplet_1, and record the heuristic information ${\eta}_{01}$ and the node n

_{3}. Similarly, in Figure 6d, calculate the minimum of the heuristic information in the remaining nodes, and record the heuristic information ${\eta}_{01}^{\prime}$ and node n

_{4}. If ${\eta}_{01}$ is greater than ${\eta}_{01}^{\prime}$, node n

_{3}will be selected to map chiplet_4; on the contrary, n

_{2}will be selected.

## 4. Evaluation Results

## 5. Conclusions

## Author Contributions

## Funding

## Data Availability Statement

## Conflicts of Interest

## References

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**Figure 4.**(

**a**) An example of initial chiplet placement; (

**b**) symmetrical placement with the same mapping effect.

**Figure 6.**(

**a**,

**b**) An example of nodes having the same heuristic information. (

**c**,

**d**) Secondary exploration method to map the next chiplet.

**Figure 9.**(

**a**) Initial layout of MWD; (

**b**) multi-objective optimization result with α equal to 0.5; (

**c**) multi-objective optimization result with α equal to 0.8; (

**d**) multi-objective optimization result with α equal to 0.2; and (

**e**) communication consumption single-objective optimization result.

Priority | Chiplet Number | Chiplet Name | Communication Data (Mbit/s) |
---|---|---|---|

1 | 8 | mem3 | 256 |

2 | 4 | hs | 224 |

1 | nr | 224 | |

3 | 0 | in | 192 |

3 | vs | 192 | |

5 | mem2 | 192 | |

6 | hvs | 192 | |

7 | jug1 | 192 | |

9 | jug2 | 192 | |

4 | 10 | se | 128 |

2 | mem1 | 64 | |

5 | 11 | blend | 64 |

Chiplet Name | Chiplet Theoretical Size (mm^{2}) | Chiplet Actual Size (mm^{2}) | Power (W) |
---|---|---|---|

mem3 | 6.0 × 2.0 | 4.5 × 1.5 | 10 |

hs | 6.0 × 6.0 | 4.5 × 4.5 | 40 |

nr | 8.0 × 6.0 | 7.5 × 4.5 | 70 |

in | 6.0 × 6.0 | 4.5 × 4.5 | 30 |

vs | 6.0 × 6.0 | 4.5 × 4.5 | 20 |

mem2 | 6.0 × 2.0 | 4.5 × 1.5 | 10 |

hvs | 6.0 × 6.0 | 4.5 × 4.5 | 30 |

jug1 | 6.0 × 6.0 | 4.5 × 4.5 | 50 |

jug2 | 6.0 × 6.0 | 4.5 × 4.5 | 50 |

se | 6.0 × 6.0 | 4.5 × 4.5 | 20 |

mem1 | 6.0 × 2.0 | 4.5 × 1.5 | 10 |

blend | 4.0 × 4.0 | 2.5 × 2.5 | 5 |

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**MDPI and ACS Style**

Sun, H.; Peng, X.; Cang, D.; Zhao, J.; Liu, Y.; Fang, J. Chiplet Multi-Objective Optimization Algorithm Based on Communication Consumption and Temperature. *Electronics* **2023**, *12*, 1604.
https://doi.org/10.3390/electronics12071604

**AMA Style**

Sun H, Peng X, Cang D, Zhao J, Liu Y, Fang J. Chiplet Multi-Objective Optimization Algorithm Based on Communication Consumption and Temperature. *Electronics*. 2023; 12(7):1604.
https://doi.org/10.3390/electronics12071604

**Chicago/Turabian Style**

Sun, Haiyan, Xinwei Peng, Dongqing Cang, Jicong Zhao, Yanhua Liu, and Jiaen Fang. 2023. "Chiplet Multi-Objective Optimization Algorithm Based on Communication Consumption and Temperature" *Electronics* 12, no. 7: 1604.
https://doi.org/10.3390/electronics12071604