# Demystifying Non-Isolated DC–DC Topologies on Partial Power Processing Architectures

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## Abstract

**:**

## 1. Introduction

## 2. PPC Architecture Description

## 3. Single Inductor Topology Case Study

## 4. Double Inductor Topology Case Study

## 5. Experimental Results

#### 5.1. Prototype Design

- Power block 1 uses ${Q}_{L,H}$, ${Q}_{R,H},$ and ${Q}_{R,L}$ to act as ${Q}_{3}$,$\text{}{Q}_{4}$, and ${Q}_{2}$, respectively (Figure 5).

- Power block 2 uses ${Q}_{R,H}\text{}$ and ${Q}_{R,L}$ to act as ${Q}_{5}$ and ${Q}_{1}$, respectively (Figure 5).

#### 5.2. Description of the Experimental Set-up

- ${V}_{in}$ and ${V}_{out}$, which also represent ${V}_{source}$ and ${V}_{load}$.
- ${I}_{in}$ and ${I}_{out}$, which also represent ${I}_{source}$ and ${I}_{load}$.

- ${V}_{source}$, ${V}_{out}$, and ${V}_{in}$, where the latter coincides with ${V}_{load}$.
- ${I}_{load}$, ${I}_{in}$, and ${I}_{source}$, where the latter coincides with ${I}_{out}$.

#### 5.3. Results

#### 5.3.1. Single Inductor Topology

#### 5.3.2. Double Inductor Topology

## 6. Discussion

## 7. Conclusions

## Author Contributions

## Funding

## Conflicts of Interest

## Appendix A

Description | Reference |
---|---|

Source | ITECH IT6012C-800-40 |

Load | EA-ELR 9750-22 |

Power meter | YOKOGAWA WT500 |

Temperature measurement | Pico TC-08 |

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**Figure 4.**Current and voltage steady-state waveforms at the single-inductor topology (

**a**) inductor, (

**b**) semiconductor, and (

**c**) capacitor.

**Figure 5.**MSIBC topology implemented on a (

**a**) FPC architecture, (

**b**) an FC-type PPC architecture, and (

**c**) a switching sequence between an FPC-MSIBC and a PPC-MSIBC.

**Figure 8.**Mounted inductance for the (

**a**) HB ($L=150\mathsf{\mu}\mathrm{H}$ and ${R}_{L}=26\text{}\mathrm{m}\mathsf{\Omega}$) and (

**b**) MSIBC ($L=75\mathsf{\mu}\mathrm{H}$ and ${R}_{L}=31\text{}\mathrm{m}\mathsf{\Omega}$).

**Figure 9.**Assembled full-bridge prototype. (

**a**) High level schematic. (

**b**) Power layer. (

**c**) Driver layer.

Parameter | Value |
---|---|

${V}_{source}\left(\mathrm{V}\right)$ | 100 |

${V}_{load}\left(\mathrm{V}\right)$ | 125 |

${f}_{sw}$ (kHz) | 50 |

P (kW) | 1.5 |

Parameter | FPC-HB | PPC-HB |
---|---|---|

${V}_{in}\left(\mathrm{V}\right)$ | 100 | 125 |

${V}_{out}\left(\mathrm{V}\right)$ | 125 | 25 |

${K}_{pr}$ | 1 | 0.25 |

${P}_{conv}$ (kW) | 1.5 | 0.375 |

Operation mode | Boost | Buck |

$L$ (µH) | 150 | |

$C$ (µF) | 200 | |

${Q}_{1-2}$ (mΩ) | ${R}_{ds}=29$ |

Parameter | FPC-HB | PPC-HB |
---|---|---|

${P}_{conduction}$ (W) | $6.5$ | $6.5$ |

${P}_{switching}$ (W) | $50$ | $50$ |

${\eta}_{sys}$ (%) | $96.23$ | $96.23$ |

${\eta}_{conv}$ (%) | $96.23$ | $84.8$ |

${K}_{pr}$ (p.u.) | $1$ | $0.248$ |

Parameter | Value |
---|---|

${V}_{source}\left(\mathrm{V}\right)$ | $100$ |

${V}_{load}\left(\mathrm{V}\right)$ | $125$ |

${f}_{sw}$ (kHz) | $50$ |

P (kW) | $0.75$ |

Parameter | FPC-MSIBC | PPC-MSIBC |
---|---|---|

${V}_{in}$(V) | $100$ | $125$ |

${V}_{out}$ (V) | $125$ | $25$ |

${K}_{pr}$ (p.u.) | $1$ | $0.25$ |

${P}_{conv}$ (kW) | $0.75$ | $0.187$ |

Operation mode | Boost | Buck |

${L}_{1}$ & ${L}_{2}$ (µH) | $75$ | |

$C$ (µF) | $200$ | |

${Q}_{1-5}$ (mΩ) | ${R}_{ds}=29$ |

Parameter | FPC-MSIBC | PPC-MSIBC |
---|---|---|

${P}_{conduction}$ (W) | $3.3$ | $0.66$ |

${P}_{switching}$ (W) | $35$ | $21$ |

${\eta}_{sys}$ (%) | $94.89$ | $97.1$ |

${\eta}_{conv}$ (%) | $94.89$ | $88.31$ |

${K}_{pr}$ (p.u.) | $1$ | $0.248$ |

**Table 7.**Selected capacitor, semiconductor, and heatsink for the single and the double inductor topologies.

Component | Reference | Value |
---|---|---|

$C$ | MKP1848C | $C=200\mu \mathrm{F}$ (2 in parallel) |

$Q$ | IPT65R033G7 | ${R}_{ds}=29\mathrm{m}\mathsf{\Omega}$ |

Heatsink | LA 9/150 24V | ${R}_{th}=0.18\mathrm{K}/\mathrm{W}$ |

**Table 8.**Experimental power loss, efficiency, and ${K}_{pr}$ results obtained with the single-inductor topology.

Parameter | FPC-HB | PPC-HB |
---|---|---|

${P}_{conduction}$ (W) | $11.36$ | $11.49$ |

${P}_{switching}$ (W) | $49.63$ | $46.5$ |

${\eta}_{sys}$ (%) | $95.93$ | $96.13$ |

${\eta}_{conv}$ (%) | $95.93$ | $84.27$ |

${K}_{pr}$ (p.u.) | $1$ | $0.246$ |

**Table 9.**Experimental power loss, efficiency, and ${K}_{pr}$ results obtained with the double-inductor topology.

Parameter | FPC-MSIBC | PPC-MSIBC |
---|---|---|

${P}_{conduction}$ (W) | $5.63$ | $3.38$ |

${P}_{switching}$ (W) | $34.36$ | $20.61$ |

${\eta}_{sys}$ (%) | $94.67$ | $96.8$ |

${\eta}_{conv}$ (%) | $94.67$ | $86.9$ |

${K}_{pr}$ (p.u.) | $1$ | $0.245$ |

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**MDPI and ACS Style**

Anzola, J.; Aizpuru, I.; Arruti, A.; Artal-Sevil, J.S.; Bernal, C.
Demystifying Non-Isolated DC–DC Topologies on Partial Power Processing Architectures. *Electronics* **2022**, *11*, 480.
https://doi.org/10.3390/electronics11030480

**AMA Style**

Anzola J, Aizpuru I, Arruti A, Artal-Sevil JS, Bernal C.
Demystifying Non-Isolated DC–DC Topologies on Partial Power Processing Architectures. *Electronics*. 2022; 11(3):480.
https://doi.org/10.3390/electronics11030480

**Chicago/Turabian Style**

Anzola, Jon, Iosu Aizpuru, Asier Arruti, Jesus Sergio Artal-Sevil, and Carlos Bernal.
2022. "Demystifying Non-Isolated DC–DC Topologies on Partial Power Processing Architectures" *Electronics* 11, no. 3: 480.
https://doi.org/10.3390/electronics11030480