Research on Bidirectional Isolated Charging System Based on Resonant Converter

Abstract

This paper proposes a two-stage bidirectional isolated charging system, which can realize the bidirectional flow of electric energy, not only making the electric energy flow from the grid side to the battery side but also converting the battery’s energy into single-phase alternating current to supply other electric equipment. The charging system also has the function of power factor correction and wide-range voltage output. The front stage of the charging system is a bidirectional totem pole structure power factor correction converter with a voltage and current double closed-loop control strategy to ensure the stability of the DC bus voltage, and the rear stage is a bidirectional CLLLC resonant converter, which adopts a high-frequency soft start strategy to reduce the inrush current during start-up and ensure the safe operation of the converter. Moreover, the frequency control strategy is used to make it have a wide range of DC output characteristics. In this paper, the principle analysis and parameter calculation of the charging system is carried out, the simulation platform and hardware circuit design are built, and a test prototype is piloted to verify the bidirectional operating characteristics of the charging system. The simulation and experimental results demonstrate the correctness of the theoretical analysis and topology design.

1. Introduction

With the development of the economy and the increase of social demand, new energy electric vehicles are one of the important means to alleviate the shortage of oil energy, environmental pollution, and the development trend to replace fuel cars [1,2]. While electric vehicles are attracting attention, on-board charging technology is also developing rapidly and is generally divided into unidirectional vehicle chargers and bidirectional vehicle chargers. Compared with the single function of unidirectional vehicle charger, which can only transfer energy from the grid to the vehicle battery, the bidirectional vehicle charger also allows the vehicle battery to provide energy to the outside, and it is the core equipment in V2X technology. The bidirectional vehicle charger can also be used as an emergency power source for the family during power outages, and the research into this device is beneficial to the development of a variety of disciplines.

A bidirectional charging system is a device that uses conduction to convert AC power to DC power to charge a battery. Its commonly used two-stage power architecture is shown in Figure 1. The bidirectional charger is capable of the bidirectional flow of energy between the grid and the battery, with a bidirectional AC/DC converter in the front stage, which can achieve power factor correction, reduce harmonic content, and output a stable bus voltage; and a bidirectional isolated DC/DC converter in the backstage, which can output a wide range of DC voltages with low pulsation ripple [3,4].

Bidirectional AC/DC converters are often used as system pre-stages with either a half-bridge structure or a full-bridge structure. The half-bridge structure requires fewer devices and is easy to control, but the switching transistor voltage and current stress are high, and the efficiency is low. An improved single-cycle controlled bidirectional half-bridge AC/DC converter is proposed in [5], capable of stable operation in rectifier and inverter modes with a high power factor, but it has high reactive power losses and low efficiency. The full-bridge AC/DC converter is more widely used than the half-bridge structure. In [6], a full-bridge AC/DC converter considering inductor resistance and conduction voltage is proposed with a single-loop bidirectional current sensor-free control strategy, which reduces the number of sensors and can regulate the voltage of the household DC grid. An interleaved parallel structure has also been derived from the bridge structure. [7] proposes a bidirectional interleaved parallel AC/DC converter with no auxiliary circuit and a TCM mode soft-switching strategy. This topology can effectively reduce losses and improve the overall system efficiency, but it adds difficulty to the control system design. To improve the efficiency and reduce the switching losses, a segmented synchronous control strategy based on zero-vector embedding is proposed in [8] to ensure good input-output performance. Ref. [9] proposes an improved space vector pulse width modulation strategy to enhance the system’s reliability, but its main circuit structure and control circuit are complex, with more switching elements and higher stress on the switching transistors. Ref. [10] proposes a control strategy that can govern AC bus harmonic currents to ensure that the microgrid has good power quality, but still cannot solve the problem of large turn-off losses. Ref. [11] proposes a diode-clamped three-level AC/DC converter with a composite control strategy combining PI control based on a rotating coordinate system and T/2 period repetition control to ensure dynamic performance and improve steady-state accuracy. However, the structure requires more power switching transistors, and the midpoint potential of the DC bus is prone to imbalance. Ref. [12] proposes a bidirectional isolated AC/DC matrix converter that can be suitable for bidirectional power flow with minimal high harmonics; however, the large number of power devices makes it require more circuit cost and makes it difficult to control. Combining the advantages of fewer switching devices, high power density, and significant common-mode interference capability, the bidirectional totem pole converter is widely used.

Bidirectional isolated DC/DC converters as systems backstage are usually classified into non-resonant or resonant topologies. The typical non-resonant topology is a dual active bridge converter (DAB) [13,14], which is easy to control and can achieve zero voltage switching (ZVS). When the switch transistor is turned off, however, the current flowing through is larger, the converter shutdown loss is larger, and the current harmonics flowing through the high frequency transformer are larger, which also increases transformer losses and reduces efficiency [15]. To achieve soft switching and improve efficiency, resonant converters are widely used and have been gradually developed from LC series-parallel structures to LLC [16,17], CLLC [18,19], and CLLLC [20,21] structures. The bidirectional LLC resonant converter can achieve ZVS and Zero Current Switching (ZCS) in forward operation, i.e., battery charging. The voltage gain, however, is less than 1 in the reverse operation, i.e., battery discharging, and soft switching cannot be achieved. Refs. [22,23] propose an inverter-phase shift control method to meet the gain requirement for reverse operation and achieve full-range soft switching under such control. Ref. [24] proposes a half-bridge three-level bidirectional LLC resonant converter with a three-stage hybrid control strategy combining “frequency, phase shift, and frequency burst” control methods to achieve high efficiency and wide-range voltage output. However, it is prone to inrush current and long commutation time during switching control. The bidirectional CLLC resonant converter is composed by adding a resonant capacitor to the secondary side of the resonant network and has similar characteristics to the LLC resonant converter in forward and reverse operation. A fixed-bus scheme is proposed in [25] for parameter design optimization, but the asymmetric resonant cavity structure and high coupling degree of the bidirectional CLLC resonant converter make the difference between forward and reverse operating characteristics relatively large and difficult to control. Compared with the bidirectional CLLC resonant converter, the bidirectional CLLLC resonant converter is a set of LC series resonant structures added on the secondary side, with symmetrical structure, consistent forward and reverse characteristics, low coupling degree, and easy control.

For the requirements of high efficiency and wide range, this paper proposes a two-stage isolated vehicle charger with a bidirectional totem pole structure in the front stage, which can realize power factor correction and provide stable bus voltage for the rear stage, and a bidirectional CLLLC resonant converter in the rear stage, which inherits the characteristics of the traditional LLC resonant converter such as wide range, soft switching, and high power density. The resonant network is symmetrical with identical forward and reverse operation characteristics to realize bidirectional boost conversion. Through the parameter design and characteristic analysis, the power components can realize full-range soft switching under full load and improve the system efficiency.

2. Bidirectional Isolation Type Charging System and Characterization

The main circuit topology of the two-stage bidirectional charging system designed in this paper is shown in Figure 2. The front stage is a bidirectional totem pole converter with a full bridge structure, and the rear stage is a bidirectional CLLLC resonant converter. This converter has a symmetrical structure with the same operating characteristics in forward and reverse operation, which has high efficiency.

During forward charging, the bidirectional totem pole converter achieves power factor correction and outputs a stable DC bus voltage V_dc. Power switches Q₁~Q₄ obtain drive signals to invert the DC voltage V_dc, Q₅~Q₈ pulse blocking, and body diodes D_q5~D_q8 conduct work to rectify the high-frequency signal on the secondary side of the transformer.

During reverse discharging, the power switch Q₅~Q₈ inverts the DC power into a high-frequency AC signal, Q₁~Q₄ pulse blocking, and the body diode D_q1~D_q4 completes the rectification function. Then the bidirectional totem pole converter achieves the inverter supply AC load power.

2.1. Modeling Analysis of Bidirectional Totem Pole Converter

For example, a bidirectional totem pole converter operating in forward charging mode and the grid voltage in the positive half cycle can be divided into two modes according to the on and off of the switching transistors. Its equivalent circuit is shown in Figure 3.

The matrix form of the equation of state when the switching transistor is on is:

$$\left[\begin{array}{c}\stackrel{•}{i_{\mathrm{ac}}(t)}\\ \stackrel{•}{v_{\mathrm{dc}}(t)}\end{array}\right]=\left[\begin{array}{cc}0& 0\\ 0& -\frac{1}{R{C}_{\mathrm{dc}}}\end{array}\right]\left[\begin{array}{c}{i}_{\mathrm{ac}}(t)\\ v_{\mathrm{dc}}(t)\end{array}\right]+\left[\begin{array}{c}\frac{1}{L}\\ 0\end{array}\right]\left[v_{\mathrm{in}}(t)\right]$$

(1)

where i_ac(t) is the AC current; v_dc(t) is the DC bus voltage; R is the equivalent resistance of the rear stage converter; C_dc is the DC bus capacitance; L is the AC inductance; v_in(t) is the grid voltage.

The coefficient matrix can be obtained as:

$${\mathit{A}}_{\mathbf{0}}=\left[\begin{array}{cc}0& 0\\ 0& -\frac{1}{R{C}_{\mathrm{dc}}}\end{array}\right],{\mathit{B}}_{\mathbf{0}}=\left[\begin{array}{c}\frac{1}{L}\\ 0\end{array}\right]$$

(2)

The matrix form of the equation of state when the switching transistor is turned off is:

$$\left[\begin{array}{c}\stackrel{•}{i_{\mathrm{ac}}(t)}\\ \stackrel{•}{v_{\mathrm{dc}}(t)}\end{array}\right]=\left[\begin{array}{cc}0& \frac{1}{L}\\ \frac{1}{C_{\mathrm{dc}}}& -\frac{1}{R{C}_{\mathrm{dc}}}\end{array}\right]\left[\begin{array}{c}{i}_{\mathrm{ac}}(t)\\ v_{\mathrm{dc}}(t)\end{array}\right]+\left[\begin{array}{c}\frac{1}{L}\\ 0\end{array}\right]\left[v_{\mathrm{in}}(t)\right]$$

(3)

The coefficient matrix can be obtained as:

$${\mathit{A}}_{\mathbf{1}}=\left[\begin{array}{cc}0& -\frac{1}{L}\\ \frac{1}{C_{\mathrm{dc}}}& -\frac{1}{R{C}_{\mathrm{dc}}}\end{array}\right],{\mathit{B}}_{\mathbf{1}}=\left[\begin{array}{c}\frac{1}{L}\\ 0\end{array}\right]$$

(4)

where A_0,B₀, A₁, B₁ are state coefficients.

Let the state vector x(t) = [i_ac(t) v_dc(t)]^T and the input vector u(t) = [v_in(t)], the steady-state expressions of the state vector and the input vector for the whole switching period T can be obtained by combining Equations (1)–(4) as follows:

$$\stackrel{•}{x}=[d{A}_{\mathbf{0}}+(1-d)A_{\mathbf{1}}]x+[d{B}_{\mathbf{0}}+(1-d)B_{\mathbf{1}}]u\hspace{1em}\hspace{1em}\hspace{1em}0\le t\le T$$

(5)

where d is the duty cycle.

The equation of state coefficients are:

$$\{\begin{array}{l}A=d{A}_{\mathbf{0}}+(1-d)A_{\mathbf{1}}=\left[\begin{array}{cc}0& -\frac{1-d}{L}\\ \frac{1-d}{C_{\mathrm{dc}}}& -\frac{1}{R{C}_{\mathrm{dc}}}\end{array}\right]\\ B=d{B}_{\mathbf{0}}+(1-d)B_{\mathbf{1}}=\left[\begin{array}{c}\frac{1}{L}\\ 0\end{array}\right]\end{array}$$

(6)

Add a perturbation to the steady-state Equation (5) such that:

$$\{\begin{array}{c}x=X+\stackrel{\wedge }{x}\\ u=U+\stackrel{\wedge }{u}\\ d=D+\stackrel{\wedge }{d}\end{array}$$

(7)

where X, U, and D are the steady-state values of the state vector, input vector, and duty cycle, respectively.

Substituting Equation (7) into Equation (5), we get:

$$\begin{array}{ll}\stackrel{•}{X}+\stackrel{\stackrel{•}{\wedge }}{x}=& [(D+\stackrel{\wedge }{d})A_{\mathbf{0}}+(1-D-\stackrel{\wedge }{d})A_{\mathbf{1}}](X+\stackrel{\wedge }{x})+\\ & [(D+\stackrel{\wedge }{d})B_{\mathbf{0}}+(1-D-\stackrel{\wedge }{d})B_{\mathbf{1}}](U+\stackrel{\wedge }{u})\end{array}$$

(8)

Neglecting the higher-order terms, Equation (8) can be decomposed into the steady state equation and the perturbation equation as Equations (9) and (10), respectively:

$$\stackrel{•}{X}=[D{A}_{\mathbf{0}}+(1-D)A_{\mathbf{1}}]X+[D{B}_{\mathbf{0}}+(1-D)B_{\mathbf{1}}]U$$

(9)

$$\begin{array}{ll}\stackrel{\stackrel{•}{\wedge }}{x}=& [D{A}_{\mathbf{0}}+(1-D)A_{\mathbf{1}}]\stackrel{\wedge }{x}+[D{B}_{\mathbf{0}}+(1-D)B_{\mathbf{1}}]\stackrel{\wedge }{u}+\\ & [X(A_{\mathbf{0}}-A_{\mathbf{1}})+U(B_{\mathbf{0}}-B_{\mathbf{1}})]\stackrel{\wedge }{d}+\\ & (A_{\mathbf{0}}-A_{\mathbf{1}})\stackrel{\wedge }{d}\stackrel{\wedge }{\mathit{x}}+(B_{\mathbf{0}}-{\mathit{B}}_{\mathbf{1}})\stackrel{\wedge }{d}\stackrel{\wedge }{u}\end{array}$$

(10)

Assume that the quadratic term of the small signal is much smaller than the remaining terms, i.e.,:

$$\begin{array}{l}|(A_{\mathbf{0}}-A_{\mathbf{1}})\stackrel{\wedge }{d}\stackrel{\wedge }{x}+(B_{\mathbf{0}}-B_{\mathbf{1}})\stackrel{\wedge }{d}\stackrel{\wedge }{u}|\ll |[D{A}_{\mathbf{0}}+(1-D)A_{\mathbf{1}}]\stackrel{\wedge }{x}+\\ [D{{\rm B}}_{\mathbf{0}}+(1-D)B_{\mathbf{1}}]\stackrel{\wedge }{u}+[X(A_{\mathbf{0}}-A_{\mathbf{1}})+U(B_{\mathbf{0}}-B_{\mathbf{1}})]\stackrel{\wedge }{d}|\end{array}$$

(11)

From this, neglecting the AC small signal product term in Equation (10), it is obtained that:

$$\stackrel{\stackrel{•}{\wedge }}{x}=A\stackrel{\wedge }{x}+B\stackrel{\wedge }{u}+[X(A_{\mathbf{0}}-A_{\mathbf{1}})+U(B_{\mathbf{0}}-B_{\mathbf{1}})]\stackrel{\wedge }{d}$$

(12)

Converting the time domain Equation (12) to the frequency domain equation yields:

$$s\stackrel{\wedge }{x(s)}=A\stackrel{\wedge }{x(s)}+B\stackrel{\wedge }{u(s)}+[X(A_{\mathbf{0}}-A_{\mathbf{1}})+U(B_{\mathbf{0}}-B_{\mathbf{1}})]\stackrel{\wedge }{d(s)}$$

(13)

And then we can get:

$$\stackrel{\wedge }{x(s)}={(sI-A)}^{-1}B\stackrel{\wedge }{u(s)}+{(sI-A)}^{-1}\cdot [X(A_{\mathbf{0}}-A_{\mathbf{1}})+U(B_{\mathbf{0}}-B_{\mathbf{1}})]\stackrel{\wedge }{d(s)}$$

(14)

where I is the unit matrix.

Substituting Equations (2), (4) and (6) into Equation (14), we get:

$$\begin{array}{ll}\left[\begin{array}{c}\stackrel{\wedge }{i_{\mathrm{ac}}(s)}\\ \stackrel{\wedge }{v_{\mathrm{dc}}(s)}\end{array}\right]=& {\left[\begin{array}{cc}s& \frac{1-D}{L}\\ -\frac{1-D}{C_{\mathrm{dc}}}& s+\frac{1}{R{C}_{\mathrm{dc}}}\end{array}\right]}^{-1}\left[\begin{array}{c}\frac{1}{L}\\ 0\end{array}\right]\left[\stackrel{\wedge }{v_{\mathrm{in}}(s)}\right]+\\ & {\left[\begin{array}{cc}s& \frac{1-D}{L}\\ -\frac{1-D}{C_{\mathrm{dc}}}& s+\frac{1}{R{C}_{\mathrm{dc}}}\end{array}\right]}^{-1}\left[\begin{array}{cc}0& \frac{1}{L}\\ -\frac{1}{C_{\mathrm{dc}}}& 0\end{array}\right]\left[\begin{array}{c}{I}_{\mathrm{ac}}\\ V_{\mathrm{dc}}\end{array}\right]\left[\stackrel{\wedge }{d(s)}\right]\end{array}$$

(15)

From the above equation, we get:

$$\stackrel{\wedge }{i_{\mathrm{a}\mathrm{c}}(s)}=\frac{s{C}_{\mathrm{d}\mathrm{c}}+\frac{1}{R}}{s^{2}L{C}_{\mathrm{d}\mathrm{c}}+s\frac{L}{R}+{(1-D)}^2}\stackrel{\wedge }{v_{\mathrm{i}\mathrm{n}}(s)}+\frac{(1-D)I_{\mathrm{a}\mathrm{c}}+(s{C}_{\mathrm{d}\mathrm{c}}+\frac{1}{R})V_{\mathrm{d}\mathrm{c}}}{s^{2}L{C}_{\mathrm{d}\mathrm{c}}+s\frac{L}{R}+{(1-D)}^2}\stackrel{\wedge }{d(s)}$$

(16)

$$\stackrel{\wedge }{v_{\mathrm{d}\mathrm{c}}(s)}=\frac{1-D}{s^{2}L{C}_{\mathrm{d}\mathrm{c}}+s\frac{L}{R}+{(1-D)}^2}\stackrel{\wedge }{v_{\mathrm{i}\mathrm{n}}(s)}+\frac{(1-D)V_{\mathrm{d}\mathrm{c}}-sL{I}_L}{s^{2}L{C}_{\mathrm{d}\mathrm{c}}+s\frac{L}{R}+{(1-D)}^2}\stackrel{\wedge }{d(s)}$$

(17)

From Equations (16) and (17), the transfer functions G_id(s) for input current versus duty cycle and G_vd(s) for bus voltage versus duty cycle are:

$$G_{\mathrm{i}\mathrm{d}}(s)=\frac{\stackrel{\wedge }{i_{\mathrm{a}\mathrm{c}}(s)}}{\stackrel{\wedge }{d(s)}}=\frac{(s{C}_{\mathrm{d}\mathrm{c}}+\frac{1}{R})V_{\mathrm{d}\mathrm{c}}}{s^{2}L{C}_{\mathrm{d}\mathrm{c}}+s\frac{L}{R}+{(1-D)}^2}$$

(18)

$$G_{v\mathrm{d}}(s)=\frac{\stackrel{\wedge }{v_{\mathrm{d}\mathrm{c}}(s)}}{\stackrel{\wedge }{d(s)}}=\frac{(1-D)V_{\mathrm{d}\mathrm{c}}}{s^{2}L{C}_{\mathrm{d}\mathrm{c}}+s\frac{L}{R}+{(1-D)}^2}$$

(19)

In the bidirectional totem pole converter circuit, there is the following relationship:

$$D=1-\frac{v_{\mathrm{in}}}{v_{\mathrm{d}\mathrm{c}}}$$

(20)

In the analysis and design of the control circuit, G_id(s) is the commonly used control object, where R, L, and C_dc are constants in the transfer function. At the same time, duty cycle D, AC input current I_ac, and output voltage V_o are the quantities that keep changing with normal operation. According to Equation (20), the factors affecting the duty cycle are the input voltage and the output voltage; when the input power is specific, the factor affecting the size of the AC input current is also the input voltage. There is a large filter capacitor at the output of the bidirectional totem pole converter circuit, so the output voltage does not vary much and can be neglected [26]. Therefore, the factor affecting G_id(s) is the magnitude of the input voltage. To analyze the effect of the input voltage on the transfer function, the Byrd diagram is drawn for different input voltage levels, as shown in Figure 4.

As seen in Figure 4, the low-frequency characteristics of G_id(s) are different for different input voltages, whereas the high-frequency characteristics are the same. The current loop deals with the high-frequency signal, so the influence of the low-frequency band can be ignored in the analysis, and then the control system can be designed.

2.2. Bidirectional CLLLC Resonant Converter Modeling

The fundamental wave analysis method is used to model the bidirectional CLLLC resonant converter. Then its equivalent circuit model is obtained to analyze the characteristics of the bidirectional CLLLC resonant converter.

2.2.1. Equivalent Circuit Model

Taking forward operation as an example, the alternating conduction of power switches Q₁ to Q₄ makes the input voltage v_ab of the resonant network a square wave signal with amplitude varying from −V_dc to V_dc, for which the Fourier expansion is carried out to obtain the following expression:

$$v_{\mathrm{a}\mathrm{b}}(t)=\frac{4V_{\mathrm{d}\mathrm{c}}}{\pi }{\displaystyle \sum _{m=1,3,5\cdots }^{\infty }\frac{1}{m}\sin (2\pi m{f}_{s}t)}$$

(21)

where m is an integer parameter; f_s is the switching frequency.

From Equation (21), the fundamental components of v_ab and their RMS values are:

$$v_{\mathrm{a}\mathrm{b}\_\mathrm{F}\mathrm{H}\mathrm{A}}=\frac{4V_{\mathrm{d}\mathrm{c}}}{\pi }\sin (2\pi f_{s}t)$$

(22)

$$V_{\mathrm{a}\mathrm{b}\_\mathrm{F}\mathrm{H}\mathrm{A}}=\frac{2\sqrt{2}{V}_{\mathrm{d}\mathrm{c}}}{\pi }$$

(23)

Similarly, the output voltage v_cd, the fundamental component of the output voltage v_{cd_FHA,} and its RMS value V_{cd_FHA} are obtained as follows:

$$v_{\mathrm{cd}}(t)=\frac{4V_{\mathrm{o}}}{\pi }{\displaystyle \sum _{m=1,3,5\cdots }^{\infty }\frac{1}{m}\sin (2\pi m{f}_{\mathrm{s}}t-\theta )}$$

(24)

$$v_{\mathrm{c}\mathrm{d}\_\mathrm{F}\mathrm{H}\mathrm{A}}=\frac{4V_{\mathrm{o}}}{\pi }\sin (2\pi f_{\mathrm{s}}t-\theta )$$

(25)

$$V_{\mathrm{c}\mathrm{d}\_\mathrm{F}\mathrm{H}\mathrm{A}}=\frac{2\sqrt{2}{V}_{\mathrm{o}}}{\pi }$$

(26)

where θ is the phase difference between v_ab and v_cd.

Equating the load at the output to the resistance R_o, the expression of the output current of the resonant network is:

$$i_{\mathrm{L}\mathrm{s}}(t)=\sqrt{2}{I}_{\mathrm{L}\mathrm{s}}\sin (2\pi f_{\mathrm{s}}t-\theta )$$

(27)

where I_Ls is the RMS value of the output current of the resonant network.

From Equation (27), the average value of the output current is:

$$I_{\mathrm{o}}=\frac{2}{T_{\mathrm{s}}}{\displaystyle {\int }_0^{\frac{T_{\mathrm{s}}}{2}}\left|i_{\mathrm{L}\mathrm{s}}(t)\right|}dt=\frac{2\sqrt{2}}{\pi }{I}_{\mathrm{L}\mathrm{s}}$$

(28)

And because v_{cd_FHA} is in phase with i_Ls, the rectifier network, as well as the output load, can be equated to a purely resistive load, i.e.,

$$V_{\mathrm{c}\mathrm{d}\_\mathrm{F}\mathrm{H}\mathrm{A}}=\frac{2\sqrt{2}{V}_{\mathrm{o}}}{\pi }$$

(29)

Converting the secondary components of the transformer to the primary side, we get:

$$\begin{array}{l}{R}_{\mathrm{e}\mathrm{q}}=n^2{R}_{\mathrm{o}.\mathrm{e}\mathrm{q}}=\frac{8n^2}{{\pi }^2}{R}_{\mathrm{o}}\\ C_{\mathrm{s}}^{´}=\frac{C_{\mathrm{s}}}{n^2}\\ L_{\mathrm{s}}^{´}=n^2{L}_{\mathrm{s}}\end{array}$$

(30)

where R_eq is the resistance converted to the primary side; C_s^′ is the capacitance converted to the primary side; L_s^′ is the inductance converted to the primary side; n is the transformer ratio.

In summary, the voltages at points a and b on the primary side of the transformer are v_{ab_FHA}(t), and the voltages between points c and d on the secondary side are converted to nv_{cd_FHA}(t) on the primary side, while the capacitance inductance on the secondary side is converted to the primary side, resulting in the equivalent circuit model of the rear stage converter, as shown in Figure 5.

2.2.2. Characteristic Analysis

The following is a characterization of the bidirectional CLLLC resonant converter, including voltage gain characteristics, impedance characteristics, inductance coefficient, and quality factor.

• Voltage Gain Characteristics

M is the DC voltage gain characteristic of the CLLLC resonant converter, whose expression is:

$$M(f_{\mathrm{n}})=\frac{1}{\sqrt{{(1+\frac{1}{k}-\frac{1}{k{f}_{\mathrm{n}}^2})}^2+{[Q{f}_{\mathrm{n}}(2+\frac{1}{k})-\frac{Q}{f_{\mathrm{n}}}(2+\frac{2}{k})+\frac{Q}{k{f}_{\mathrm{n}}^3}]}^2}}$$

(31)

where f_n is the normalized frequency, k is the inductance factor, and Q is the quality factor. The expressions are:

$$\begin{array}{c}{f}_n=\frac{f_s}{f_{r1}}\\ k=\frac{L_m}{L_p}\\ Q=\frac{\sqrt{L_p/C_p}}{{\mathrm{R}}_{eq}}\end{array}$$

(32)

where f_r1 is the resonant frequency of the resonant inductor and resonant capacitor of the transformer, i.e., the resonant frequency of L_p, C_p, or L_s, C_s; f_s is the switching frequency.

As seen from Equation (32), the main parameters affecting the voltage gain are k and Q. If the quality factor Q = 0.5, the change law of voltage gain with normalized frequency for different k values is shown in Figure 6.

When the Q value is specific, the maximum voltage gain value of the resonant converter gradually decreases with the increase of the k value, the corresponding normalized frequency gradually decreases, and the curve has a trough after the highest point. On the right side of the resonance point, the smaller the k value is, the faster the voltage gain changes with the normalized frequency, which benefits the voltage gain regulation [27].

When the inductance coefficient k = 2, the curves of voltage gain with f_n change at different Q values are shown in Figure 7.

When the value of k is specific, and the normalized frequency is less than 1, the Q value is small, the voltage gain of the converter is wide, and the voltage regulation rate is fast. In contrast, when the normalized frequency is greater than 1, the voltage gain of the converter is narrow, and the voltage regulation rate is relatively flat, which will not meet the requirements of the system. When the Q value is too large, the voltage gain curve has two peak points when the switching frequency is less than the resonant frequency, which is unsuitable for the converter’s stability and the control system’s design. At more significant values than the resonant frequency, the gain curve of the converter gradually becomes steeper, but the peak gain may not meet the system requirements for voltage gain. Therefore, the Q value is too large or too small to meet the design requirements, and a compromise should be made in the specific selection process.

2.

Impedance Characteristics Analysis

According to Figure 5, the following impedances are defined:

$$\{\begin{array}{c}{Z}_1=j{\omega }_{\mathrm{s}}{L}_{\mathrm{p}}+1/(j{\omega }_{\mathrm{s}}{C}_{\mathrm{p}})\\ Z_2=j{\omega }_{\mathrm{s}}{L}_{\mathrm{s}}^{´}+1/(j{\omega }_{\mathrm{s}}{C}_{\mathrm{s}}^{\prime })\\ Z_{\mathrm{m}}=j{\omega }_{\mathrm{s}}{L}_{\mathrm{m}}\end{array}$$

(33)

where Z₁ is the primary series resonant impedance; Z₂ is the equivalent secondary series resonant impedance; Z_m is the excitation inductance impedance; ω_s = 2πf_s is the switching angle frequency.

The input impedance is:

$$Z_{\mathrm{in}}=Z_1+Z_{\mathrm{m}}//(Z_2+R_{\mathrm{eq}})$$

(34)

The imaginary part:

$$\mathrm{Im}(Z_{\mathrm{in}})=\frac{R_{\mathrm{eq}}Q((k+1)f_n^3-f_{\mathrm{n}})[Q^2((2k+1)f_{\mathrm{n}}^2-1)(f_{\mathrm{n}}^2-1)+f_{\mathrm{n}}^2]}{f_{\mathrm{n}}^4+Q^2{(f_{\mathrm{n}}-(k+1)f_{\mathrm{n}}^3)}^2}$$

(35)

Let Equation (35) be 0, then:

$$\{\begin{array}{c}Q=\frac{f_{\mathrm{n}}}{\sqrt{(1-f_{\mathrm{n}}^2)[(2k+1)f_{\mathrm{n}}^2-1]}}\\ f_{\mathrm{n}1}=\frac{1}{\sqrt{k+1}}\end{array}$$

(36)

Substituting Equation (36) into Equation (31), we get M = 1, and then according to Im(Z_in)> 0 when f_n > 1, we can get the resistive divider of the bidirectional CLLLC resonant converter as shown in Figure 8.

As seen from Figure 8, the overlap area on the upper side of the line M = 1 and the right side of f_n = (k + 1)^−1/2 is the inductive region. The inductive region in the region where f_n > 1 can realize the ZVS of the switching transistor, and in the process of designing k and Q it is essential to ensure that the curve falls within these two regions.

3.

Design Conditions for the Inductance Factor K and Quality Factor Q

The bidirectional CLLLC resonant converter needs to meet the voltage gain requirement. At no-load Q = 0, the voltage gain is:

$${M(f_{\mathrm{n}\_\max })|}_{Q=0}=\frac{1}{1+\frac{1}{k}-\frac{1}{k{f}_{\mathrm{n}\_\max }^2}}$$

(37)

The minimum voltage gain M_min satisfies:

$$M_{\min }>{M(f_{\mathrm{n}\_\max })|}_{Q=0}$$

(38)

This leads to the design condition of the inductance coefficient k:

$$k<\frac{M_{\min }(f_{\mathrm{n}\_\max }^2-1)}{(1-M_{\min })f_{\mathrm{n}\_\max }^2}$$

(39)

As can be seen from Figure 8, in f_n > 1, the voltage gain curve is located in the inductive region and monotonically decreasing; in the area of 1/(k + 1)^1/2 < f_n < 1, the voltage gain curve may be located outside the inductive area and may not appear monotonically, to meet the requirements, Q needs to meet certain conditions, thus the following focus on this operating frequency range. To meet the ZVS condition of the switching transistor, Im(Z_in) > 0 should be satisfied. Then:

$$Q_{\max 1}<F_1(f_{\mathrm{n}})=\frac{f_{\mathrm{n}}}{\sqrt{(1-f_{\mathrm{n}}^2)[(2k+1)f_{\mathrm{n}}^2-1]}}$$

(40)

Let F₁^′(f_n) = 0; then there is a unique solution in the range of 1/(k + 1)^1/2 < f_n < 1; that is, f_n1 = 1/(2k + 1)^1/4, which is a minimal value, and which is substituted into the equation F₁(f_n) to get:

$$Q_{\max 1}<\frac{1}{\sqrt{2k+1}-1}$$

(41)

To make the voltage gain curve monotonically decreasing, we have:

$$M^{´}(f_{\mathrm{n}})=\frac{-\frac{2}{k}{f}_{\mathrm{n}}^{4}A(f_{\mathrm{n}})-Q^2{f}_{\mathrm{n}}^{2}B(f_{\mathrm{n}})C(f_{\mathrm{n}})}{{[f_{\mathrm{n}}^2{A}^2(f_{\mathrm{n}})+Q^2{B}^2(f_{\mathrm{n}})]}^{\frac{3}{2}}}<0$$

(42)

$$\{\begin{array}{c}A(f_{\mathrm{n}})=f_{\mathrm{n}}^2(1+\frac{1}{k})-\frac{1}{k}\\ B(f_{\mathrm{n}})=f_{\mathrm{n}}^4(2+\frac{1}{k})-f_{\mathrm{n}}^2(2+\frac{2}{k})+\frac{1}{k}\\ C(f_{\mathrm{n}})=f_{\mathrm{n}}^4(2+\frac{1}{k})+f_{\mathrm{n}}^2(2+\frac{2}{k})-\frac{3}{k}\end{array}$$

(43)

In the range of 1/(k + 1)^1/2 < f_n < 1, A(f_n) > 0, B(f_n) < 0, and C(f_n) there exists a zero point for:

$$f_{\mathrm{n}2}=\sqrt{\frac{-(k+1)+\sqrt{4+8k+k^2}}{2k+1}}$$

(44)

It is known that f_n2 < f_n1 and C(f_n) > 0 in the range f_n1 < f_n < 1. To make M′(f_n) less than 0, it follows that:

$$Q_{\max 2}<F_2(f_{\mathrm{n}})=\sqrt{\frac{-\frac{2}{k}{f}_{\mathrm{n}}^{2}A(f_{\mathrm{n}})}{B(f_{\mathrm{n}})C(f_{\mathrm{n}})}}$$

(45)

In summary, two constraints on the quality factor Q are obtained.

3. Control Strategy of the Charging System

The block diagram of the bidirectional charging system control strategy is shown in Figure 9. The front-stage bidirectional totem pole converter adopts a voltage and current double closed-loop control, and the dc bus voltage v_dc is compared with the reference voltage v_{dc_ref} to obtain the error v_err; the error v_err is first passed through the transfer function G_v(s) of the voltage loop PI controller, and then multiplied by the v_shape obtained through the phase-locked loop PLL to get further the current reference which is consistent with the phase of the ac input voltage i_{ac_ref}, and then make a difference with the sampled input current i_ac, the result i_err after the current loop PI controller transfer function G_i(s) for Sinusoidal Pulse Width Modulation (SPWM), the output signal through the drive circuit to control the switching transistor on and off.

The back-stage bidirectional CLLLC resonant converter adopts frequency conversion control; when working in the forward operation, the actual output voltage V_o and the given voltage V_{o_ref} make a difference through the PI regulator and for limiting, and then through the pulse frequency modulation (PFM) and the driver module to control the switch transistor Q₁~Q₄ on and off; at this time the secondary side switch transistor is only renewed by the body diode. The control in the reverse operation is similar to that in the forward movement and will not be described in detail here.

To improve the power factor, the input current of the bidirectional totem pole converter should accurately track the input voltage, thus requiring the current inner loop for regulation; the normal operation of the backstage CLLLC resonant converter requires a stable DC voltage output from the front stage, thus requiring the voltage outer loop for regulation. The voltage and current double closed-loop controller design will be carried out below.

3.1. Current Internal Loop Controller Design

The current in-loop controller is shown in Figure 10, where G_id(s) is the transfer function of the input current versus the duty cycle.

The expression for the PI controller G_i(s) is:

$$G_{\mathrm{i}}(s)=k_{\mathrm{ip}}+\frac{k_{\mathrm{ii}}}{s}$$

(46)

where k_ip is the proportionality factor; k_ii is the integration factor.

From Figure 10, the current loop open-loop transfer function is:

$$G_{\mathrm{io}}(s)=G_{\mathrm{i}}(s)G_{\mathrm{id}}(s)=\frac{(k_{\mathrm{ip}}s+k_{\mathrm{ii}})V_{\mathrm{dc}}}{s^{2}L}$$

(47)

Let s = jω be substituted in the above equation to get:

$$G_{\mathrm{io}}(\mathrm{j}\omega )=\frac{(\mathrm{j}{k}_{\mathrm{ip}}\omega +k_{\mathrm{ii}})V_{\mathrm{dc}}}{-{\omega }^{2}L}$$

(48)

The corresponding amplitude-frequency characteristics and phase frequency characteristics are:

$$\{\begin{array}{c}{L}_{\mathrm{io}}(\omega )=20\log \left|G_{\mathrm{io}}(\mathrm{j}\omega )\right|=20\log \left(\frac{V_{\mathrm{dc}}\sqrt{{\omega }^2{k}_{\mathrm{ip}}^2+k_{\mathrm{ii}}^2}}{{\omega }^{2}L}\right)\\ {\phi }_{\mathrm{io}}(\omega )=\arctan (\frac{k_{\mathrm{ip}}\omega }{k_{\mathrm{ii}}})-{180}^{\circ }\end{array}$$

(49)

To ensure the stability of the system, in general, the Bode diagram crossing frequency of the corrected open-loop transfer function is lower than 1/10 of the switching frequency. The switching frequency of the bidirectional totem pole converter in this design is 50 kHz, so the cutoff frequency is selected as 5 kHz, i.e., ω_c = 2πf_s = 3.14 × 10⁴ rad/s, while keeping the phase margin as γ_i = 45°. Substituting the design conditions to Equation (49) to obtain:

$$\{\begin{array}{c}\frac{V_{\mathrm{dc}}\sqrt{{\omega }_{\mathrm{ic}}^2{k}_{\mathrm{ip}}^2+k_{\mathrm{ii}}^2}}{{\omega }_{\mathrm{ic}}^{2}L}=1\\ {180}^{\circ }+\arctan (\frac{k_{\mathrm{ip}}{\omega }_{\mathrm{ic}}}{k_{\mathrm{ii}}})-{180}^{\circ }={\gamma }_{\mathrm{i}}\end{array}$$

(50)

From Equation (50), we obtain k_ip = 0.2137 and k_ii = 6710. The open-loop Bode diagram of the current loop before and after correction of the system is shown in Figure 11; the cut-off frequency of the system after modification is 5 kHz, and the phase margin is 45°, so the system can reach the steady state to meet the design requirements.

3.2. Voltage Outer Loop Controller Design

A simplified controller can be obtained by putting the current loop regulation link as a whole into the block diagram of the voltage outer loop, as shown in Figure 12.

The transfer function of the voltage loop PI compensator is:

$$G_{\mathrm{v}}(s)=k_{\mathrm{vp}}+\frac{k_{\mathrm{vi}}}{s}$$

(51)

where k_vp is the proportionality factor; k_vi is the integration factor.

The current closed-loop transfer function is:

$$G_{\mathrm{ic}}(s)=\frac{G_{\mathrm{io}}(s)}{1+G_{\mathrm{io}}(s)}=\frac{(k_{\mathrm{ip}}s+k_{\mathrm{ii}})V_{\mathrm{dc}}}{s^{2}L+(k_{\mathrm{ip}}s+k_{\mathrm{ii}})V_{\mathrm{dc}}}$$

(52)

G_iv(s) is the transfer function that represents the relationship between input current and output voltage, which can be obtained from Equations (18) and (19):

$$G_{\mathrm{vi}}(s)=\frac{G_{\mathrm{vd}}(s)}{G_{\mathrm{id}}(s)}=\frac{(1-D)R}{sCR+1}$$

(53)

From Equations (51)–(53), the open-loop transmission of the voltage loop before correction is as follows:

$$\begin{array}{ll}{G}_{\mathrm{vob}}(s)& = G_{\mathrm{ic}}(s)\times G_{\mathrm{vi}}(s)=\frac{(k_{\mathrm{ip}}s+k_{\mathrm{ii}})V_{\mathrm{dc}}}{s^{2}L+(k_{\mathrm{ip}}s+k_{\mathrm{ii}})V_{\mathrm{dc}}}\times \frac{(1-D)R}{sCR+1}\\ & =\frac{(0.2137s+6710)\times 400}{s^2\times 3.85\times {10}^{-3}+(0.2137s+6710)\times 400}\times \frac{0.55\times 533}{s\times 330\times {10}^{-6}\times 533+1}\\ & \approx \frac{25060s+7868\times {10}^5}{6.772\times {10}^{-4}{s}^3+15.04s^2+4722\times {10}^{2}s+2684\times {10}^3}\end{array}$$

(54)

The open-loop transfer function of the corrected voltage loop is:

$$G_{\mathrm{vo}}(s)=G_{\mathrm{v}}(s)G_{\mathrm{vob}}(s)=\frac{(k_{\mathrm{vp}}s+k_{\mathrm{vi}})(k_{\mathrm{ip}}s+k_{\mathrm{ii}})V_{\mathrm{dc}}(1-D)R}{s[s^{2}L+(k_{\mathrm{ip}}s+k_{\mathrm{ii}})V_{\mathrm{dc}}](sCR+1)}$$

(55)

To reduce the output voltage ripple, the cutoff frequency of the voltage loop is set to 10 Hz, i.e., ω_vc = 62.8 rad/s, and the phase margin is set to 45°. Substitute s = jω into Equation (55) to obtain the corresponding amplitude and phase frequency characteristics as:

$$\{\begin{array}{c}{L}_{\mathrm{v}}({\omega }_{\mathrm{vc}})=1\\ 180^{\circ }+{\phi }_{\mathrm{v}}({\omega }_{\mathrm{vc}})={45}^{\circ }\end{array}$$

(56)

From the above equation, k_vp = 0.0242 and k_vi = 1.822. The open-loop Bode diagram of the voltage loop before and after correction of the system is shown in Figure 13. The cutoff frequency of the system before correction is 290 Hz, which becomes 10.1 Hz after correction, and the phase margin also becomes 46°, which shows that the PI controller meets the expected design requirements.

3.3. Control of Soft Start

After the optimization of the relevant coefficients, in order to ensure that the system can achieve the desired control objectives, realize safe and reliable operation, significantly improve the system operating efficiency and reduce the occurrence of faults, it is necessary to propose a highly efficient control method of frequency conversion for the current operating characteristics of the system, so as to achieve the rationalization of resource utilization. In addition, the use of a high-efficiency control strategy can also improve the shock resistance, form a favorable protection for capacitors, and further optimize the system to ensure that the CLLLC resonant converter has a soft-start function and can smoothly complete the continuous output of voltage, so it can be seen that the application of a control strategy is extremely important. At the same time, the resonant converter uses PFM control during the operation phase, and this control system has certain special features that need to be adjusted to the maximum value when the load is light, combined with the relevant switching frequency theory, in order to ensure the actual efficacy [28]. Therefore, in order to improve the utilization of the inverter controller, relevant research in the CLLLC resonant converter, in which soft-start control is more effective, is carried out.

The application of soft-start control to the inverter system can complete the improvement of the system performance and make the system performance more smoother. For the CLLLC resonant converter the role for the application range expansion gradually presents itself. When in normal start, usually, it will be in a default state, allowing the primary side capacitor to complete charging, when the output voltage is 0 [29]. Based on such a premise, the signal based on PFM control can be used directly to complete the drive to control the primary side switch, as can be seen from the equivalent circuit in Figure 5; the output voltage of the bridge arm has all been added to the CLLLC resonance, and on this basis it can complete the charging of the output capacitor is on the secondary side; it is worth noting that in this process there will be a large current surge. Based on such a situation, the probability of breakdown of the switching transistor will increase, over-voltage problems will occur, resulting in damage to the resonant capacitor, and the safety of the output capacitor cannot be guaranteed. In a word, simple high-frequency starting cannot be equated with an ideal starting effect, and a soft start must be invoked on the basis of the original control strategy to ensure that the CLLLC functionality is brought into play and its safe starting operation is ensured.

The soft start of the CLLLC resonant converter is a dynamic response process. In the process of soft start, the frequency change is very large. First, in the initial stage of the soft start, the frequency must be increased to a relatively high level, thus reducing the voltage and current stress in the resonant cavity. Then the frequency is slowly reduced, gradually dropping to the resonant frequency point and gradually building up the output voltage.

Commonly used frequency reduction methods are shown in Figure 14, Frequency reduction method 1 for uniform frequency reduction; that is, in the start-up process of the switching frequency proportional to time, from the maximum start the frequency f_max began to decline at a uniform rate, and the end of the start-up the frequency is equal to the circuit operating frequency. Frequency reduction method 2 is improved on the basis of the former circuit to establish the initial stage of resonant network energy with a faster rate of frequency reduction, to complete and then to reduce the relatively slower switching frequency to complete the process of establishing the output voltage until the start-up is completed. Frequency reduction method 3 uses the exponential function to calculate the switching frequency at each moment, but its decreasing speed is faster than the linear downscaling speed, which generates a larger current overshoot when the CLLLC resonant converter does not reach the steady state [30]. Therefore, the first frequency reduction method is used in this paper.

In this paper, the soft start of the resonant converter is completed by a high-frequency soft-start strategy under a PI regulator. The switching frequency is increased to 150 kHz at start-up, and then the switching frequency is slowly reduced to 100 kHz, and the voltage gain is gradually increased to complete the soft start. The comparison graph of resonant current with and without a soft start in forward operating mode is shown in Figure 15. From the figure, it can be seen that, in both cases, the bidirectional CLLLC resonant converter is started from 0.004 s, and the resonant current to the device is much smaller when a soft start is adopted compared with when no soft start is taken. Comparison of the secondary side output current is shown in Figure 16. In the circuit without a soft start, the inrush current can reach 180 A, which is very dangerous for the circuit, while in a soft-start circuit the inrush current does not exceed 50 A and quickly falls to less than 15 A, indicating that a soft start for the circuit as well as the power switching transistor has a better protection effect.

4. Parameter Design of Charging System

The whole parameters of the charging system are designed as shown in

Table 1. Design of the charging system.

Symbol	Description	Value
Vin	AC input voltage range	176–264 V
Vin_rated	Rated AC side input voltage	220 V
Vdc	DC bus voltage range	380–420 V
Vdc_rated	Rated DC bus voltage	400 V
Vo	DC output voltage range	44–56 V
Vo_rated	Rated DC output voltage	48 V
Po	Rated power	300 W
fs	Switching frequency	50–150 kHz
fr1	Resonant frequency	100 kHz
η	Efficiency	95%

.

4.1. Parameter Design of Bidirectional Totem Pole Changer

The inductor-capacitor is particularly important when performing the bidirectional totem pole parameter design. The design of the inductor-capacitor is carried out according to the design index of the whole charging system. At the same time, the powerswitching transistor is determined by the voltage, current, and other related parameters [31].

• AC Inductance

The inductor stores and releases electrical energy during circuit operation and is generally designed to operate at the lowest input voltage.

Since the efficiency of the whole machine is 95%, the maximum input power of the circuit at rated condition P_in is:

$$P_{\mathrm{in}}=\frac{P_{\mathrm{o}}}{\eta }=\frac{300}{95\%}\approx 316(\mathrm{W})$$

(57)

where P_o is the output power; η is the efficiency.

Assuming a maximum grid voltage fluctuation of 20%, when the input voltage minimum RMS value is V_{in(min)_rms} = 176 V, the input current maximum RMS value I_rms(max) is:

$$I_{\mathrm{r}\mathrm{m}\mathrm{s}(\max )}=\frac{P_{\mathrm{i}\mathrm{n}}}{V_{\mathrm{i}\mathrm{n}(\min )\_\mathrm{r}\mathrm{m}\mathrm{s}}}=\frac{316}{176}\approx 1.80(\mathrm{A})$$

(58)

The peak input current I_peak is:

$$I_{\mathrm{p}\mathrm{e}\mathrm{a}\mathrm{k}}=\sqrt{2}{I}_{\mathrm{r}\mathrm{m}\mathrm{s}(\max )}=2.55(\mathrm{A})$$

(59)

The size of the inductor is related to the size of the ripple of the input current. Assuming that the ripple coefficient of the input current is 20%, the ripple current ΔI is:

$$\mathrm{\Delta }I=20\%I_{\mathrm{p}\mathrm{e}\mathrm{a}\mathrm{k}}=20\%\times 2.55=0.51(\mathrm{A})$$

(60)

The duty cycle D at the time of the maximum peak of the input current is:

$$D=1-\frac{V_{\mathrm{i}\mathrm{n}(\min )\_\mathrm{p}\mathrm{e}\mathrm{a}\mathrm{k}}}{V_{\mathrm{d}\mathrm{c}\_\mathrm{r}\mathrm{a}\mathrm{t}\mathrm{e}\mathrm{d}}}=1-\frac{176\sqrt{2}}{400}\approx 0.3777$$

(61)

Therefore, the AC inductance is:

$$L\ge \frac{V_{\mathrm{i}\mathrm{n}(\min )\_\mathrm{p}\mathrm{e}\mathrm{a}\mathrm{k}}D}{f_{\mathrm{s}}\mathrm{\Delta }I}=\frac{176\sqrt{2}\times 0.3777}{50\times {10}^3\times 0.51}\approx 3.69(\mathrm{m}\mathrm{H})$$

(62)

where V_in(min)peak is the peak voltage of the minimum input voltage; f_s is the switching frequency.

2.

DC Bus Capacitance

When designing a capacitor, if the maintenance time is used as a limiting condition, the difference between the energy on the capacitor before and after the energy cutoff at the input is equal to the energy consumed by the load during the maintenance time. Therefore:

$$C=\frac{2P_{\mathrm{o}}\mathrm{\Delta }t}{V_{\mathrm{d}\mathrm{c}\_\mathrm{r}\mathrm{a}\mathrm{t}\mathrm{e}\mathrm{d}}^2-V_{\mathrm{d}\mathrm{c}(\min )}^2}=\frac{2\times 300\times 0.02}{{400}^2-{(0.8\times 400)}^2}\approx 208(\mathsf{\mu }\mathrm{F})$$

(63)

where Δt is the maintenance time; V_dc is the output voltage; V_dc(min) is the minimum capacitance-voltage value allowed after the energy cutoff at the input.

If output voltage ripple is used as a limiting condition, a compromise must be made in designing the capacitor so that the capacitor size and cost are in the correct range.

Assuming a maximum output voltage ripple of 5% of the output voltage, then:

$$\frac{\mathrm{\Delta }{V}_{\mathrm{c}\mathrm{p}\mathrm{p}}}{V_{\mathrm{d}\mathrm{c}}}=\frac{I_{\mathrm{o}}}{\omega C{V}_{\mathrm{d}\mathrm{c}\_\mathrm{r}\mathrm{a}\mathrm{t}\mathrm{e}\mathrm{d}}}\le 5\%$$

(64)

where ΔV_cpp is the peak-to-peak value of the ripple.

Therefore:

$$C\ge \frac{I_{\mathrm{o}}}{0.05\omega V_{\mathrm{d}\mathrm{c}\_\mathrm{r}\mathrm{a}\mathrm{t}\mathrm{e}\mathrm{d}}}\approx 119(\mathsf{\mu }\mathrm{F})$$

(65)

To meet the requirements of voltage maintenance time and output voltage ripple, the DC bus capacitor should be selected as a more significant value and retain a certain margin. In this paper, a 450 V/330 μF electrolytic capacitor is selected.

3.

Power Switching Transistor Selection

In general, if the withstand voltage of the switching transistor is 1.2–1.5 times the rated withstand voltage, and the withstand current can be considered as 1.5–2 times the margin, then:

$$\{\begin{array}{c}{V}_{\mathrm{V}\mathrm{E}\mathrm{M}}>1.5V_{\mathrm{d}\mathrm{c}\_\mathrm{r}\mathrm{a}\mathrm{t}\mathrm{e}\mathrm{d}}=1.5\times 400=600(V)\\ I_{\mathrm{V}\mathrm{E}\mathrm{M}}>2I_{\mathrm{p}\mathrm{e}\mathrm{a}\mathrm{k}}=2\times 2.55=5.1(A)\end{array}$$

(66)

As can be seen from (66), the rated voltage of the power switching transistor should be not less than 600 V, the rated current should be not less than 600 V, and the rated current should be not less than 5.1 A. Therefore, the selected power switching transistor is IPD65R420CFDA, whose minimum drain breakdown voltage is 650 V and whose maximum continuous drain current at 25 °C is 8.7 A, all of which meet the circuit requirements.

4.2. Parameter Design of Bidirectional CLLLC Resonant Changer

The parameters of the bidirectional CLLLC resonant converter are designed according to the design index of the charging system, and mainly for the design of the transformer, resonant inductor-capacitor design, and power switch transistor selection.

• Transformer Turns Ratio

At the rated operating point, the transformer turns ratio is:

$$n=\frac{V_{\mathrm{dc}\_\mathrm{rated}}}{V_{\mathrm{o}}}=\frac{400}{48}\approx 8.333$$

(67)

2.

The Maximum and Minimum Voltage Gain of the Transformer

According to the voltage range of DC input and output, the maximum voltage gain and minimum voltage gain of the transformer can be obtained as:

$$\begin{array}{l}{M}_{\max }=\frac{n{V}_{\mathrm{o}\_\max }}{V_{\mathrm{dc}\_\min }}\approx 1.228\\ M_{\min }=\frac{n{V}_{\mathrm{o}\_\min }}{V_{\mathrm{dc}\_\max }}\approx 0.794\end{array}$$

(68)

3.

Inductance Factor K and Quality Factor Q

The maximum operating frequency is 150 kHz, and according to Equation (39), the inductance coefficient is:

$$k<\frac{M_{\min }(f_{\mathrm{n}\_\max }^2-1)}{(1-M_{\min })f_{\mathrm{n}\_\max }^2}\approx 2.141$$

(69)

Under the consideration of converter efficiency and limitation, the larger the choice of k, the better, so k is taken as 2. Substituting the value of k into Equation (41), we get:

$$Q_{\max 1}<\frac{1}{\sqrt{2k+1}-1}\approx 0.809$$

(70)

Then, according to Equation (45), we can see that:

$$Q_{\max 2}<F_2(f_{\mathrm{n}})=\sqrt{\frac{-\frac{2}{k}{f}_{\mathrm{n}}^{2}A(f_{\mathrm{n}})}{B(f_{\mathrm{n}})C(f_{\mathrm{n}})}}\approx 0.706$$

(71)

Combined with Equations (70) and (71), and Figure 8, Q = 0.5 is selected. At this time, the voltage gain curve is located within the inductive region near the resonance point. The maximum and minimum gain requirements can be met by more minor frequency adjustments and remain monotonic.

4.

Resonant Inductance and Capacitance

The equivalent impedance of the converter is:

$$R_{\mathrm{eq}}=\frac{8n^2}{{\pi }^2}{R}_{\mathrm{o}}=432.3\mathrm{\Omega }$$

(72)

Then the parameters of the original secondary resonant inductor and resonant capacitor are:

$$\{\begin{array}{c}{L}_{\mathrm{p}}=\frac{Q{R}_{\mathrm{eq}}}{2\pi f_{\mathrm{r}1}}=344.01\mathsf{\mu }\mathrm{H}\\ C_{\mathrm{p}}=\frac{1}{{(2\pi f_{\mathrm{r}1})}^2{L}_{\mathrm{p}}}=7.36\mathrm{n}\mathrm{F}\\ L_{\mathrm{s}}=\frac{L_{\mathrm{p}}}{n^2}=4.95\mathsf{\mu }\mathrm{H}\\ C_{\mathrm{s}}=n^2{C}_{\mathrm{p}}=0.51\mathsf{\mu }\mathrm{F}\\ L_{\mathrm{m}}=k{L}_{\mathrm{p}}=688.02\mathsf{\mu }\mathrm{H}\end{array}$$

(73)

5.

The Selection of Power Switching

In forward operation, the effective value of the primary resonant current is:

$$I_{\mathrm{p}\_\mathrm{rms}1}=\sqrt{\frac{V_{\mathrm{o}\_\mathrm{rated}}^2}{8}[{(\frac{n}{2f_{\mathrm{r}1}{L}_{\mathrm{m}}})}^2+{(\frac{\pi }{n{R}_{\mathrm{o}}})}^2]}\approx 1.323\mathrm{A}$$

(74)

The effective value of the secondary resonant current is:

$$I_{\mathrm{s}\_\mathrm{rms}1}=\sqrt{\frac{(5{\pi }^2-48)}{192{\pi }^2}{(\frac{n{V}_{\mathrm{o}\_\mathrm{rated}}}{L_{\mathrm{m}}{f}_{\mathrm{r}1}})}^2+\frac{{\pi }^2{V}_{\mathrm{o}\_\mathrm{rated}}^2}{16R_{\mathrm{o}}^2}}=4.91\mathrm{A}$$

(75)

In reverse operation, the corresponding resonant current is:

$$\begin{array}{l}{I}_{\mathrm{p}\_\mathrm{rms}2}=0.589\mathrm{A}\\ I_{\mathrm{s}\_\mathrm{rms}2}=11.02\mathrm{A}\end{array}$$

(76)

The voltage stress of the primary power switch is the maximum value of the DC bus voltage, i.e., 420 V, and the current stress is the peak value of the primary resonant current, i.e., 1.871 A. Therefore, the primary switch is SMD7N65, whose drain-source withstand voltage is 650 V and continuous drain current is 7 A, and the secondary switch is SQJ402EP-T1_GE3, whose drain-source withstand voltage is 100 V and the continuous drain current is 32 A.

5. Simulation Analysis

The two-stage bidirectional charging system’s simulation model includes the main circuit and the control circuit. The power circuit includes a grid, bidirectional totem pole converter, and bidirectional CLLLC resonant converter; the control circuit consists of a PI controller (current loop, voltage loop), SPWM modulation, and frequency control module. In the control of the post-stage CLLLC resonant converter, the PWM signal is obtained by comparing the output voltage with the given voltage through the PI regulator and pulse frequency modulation (PFM) to control the power switching transistor. The charging system simulation model is shown in Figure 17.

5.1. Simulation of the Forward Operating State

The bidirectional totem pole converter is cascaded with a bidirectional CLLLC resonant converter to obtain the waveform of the rated output of the charging system at full load. The simulated waveform of the front stage is shown in Figure 18. The figure shows that after 0.045 s, the front stage converter’s input voltage and current phase can be kept consistent. The pre-stage output voltage fluctuates between 395 V and 405 V, and the voltage ripple is about 2.5%.

The voltage and current of the switching transistor Q₁ are shown in Figure 19. Through the detection of the voltage at the terminal of the primary-side switching transistor Q₁ and the current flowing through Q₁, it can be seen that when the voltage at Q₁ drops from V_dc to zero, the current flows positively through the switching transistor Q₁ only from the anti-parallel body diode of Q₁, so the primary-side switching transistor in this state can realize ZVS. The waveforms of the resonant current and the excitation current are shown in Figure 20. When the excitation current is equal to the resonant current, the excitation current increases rapidly in the reverse operation, which shows that the operation is near the quasi-resonant point at this time. Due to the fluctuation of the DC bus voltage, the switching frequency of the resonant converter fluctuates between 95 kHz and 102 kHz.

The currents of diodes D_q5 and D_q7 with the post-stage output voltages are shown in Figure 21 and Figure 22. The detection of the secondary sidelobe diodes D_q5 and D_q7 shows that D_q5 and D_q7 just achieve ZCS, i.e., the secondary sidelobe diodes can achieve ZCS, the output voltage fluctuates between 47.9 V and 48.1 V when stable, and the output voltage ripple is about 0.4%

5.2. Simulation of Reverse Operating State

The voltage and current waveforms of the switching transistor Q₅ are shown in Figure 23. The DC bus voltage fluctuation makes the resonant converter’s switching frequency fluctuate between 110 kHz and 115 kHz. The Q₅ current flows positively to the switching transistor only after the voltage at Q₅ is zero, so the secondary side switching transistor can realize ZVS.

The waveforms of the excitation current and the resonant current are shown in Figure 24, when the excitation current is equal to the resonant current. After the excitation current is equal to the resonant current, it rapidly increases in the reverse operation, and it is known that at this time the work is near the quasi-resonant point, and the voltage gain is about 1. In this process, the primary-side body diodes D_q1 and D_q3 can just achieve ZCS, and the waveform approximates a sinusoidal waveform. The current waveforms of diodes D_q1 and D_q3 are shown in Figure 25.

The output voltage of the rear stage converter and the output voltage of the front stage converter are shown in Figure 26 and Figure 27. The output voltage of the rear stage bidirectional CLLLC resonant converter can be stabilized at 400 V left, and when the front stage converter works in reverse, the output voltage is output in the form of a sinusoidal waveform with a certain harmonic content. Basically, however, it can meet the output requirements.

6. Experimental Verification

The hardware structure of the two-stage bidirectional isolated charging system is shown in Figure 28. The control chip TMS320F28335 is used to process the sampled input current, input voltage, and DC voltage signals to get the control signal. Then the isolated driver chip is used to drive the switch transistor to realize the forward and reverse operation of the system.

The experimental platform of the charging system is designed and built through the above analysis, as shown in Figure 29. It mainly includes a bidirectional isolated charging system, oscilloscope, PC, DC power supply, and electronic load, et al.

6.1. Forward Operation

When the charging system works in the forward operation, and at full load, the input current and voltage waveforms are shown in Figure 30. The peak value of the input current is about 2 A, which is in the same phase as the input voltage. The input current contains fewer harmonics, and the overall power factor of the charging system is high and meets the working requirements. The DC bus voltage and post-stage output voltage waveforms are shown in Figure 31. The amplitude of the DC bus voltage ranges from 392.3 V to 403.7 V, which meets the input voltage requirements of the post-stage.

The waveforms of the gate-source voltage V_{gs_2} and drain-source voltage V_{ds_2} of the primary-side switch transistor Q₂ in the forward operation of the rear stage CLLLC resonant converter are shown in Figure 32. When V_{ds_2} drops to zero potential, V_{gs_2} starts to increase, indicating that all switch transistors on the primary side in the forward operation mode can achieve ZVS, thus reducing the turn-on loss of the switch transistors.

When starting the charging system, set the maximum dead time and the highest frequency so that the starting current is small, and then gradually reduce the operating frequency and dead time to ensure normal operation; taking the resonant current as an example, there is no current shock during the starting process, and you can choose equipment with a smaller value of voltage and current resistance to reduce costs. The soft-start process is shown in Figure 33.

6.2. Reverse Operation

When the charging system works in reverse and is fully loaded, the waveforms of output voltage and output current are shown in Figure 34. The output voltage and output current maintain a sinusoidal output, and the peak output voltage is about 311 V at this time. There is a certain harmonic content; however, it meets the requirements, which allows the power to be supplied to other devices in reverse.

The waveforms of the gate-source voltage V_{gs_5} and drain-source voltage V_{ds_5} of the rear stage CLLLC resonant converter at the secondary side switch transistor Q₅ during reverse operation are shown in Figure 35, and V_{gs_5} starts to increase when V_{ds_5} drops to zero potential, thus realizing ZVS. The current waveforms of the body diodes D_q1 and D_q3 and the resonant current waveforms are shown in Figure 36. It can be seen that the body diodes can achieve zero-current shutdown and that the resonant current approximates a sinusoidal waveform, which is the highest efficiency.

A charging system with a bidirectional CLLC resonant converter in the rear stage was designed in [27] with an overall control strategy of up to 94.5% in efficiency. In this paper, the efficiency of the two-stage isolated charging system was tested and calculated at different loads, and the resulting efficiency graph is shown in Figure 37. From the graph, it can be seen that the maximum efficiency is 95.895% for forward operation and 95.504% for reverse operation. From the overall comparison, it can be seen that the charging system designed in this paper has a high efficiency.

7. Conclusions

In this paper, the theory, simulation, and experiment of two-stage isolated charging system topology based on resonant converter are studied, and the following conclusions are obtained:

• Mathematical modeling of bidirectional totem pole converter using small signal analysis can obtain the transfer function of input current transformation with a duty cycle; an equivalent model of a bidirectional CLLLC resonant converter is obtained by fundamental wave analysis for characterization, and the parameters of the design are reasonable.
• The front stage adopts voltage and current double closed-loop control to keep the DC bus voltage stable, and the rear stage adopts frequency conversion and a high-frequency soft start to control the constant output voltage. The simulation model results of the control system show that the control strategy designed in this paper is reasonable.
• The experimental results prove that the bidirectional charging system can achieve power factor correction and has soft switching characteristics across the full load range.