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Article

A Novel Switched-Capacitor Inverter with Reduced Capacitance and Balanced Neutral-Point Voltage

Wuhan National High Magnetic Field Center, School of Electrical and Electronic Engineering, Huazhong University of Science and Technology, Wuhan 430074, China
*
Author to whom correspondence should be addressed.
Electronics 2021, 10(8), 947; https://doi.org/10.3390/electronics10080947
Submission received: 14 March 2021 / Revised: 12 April 2021 / Accepted: 14 April 2021 / Published: 16 April 2021

Abstract

:
A novel three-phase switched-capacitor multilevel inverter (SCMLI) with reduced capacitance and balanced neutral-point voltage is proposed in this paper. Applying only one DC source, the three-phase seven-level topology possessing voltage-boosting capability is accomplished without the high-voltage stress of power switches. Owing to the inherent redundant switching states of the proposed topology, two charging approaches that can effectively limit the voltage ripples and path selection for capacitors can be realized. This provides the presented topology with reduced capacitance, balanced neutral-point voltage, good performance in not only the three-phase four-wire system but also the three-phase three-wire system, and low total harmonic distortion (THD) of the output voltage. A comprehensive comparison with previous SCMLIs in various aspects is conducted to validate the merits mentioned above. The simulation results accord with theoretical analyses, confirming the feasibility of the proposed three-phase SCMLI.

1. Introduction

Multilevel inverters are important circuit configurations in modern electrical power systems because of their many advantages, such as low total harmonic distortion (THD) of the output voltage, low voltage stress on power devices, and low electromagnetic interference (EMI). The main applications of these inverters include static compensators, high-voltage DC transmission systems, active power filters, and renewable energy systems that include variable-frequency motor drives [1,2,3,4,5,6]. Neutral-point-clamped (NPC) [7], flying-capacitor [8], and cascaded H-bridge [9] are three well-researched multilevel inverters. These inverters are widely used in practical and commercial applications. However, these inverters have shortcomings such as neutral-point voltage imbalance and the need for excessive isolated DC sources [10]. Owing to the inability to boost the input voltage, the sum of the DC source voltages cannot be less than the amplitude of the output voltage. To overcome the drawbacks mentioned above, many new topologies have been introduced that offer more optimized component utilization, more voltage levels, higher efficiency, and so on [11,12].
Since the input voltage is relatively low compared with the output voltage, boost circuits [13,14] are required in many applications, such as grid-connected photovoltaic modules, distributed generation (DG) systems, and electric vehicles. Inductors or transformers are used in most boost circuits, making the systems bulky and heavy [15]. Therefore, a charge pump is typically adopted as a boost circuit [16]. In the charge pump, the output voltage is equal to the sum of the capacitor voltages and the input voltage. The capacitors in the charge pump are discharged when connected in series and charged when connected in parallel along with the DC source.
Inverters using the same working principle are called switched-capacitor multilevel inverters (SCMLI), which have become a recent research topic of interest [17,18]. Unlike inductors or transformers, capacitors are used to boost the input voltage. Employing fewer isolated DC sources and related components, they can generate voltage levels. To boost the input voltage, capacitors need to be involved in the load current path. In most SCMLIs, all relevant capacitors are discharged at the top voltage level. In addition, the discharging state can last for a long time according to the modulation method. This time is called the longest discharging time (LDT). As a result, capacitors have difficulty maintaining their voltage, thus exceeding the maximum allowable value of the voltage ripples. This is a critical challenge for existing SCMLIs.
Several methods have been used to solve this problem, but the most adopted method is to increase the capacitance. By employing only one DC source in a three-phase topology, a boost seven-level switched-capacitor inverter was proposed in [19]. The voltage stress of all power switches did not exceed the input voltage, and the capacitance used was 4700 μF. This method increased the volume and cost of the system [20,21]. Another method involves increasing the frequency of the output voltage. A family of SCMLI topologies for high-frequency AC applications was proposed in [22]. This approach can generate more voltage levels with an optimal component count. The main applications of this method have been limited to high-frequency AC systems [23,24]. A third method involves decreasing the maximum allowable modulation index. A novel seven-level inverter for medium-voltage high-power applications was presented in [25], and the maximum allowable modulation index was 0.813. This method reduces the boosting ability of SCMLIs [26]. A fourth method involves reducing the load. A boost single-phase switched-capacitor inverter was presented in [27]. With fewer power switches, this SCMLI could generate nine voltage levels under a resistive load condition (200 Ω). However, this method limits the power that SCMLIs can supply when the output voltage is the same [28,29].
Another problem for several SCMLIs that adopt a DC-link converter is the neutral-point voltage imbalance [30,31,32,33]. The self-balancing characteristic of these SCMLIs self-regulates the average neutral-point voltage to a certain value (usually half the DC-link voltage). The self-balancing time is long, and the neutral-point voltage may drift excessively. In addition, a three-phase three-wire system can worsen this problem in most traditional three-phase SCMLIs. Additional hardware or software measures are necessary to solve this problem. Regarding software measures, many studies have been carried out based on NPC topology. However, there is little research on this problem in SCMLIs. Hardware measures, such as adding additional components, increase the volume and cost of the system.
Generally, the abovementioned topologies have various disadvantages. To overcome these shortcomings, a novel three-phase SCMLI is presented in this paper. The main advantages of the proposed topology are as follows:
(1)
Less capacitance (200 μF) is used.
(2)
There is no problem of neutral-point voltage imbalance.
(3)
Good performance is achieved in not only a three-phase four-wire system but also a three-phase three-wire system.
(4)
Only one DC source is used as a three-phase topology.
(5)
All floating capacitors are used to generate the top voltage level.
This paper is organized as follows: the topology of the proposed SCMLI and the operating principle are fully outlined in Section 2. Theoretical analyses of the two charging approaches are provided in Section 3. Control strategies are presented in Section 4. The voltage ripples of the capacitors are carefully analyzed in Section 5. The overall system efficiency is calculated in Section 6. Simulation results and a comprehensive comparison are presented in Section 7. Lastly, a conclusion is drawn in Section 8.

2. Proposed SCMLI and Operating Principle

The proposed three-phase SCMLI topology is shown in Figure 1. Employing one DC source and eight capacitors, it can generate seven voltage levels (0 V, 0.5 Vdc, Vdc, 1.5 Vdc, −0.5 Vdc, −Vdc, −1.5 Vdc) under different kinds of load conditions. The capacitors’ rated voltage is UN = 0.5 Vdc. Bidirectional switches are used to block positive and negative voltage stress. The floating capacitors C1,2 are used to generate the top voltage level. They can also balance the voltages of the DC-link capacitors Cdc1,2 when needed. Furthermore, the proposed topology is used in a three-phase four-wire system when O and N are connected and is used in a three-phase three-wire system when O and N are not connected.
All switching states of the proposed three-phase SCMLI are listed in Table 1. Main switching states are depicted in Figure 2a–g. Other switching states are fully discussed in Section 3 and Section 4. To generate 0 V, S2, S3, S11, and S12 need to be ON, as shown in Figure 2a. In Figure 2b,e, the black and red devices represent two different paths. Both C1 and C2 can be used to generate not only 0.5 Vdc but also −0.5 Vdc. Selecting the right path can make uC1 approach uC2. In Figure 2c,f, the capacitors Cdc1, C2 and Cdc2, C1 are used to generate Vdc and −Vdc, respectively. To generate 1.5 Vdc, S1, S7, S9, and S10 need to be ON, as shown in Figure 2d. Similarly, to generate −1.5 Vdc, S6, S7, S8, and S13 need to be ON, as shown in Figure 2g. For multilevel inverters, there are several modulation strategies. In this paper, the phase opposition disposition PWM is adopted, which is shown in Figure 2h.

3. Capacitor Charging Approaches

Two significant approaches are used in this paper to charge capacitors. Approach I that is first proposed in this paper plays an important role in balancing capacitors voltages and makes it possible for the proposed topology to solve the problem of neutral-point voltage imbalance. Approach II is a widely adopted approach that can charge the capacitors together. The equivalent circuits of approach I and approach II are shown in Figure 3a,b, respectively. Rdc1, Rdc2, R1, and R2 are the equivalent resistances of the devices.

3.1. Approach I

All of the DC-link capacitors Cdc1,2 and one of the floating capacitors C1,2 were used to realize approach I in this paper. The circuit mode with C1, Cdc1 and Cdc2 in Figure 3a is taken as an example to illustrate approach I. The approximation that Cdc1 = Cdc2 = C1 = C0 and Rdc1 = Rdc2 = R1 = R0 is introduced to simplify the analysis. The following analysis is based on this approximation. According to the topology, the equivalent capacitance Ceq and the equivalent resistance Req can be expressed as follows:
C eq = ( C dc 1 + C 1 ) C dc 2 C dc 1 + C 1 + C dc 2 = 2 3 C 0 R eq = R dc 1 R 1 R dc 1 + R 1 + R dc 2 = 3 2 R 0 .
Therefore, the current that flows through the DC source is given by
i s = V dc u eq ( 0 ) R eq e t R eq C eq ,
where
u eq ( 0 ) = u Cdc 1 ( 0 ) + u C 1 ( 0 ) 2 + u Cdc 2 ( 0 ) .
The voltage of capacitor Cdc2 can be expressed as
u Cdc 2 = u Cdc 2 ( 0 ) + 1 C dc 2 0 t i s d t = 2 3 [ V dc u eq ( 0 ) ] ( 1 e t R 0 C 0 ) + u Cdc 2 ( 0 ) .
The voltage of capacitor Cdc1 satisfies the following differential equation:
u Cdc 1 + R dc 1 C dc 1 d u Cdc 1 d t = V dc u Cdc 2 i s R dc 2 = V dc + u Cdc 1 ( 0 ) u Cdc 2 ( 0 ) + u C 1 ( 0 ) 3 .
According to Equation (5), Cdc1 initial voltage is uCdc1(0) and final voltage is (Vdc + uCdc1(0) − uCdc2(0) + uC1(0))/3. According to the full response theory of the first order circuit, uCdc1 can be expressed as
u Cdc 1 = u Cdc 1 ( 0 ) e t R 0 C 0 + V dc + u Cdc 1 ( 0 ) u Cdc 2 ( 0 ) + u C 1 ( 0 ) 3 ( 1 e t R 0 C 0 ) .
Similarly, uC1 can be expressed as
u C 1 = u C 1 ( 0 ) e t R 0 C 0 + V dc + u Cdc 1 ( 0 ) u Cdc 2 ( 0 ) + u C 1 ( 0 ) 3 ( 1 e t R 0 C 0 ) .
When uCdc1(0) > 0.5 Vdc > uCdc2(0) and uC1(0) < 0.5 Vdc, capacitors C1 and Cdc2 will be charged, and capacitor Cdc1 will be discharged according to Equations (4), (6) and (7). When uCdc1(0) < 0.5 Vdc < uCdc2(0) and uC1(0) > 0.5 Vdc, capacitors C1 and Cdc2 will be discharged, and capacitor Cdc1 will be charged similarly. If approach I is adopted, all relevant capacitor voltages will move toward 0.5 Vdc. Furthermore, these voltages will reach 0.5 Vdc if uCdc1(0) − uCdc2(0) + uC1(0) = 0.5 Vdc. As shown in Figure 4a, S1, S8, S2, and S3 are ON. C1 and Cdc1 are connected in parallel, and approach I is realized. To generate 0 V at the same time, S11 and S12 should be ON. Moreover, 0.5 Vdc and −0.5 Vdc can be generated when S10 and S13 are ON, respectively. As shown in Figure 4b, S2, S3, S6, and S9 are ON. C2 and Cdc2 are connected in parallel, and approach I is realized. Similarly, 0 V, 0.5 Vdc, and −0.5 Vdc can be generated at the same time.

3.2. Approach II

Approach II, which is used to balance the floating capacitor voltages, is shown in Figure 3b. Similarly, it is assumed that C1 = C2 = C0 and R1 = R2 = R0. According to the topology, Req = 2R0 and Ceq = 0.5C0. Therefore, is is given by
i s = V dc u eq ( 0 ) R eq e t R eq C eq ,
where ueq(0) = uC1(0) + uC2(0). uC1 can be calculated as follows:
u C 1 = u C 1 ( 0 ) + 1 C 1 0 t i s d t = 1 2 [ V dc u eq ( 0 ) ] ( 1 e t R 0 C 0 ) + u C 1 ( 0 ) .
Similarly, uC2 can be expressed as follows:
u C 2 = 1 2 [ V dc u eq ( 0 ) ] ( 1 e t R 0 C 0 ) + u C 2 ( 0 ) .
After applying approach II, the average uC1 and uC2 reach 0.5 Vdc, according to Equations (9) and (10). Moreover, uC1 and uC2 will reach 0.5 Vdc if uC1(0) = uC2(0). Approach II can be realized when S1, S8, S6, and S9 are ON, as shown in Figure 4c. Any one of 0 V, 0.5 Vdc, and −0.5 Vdc can be generated at the same time. These two charging approaches can be realized, which is an important feature of the proposed three-phase SCMLI.

4. Control Strategies to Limit Voltage Ripples

To limit voltage ripples, the control strategies of the capacitor voltages are listed in Table 2. For capacitors C1 and C2, the control strategies can be divided into two aspects. The first aspect involves using approach II and making the average of uC1 and uC2 return to 0.5 Vdc. Approach II is taken when |0.5(uC1 + uC2) − 0.5 Vdc| > uγ. uγ is an adjustable parameter. The second aspect involves selecting the right path and making uC1 approach uC2. The path selection for C1,2 is used if |0.5(uC1 + uC2) − 0.5 Vdc| < uγ.
Similarly, for capacitors Cdc1 and Cdc2, the control strategies can be divided into two aspects. The first aspect involves using approach I and making uCdc1 and uCdc2 move toward 0.5 Vdc. Approach I is taken when |uCdc1uCdc2| > uα. uα is also an adjustable parameter. The second aspect involves selecting the right path and making uCdc1 approach uCdc2. As uCdc1 + uCdc2 = Vdc, uCdc1 and uCdc2 return to 0.5 Vdc when uCdc1 reaches uCdc2. The path selection for Cdc1,2 is used if |uCdc1uCdc2| < uα.
There are more paths for selection in the proposed topology, and the redundant switching states are depicted in Figure 5a–e. With respect to Figure 5a, the black and red devices represent two different paths. S1, S8, S11, and S12 are ON, and the capacitors Cdc1 and C1 are used to generate 0 V. Similarly, S6, S9, S11, and S12 are ON, and capacitors Cdc2 and C2 are used to generate 0 V. Moreover, 0.5 Vdc is generated when S1, S8, and S10 are ON, as shown in Figure 5b, whereas −0.5 Vdc is generated when S6, S9, and S13 are ON, as shown in Figure 5d. In Figure 5c,e, capacitors C1 and C2 can be used to generate not only Vdc but also level −Vdc. For capacitors in the proposed topology, path selection is an important control strategy. As shown in Figure 2 and Figure 5, there are various paths for selection at several voltage levels, and the capacitors used are different, making it easier to balance the capacitor voltages. This is one of the main advantages of the proposed topology.
Usually, there is a conflict between the control strategies of uC1,2 and the control strategies of uCdc1,2. It is important to make a comprehensive decision according to the latest status. In this paper, the top priority is to decide whether to take approach II. |0.5(uC1 + uC2) − 0.5 Vdc| > uγ, and this is the criterion that uC1 and uC2 have to meet if approach II is to be taken. After that, approach I is taken when |uCdc1uCdc2| > uα. This will make uCdc1 and uCdc2 move toward 0.5 Vdc. Then, the path selection for Cdc1,2 is used if |uCdc1uCdc2| > uβ. uα is larger than uβ. Lastly, the path selection for C1,2 is used.
The reasons for there being no problem of neutral-point voltage imbalance for the proposed three-phase SCMLI can be divided into two aspects. On the one hand, approach I is adopted in this paper. This approach is an effective measure to balance the capacitor voltages. On the other hand, there are various paths for selection at several voltage levels. These two aspects complement each other, giving the proposed topology the ability to solve the problem of neutral-point voltage imbalance.

5. Capacitance Determination

Approach II can be used at 0 V, 0.5 Vdc, and −0.5 Vdc. Thus, capacitors C1 and C2 are discharged when uref > Vdc and ibus > 0 in the positive half cycle. To address this problem, an important change to the original modulation method is made in this paper, and the new modulation wave in the positive half cycle is shown in Figure 6.
According to the original modulation method, there are two choices in a switching period when uref > Vdc. These choices are ubus = Vdc and ubus = 1.5 Vdc. In this paper, this condition is expressed as ubus ϵ {Vdc, 1.5 Vdc}. ubus ϵ {0.5 Vdc, 1.5 Vdc} is added when t1tt4 because the abovementioned control strategies can be realized at 0.5 Vdc. Specifically, ubus ϵ {0.5 Vdc, 1.5 Vdc} is used in half of the switching periods when t1tt2 or t3tt4. ubus ϵ {0.5 Vdc, 1.5 Vdc} is used in all the switching periods when t2tt3.
The longest discharging time of floating capacitors is an important SCMLI parameter because the required capacitance can be calculated according to it. The longest discharging time tldt of floating capacitors in the proposed three-phase SCMLI can be expressed as
t ldt = 2 T s t c ,
where Ts is the switching period, and tc is the minimum duration of 0.5 Vdc when t1tt2 or t3tt4. According to Equation (11), the longest discharging time of floating capacitors in the proposed topology is smaller than 2Ts, which is much shorter than that in other traditional SCMLIs. During the longest discharging time, the current that flows through floating capacitors is ibus. The voltage variation of floating capacitors that comes from ibus can be calculated as follows:
t start t end i bus d t C 1 , 2 2 T s t c C 1 , 2 i bus | t = t start < 2 T s C 1 , 2 m A boost V dc | Z MN | ,
where m is the modulation index, and Aboost is the voltage gain. tstart and tend are the start time and end time of the longest discharging time, respectively. ZMN is the total impedance between point M and point N. Considering that approach I is adopted, Equation (12) needs to satisfy
2 T s C 1 , 2 m A boost V dc | Z MN | < 0.5 u α .
According to Equation (13), the required capacitance of floating capacitors can be calculated as follows:
C 1 , 2 > 4 T s u α m A boost V dc | Z MN | .
According to Equations (11)–(14), reducing the longest discharging time of the floating capacitors can effectively reduce the capacitance of the floating capacitors.
Approach I, which can make uCdc1 and uCdc2 move toward 0.5 Vdc, is taken if |uCdc1uCdc2| > uα. Thus, uCdc1 and uCdc2 can be limited to 0.5 Vdc ± 0.5 uα with less DC-link capacitance. Similarly, the voltage variation of the DC-link capacitors between tbegin (the end time of the first approach I) and tfinish (the start time of the second approach I) can be calculated as follows:
t begin t finish i Cdc 1 d t C dc 1 , 2 k T s C dc 1 , 2 i Cdc 1 | t = t begin < k T s 2 C dc 1 , 2 m A boost V dc | Z MN | ,
where kTs = tfinishtbegin. To coincide with approach I, Equation (15) needs to satisfy
k T s 2 C dc 1 , 2 m A boost V dc | Z MN | < 0.5 u α .
According to Equation (16), the required capacitance of the DC-link capacitors can be calculated as follows:
C d c 1 , 2 > k T s u α m A boost V dc | Z MN | .
According to Equations (14) and (17), the required capacitance of the floating capacitors is similar to that of the DC-link capacitors. Therefore, C1,2 = Cdc12 in this paper.

6. Efficiency Calculation

In this section, the overall efficiency of the proposed three-phase SCMLI is calculated. First, the conduction loss of the power switches Pcon1 can be expressed as
P con 1 = f o i = 1 N swi 0 T o ( i si 2 r si + i si V si ) d t ,
where isi, rsi, and Vsi are the current, internal resistance, and voltage drop of the i-th switch, respectively. Nswi is the number of power switches. To and fo are the period and frequency of the output voltage, respectively. The conduction loss Pcon2 that comes from the DC-link capacitors and the floating capacitors can be calculated as follows:
P con 2 = f o i = 1 N ca 0 T o i Ci 2 r Ci d t ,
where iCi and rCi are the current and the internal resistance of the i-th capacitor, respectively. Nca is the number of capacitors. The conduction loss of the output filters Pcon3 can be calculated as follows:
P con 3 = f o i = 1 N fil 0 T o ( i Lfi 2 r Lfi + i Cfi 2 r Cfi ) d t ,
where iLfi and rLfi are the current and the internal resistance of the i-th filter inductor, respectively. iCfi and rCfi are the current and the internal resistance of the i-th filter capacitor, respectively. Nfil is the number of filters.
To simplify the analysis, the voltage and the current of the power switches are considered to have a linear relation with time during the switching process. Therefore, the switching loss Poff(i,j) that is caused by the j-th turning OFF process of the i-th switch is given by
P off ( i , j ) = f o 0 t off v ( t ) i ( t ) d t = f o 0 t off V off ( i , j ) t off t [ I off ( i , j ) t off ( t t off ) ] d t = 1 6 V off ( i , j ) I off ( i , j ) t off f o ,
where Voff(i,j) and Ioff(i,j) are the voltage after the turning OFF process and the current before the turning OFF process, respectively. Similarly, switching loss Pon(i,j) that is caused by the j-th turning ON process of the i-th switch is given by
P on ( i , j ) = 1 6 V on ( i , j ) I on ( i , j ) t on f o ,
where Von(i,j) and Ion(i,j) are the voltage before the turning ON process and the current after the turning ON process, respectively. According to Equations (21) and (22), the total switching loss Psw can be calculated by
P sw = i = 1 N swi ( j = 1 N on ( i ) P on ( i , j ) + j = 1 N off ( i ) P off ( i , j ) ) = 1 6 f o i = 1 N swi ( t on j = 1 N on ( i ) V on ( i , j ) I on ( i , j ) + t off j = 1 N off ( i ) V off ( i , j ) I off ( i , j ) ) ,
where Non(i) and Noff(i) are the number of i-th switch turning ON processes and turning OFF processes, respectively.
According to Equations (18)–(20), and (23), the overall efficiency of the proposed topology is given by
η = P o P o + P con 1 + P con 2 + P con 3 + P sw .

7. Simulation Results and Comparison

7.1. Simulation Results

MATLAB/Simulink was chosen as the simulation software. The parameters of the proposed three-phase SCMLI are listed in Table 3. The input voltage was set as 200 V, which resembles many other SCMLIs. Thus, the rated voltage of the capacitors was 100 V. The modulation ratio was 0.95, and the output voltage was 285 (300 × 0.95) V. The capacitance used was 200 μF, which meets the requirement of Equation (15). The output power was 1884 W, and the resistive–inductive load Z1 was 40 Ω, 100 mH. uα was 8 V since the maximum allowable voltage ripple of capacitors was 10 V (10% of the rated voltage). The filter capacitor was 80 μF, and the filter inductor was 4 mH. The switching frequency was 20 kHz. This frequency can reduce the requirement of capacitance according to Equation (15). The output frequency was 50 Hz.

7.1.1. Performance in Three-Phase Four-Wire System

To assess the performance of the proposed three-phase SCMLI in the three-phase four-wire system, Zo = Z1 is given. Figure 7a shows the observed A-phase bus voltage. The top voltage level was 300 V, and the proposed three-phase SCMLI could boost the input voltage. Because uα was equal to 8 V, the voltages of the DC-link capacitors in the A-phase were limited to 96–104 V, as shown in Figure 7b. Approach I could move the voltage of DC-link capacitors toward 100 V when they were larger than 104 V or smaller than 96 V. Figure 7c shows the floating capacitor voltages in the A-phase, which were approximately 96–103 V. It can be seen in this figure that the longest discharging time of floating capacitors was shorter than 2Ts. These waveforms meet the voltage ripple requirement, which should be less than 10% of the rated voltage.
The output voltage of each phase under the resistive–inductive load condition is shown in Figure 8a, and the fast Fourier transform (FFT) result of the A-phase output voltage is shown in Figure 8b. According to the result, THD = 1.87%, and the amplitude of the fundamental component was 285.1 V. This amplitude agrees with the modulation ratio because the desired amplitude of the output voltage was 285 V. Similarly, the output current of each phase under the resistive–inductive load condition is shown in Figure 9a, and the FFT result of the A-phase output current is shown in Figure 9b. THD = 0.83%, and the amplitude of the fundamental component was 5.605 A. The quality of all the waveforms was high, which is attributable to the low-voltage ripples of the capacitors.
To further test the performance of the proposed three-phase SCMLI, a resistive–inductive load transient is given. The time when the load changed from Zo = 2Z1 to Zo = Z1 was 0.12 s. The bus voltage of the A-phase is shown in Figure 10a. The difference between the waveform before 0.12 s and the waveform after 0.12 s was not notable. Figure 10b shows the A-phase DC-link capacitor voltages. The voltage ripple of these capacitors was 8 V during the entire process (uα = 8 V). Figure 10c shows the A-phase floating capacitor voltages. The transient process only lasted for a short period of time (approximately 0.01 s). After that, the floating capacitor voltages quickly returned to the steady state. These waveforms also meet the voltage ripple requirements and are in good agreement with the abovementioned theoretical analysis.
The output voltage of each phase during a resistive–inductive load transient is shown in Figure 11a, and the FFT result of the A-phase output voltage is shown in Figure 11b. THD = 1.96%, and the start time was 0.12 s. There was no significant change in the output voltage of each phase after 0.12 s. The output current of each phase under the same resistive–inductive load transient is shown in Figure 12. Similarly, the transient process only lasted for a short period of time. The output current of each phase quickly changed from the initial steady state to a new steady state. Thus, there is no need to worry about the overvoltage problem or the overcurrent problem.
To test the presented three-phase SCMLI more rigorously, a special load with a temporary three-phase unbalanced disturbance is given. For each phase, Zo = 2Z1. A disturbance load Rd = 100 Ω was only added to the A-phase when 0.8 s < t < 0.85 s. Under this condition, Figure 13a shows the A-phase bus voltage, and there was no obvious change in the waveform when 0.8 s < t < 0.85 s or t > 0.85 s. Figure 13b shows the A-phase DC-link capacitor voltages. Similarly, the transient process only lasted for a short period of time (approximately 0.01 s). During this transient process, uCdc2 was momentarily larger than 104 V, and uCdc1 was momentarily smaller than 96 V. After that, the DC-link capacitor voltages were limited to 96–104 V, as before. Figure 13c shows the A-phase floating capacitor voltages. During the same transient process, uC2 was momentarily larger than 105 V. After that, the floating capacitor voltages quickly returned to the steady state.
When the disturbance load was added to the A-phase, the output voltage of each phase was as shown in Figure 14a, and the FFT result of the A-phase output voltage was as shown in Figure 14b. THD = 3.28%, and the start time was 0.08 s. The change in the output voltage of each phase during the transient process was small.
When the disturbance load was added to the A-phase, the output current of each phase was as shown in Figure 15. The amplitude of the A-phase output current ioA increased because of the disturbance load when 0.8 s < t < 0.85 s. After that (t > 0.85 s), the A-phase output current ioA quickly returned to the steady state. As for ioB and ioC, the disturbance load had no effect because it was only added to the A-phase.
All these observed waveforms in the three-phase four-wire system are in good agreement with the theoretical analyses, confirming the feasibility of the proposed three-phase SCMLI in the three-phase four-wire system.
The recorded efficiency of different topologies is shown in Figure 16. The efficiency decreased with increasing output power. Compared with [27,30], the proposed topology has greater efficiency. The efficiency of the proposed topology is similar to that of [31]. As shown in Figure 17, the share of total conduction loss was larger than that of switching loss. This is because the switching frequency was at a normal level. Furthermore, the share of switching loss increased with decreasing output power. Therefore, decreasing the switching frequency can be adopted to improve the efficiency of the proposed topology when the output power is lower than 800 W.

7.1.2. Performance in Three-Phase Three-Wire System

To test the performance of the proposed three-phase SCMLI in a three-phase three-wire system, the same resistive–inductive load transient is given. The A-phase bus voltage is shown in Figure 18a. Because uNO was not always equal to 0, the bus voltage had more voltage levels. The resistive–inductive load transient had no effect on the bus voltage. Figure 18b shows the DC-link capacitor voltages of the A-phase. The voltage ripple of these capacitors was 10 V. Figure 18c shows the floating capacitor voltages of the A-phase. They changed from 98–101 V to 96–104 V. All these waveforms met the voltage ripple requirements during the entire process.
The output voltage of each phase during a resistive–inductive load transient is shown in Figure 19a, and the FFT result of the A-phase output voltage is shown in Figure 19b. THD = 0.90%, and the start time was 0.12 s. Even in the first period after 0.12 s, the waveform quality of each phase output voltage satisfied the requirement. The output current of each phase under the same resistive–inductive load transient is shown in Figure 20. The transient process only lasted for a short period of time. The output current of each phase quickly changed from the initial steady state to a new steady state.
The problem of neutral-point voltage imbalance became more serious for traditional SCMLIs in the three-phase three-wire system. In contrast, these observed waveforms were in line with expectations, confirming that the proposed three-phase SCMLI achieves good performance in a three-phase three-wire system and there is no problem of neutral-point voltage imbalance.

7.2. Comparison

To better illustrate the advantages of the proposed topology, a comprehensive comparison with other up-to-date SCMLIs in various aspects is shown in Table 4. The main advantages of the proposed topology are as follows:
(1)
Less capacitance (200 μF) is used.
In most SCMLIs, the required capacitance is usually greater than 2000 μF, thus increasing the volume and cost of the system. The capacitance used in [27,32] was 1000 μF, but the load impedance (>150 Ω) was much larger than that of other SCMLIs. The required capacitance increases with decreasing load impedance. The cost of capacitors increases with higher rated voltage, making the advantage of reduced capacitance in the proposed topology more obvious.
(2)
There is no problem of neutral-point voltage imbalance.
The DC-link converter brings the problem of neutral-point voltage imbalance to [19,27,30,31,32,33]. The self-balancing characteristic of these SCMLIs self-regulates the average neutral point voltage to a certain value (usually half the DC-link voltage). However, the self-balancing time is long, and the neutral-point voltage may drift excessively. Additional hardware or software measures need to be taken to solve this problem. Regarding software measures, there is little research about this problem in SCMLIs. Hardware measures, such as adding additional components to the system, increase the volume and cost of the system.
(3)
Good performance is achieved in not only the three-phase four-wire system but also the three-phase three-wire system.
Most traditional three-phase SCMLIs [19,32,33] suffer from the problem of neutral-point voltage imbalance, which becomes more serious in the three-phase three-wire system. Owing to the advantage above, the proposed topology can be adopted in more applications.
(4)
Only one DC source is used as a three-phase topology.
The methods used in [20,26,27,30,31] all represent single-phase topologies. In the three-phase applications, three DC sources are required for such topologies. This advantage of the proposed topology reduces the complexity and cost of the system.
(5)
All floating capacitors are used to generate the top voltage level.
Not all floating capacitors were used to generate the top voltage level in [26,30]. The voltages of these floating capacitors are underused. This advantage of the proposed topology reduces the demand for capacitors.
Furthermore, the proposed topology is simple. Thirteen power switches are used in each phase, and the sum of their voltage stresses is only 11 Vdc, which reaches the average level of other SCMLIs. Two DC-link capacitors and two floating capacitors in each phase are used, and the sum of their rated voltages is 4 Vdc, which is not larger than that of the other three-phase SCMLIs. The proposed topology can generate seven voltage levels under different kinds of load conditions.

8. Conclusions

A novel three-phase SCMLI with reduced capacitance and balanced neutral-point voltage was proposed in this paper. Good performance was achieved in not only the three-phase four-wire system but also the three-phase three-wire system. Only one DC source was used in the three-phase topology. A comprehensive comparison with other recently presented SCMLIs in various aspects was made, and simulation results under different kinds of load conditions were given. All observed waveforms were in good agreement with the theoretical analyses, confirming the feasibility of the proposed three-phase SCMLI.

Author Contributions

Conceptualization, Z.X.; methodology, Z.X.; software, Z.X.; validation, Z.X. and Z.H.; formal analysis, Z.X.; investigation, Z.X.; resources, Z.X.; data curation, Z.X.; writing—original draft preparation, Z.X. and Z.H.; writing—review and editing, Z.X. and Z.H.; visualization, Z.X.; supervision, H.D.; project administration, H.D.; funding acquisition, H.D. All authors have read and agreed to the published version of the manuscript.

Funding

This research was funded by the National Key Research and Development Program of China, Grant number 2016YFA0401702. This research was also funded by the National Natural Science Foundation of China, Grant number 51821005.

Conflicts of Interest

The authors declare no conflict of interest.

Nomenclature

uNRated voltage of capacitors.
VdcInput DC voltage.
fs and TsSwitching frequency and switching period.
AcAmplitude of the carrier waveform.
urefReference voltage.
ubusBus voltage.
Rdc1, Rdc2, R1 and R2Equivalent resistance of the devices.
R0 and C0It is assumed that Rdc1 = Rdc2 = R1 = R2 = R0 and Cdc1 = Cdc2 = C1 = C2 = C0.
Req and CeqEquivalent resistance and equivalent capacitance of the charging topology.
isCurrent that flows through the DC source in the charging topology.
uCd1, uCd2, uC1, uC2Voltage of capacitors.
iCd1, iCd2, iC1, iC2Current of capacitors.
uCdc1(0), uCdc2(0), uC1(0), uC2(0)Initial voltage of capacitors.
ueq(0)Initial voltage of the equivalent capacitor.
uα, uβ, uγAdjustable parameters that represent the requirements of selecting the appropriate control strategy.
ibusBus current that flows through the filter inductor.
tldtThe longest discharging time of floating capacitors.
tc Minimum duration of 0.5 Vdc voltage level.
mModulation index.
AboostVoltage gain.
tstart and tend Start time and end time of the longest discharging time.
ZMNTotal impedance between point M and point N (can be calculated by the filter parameter and the load condition).
tbegin and tfinishEnd time of the first approach I and Start time of the next approach I.
kA parameter that satisfies the equation kTs = tfinishtbegin.
Pcon1Conduction loss of the power switches.
isi, rsi, and VsiCurrent, internal resistance and voltage drop of the ith switch.
NswiNumber of power switches.
fo and To Frequency and period of the output voltage.
Pcon2Conduction loss that comes from DC-link and floating capacitors.
iCi and rCiCurrent and internal resistance of the ith capacitor.
NcapNumber of capacitors.
Pcon3Conduction loss of the output filters.
iLfi and rLfiCurrent and internal resistance of the i-th filter inductor.
iCfi and rCfiCurrent and internal resistance of the i-th filter capacitor.
NfilNumber of filters.
Poff(i,j)Switching loss caused by the j-th turning OFF process of the i-th switch.
Voff(i,j) and Ioff(i,j)Voltage after the j-th turning OFF process of the i-th switch and current before the j-th turning OFF process of the i-th switch
Pon(i,j)Switching loss caused by the j-th turning ON process of the i-th switch.
Von(i,j) and Ion(i,j)Voltage before the j-th turning ON process of the i-th switch and current after the j-th turning ON process of the i-th switch.
PswTotal switching loss.
Non(i) and Noff(i)Number of i-th switch turning ON processes and turning OFF processes.
ηOverall efficiency of the proposed topology.
PoOutput power.
ZoLoad impedance.
Z1Load condition that is adopted in this paper.
RdA disturbance load that is only added to the A-phase temporarily.

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Figure 1. Proposed seven-level three-phase SCMLI topology.
Figure 1. Proposed seven-level three-phase SCMLI topology.
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Figure 2. Main switching states of the proposed three-phase SCMLI at (a) 0 V, (b) 0.5 Vdc, (c) Vdc, (d) 1.5 Vdc, (e) −0.5 Vdc, (f) −Vdc, and (g) −1.5 Vdc. (h) The waveform of the phase opposition disposition PWM in the positive quarter cycle (switching frequency fs = 5 kHz).
Figure 2. Main switching states of the proposed three-phase SCMLI at (a) 0 V, (b) 0.5 Vdc, (c) Vdc, (d) 1.5 Vdc, (e) −0.5 Vdc, (f) −Vdc, and (g) −1.5 Vdc. (h) The waveform of the phase opposition disposition PWM in the positive quarter cycle (switching frequency fs = 5 kHz).
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Figure 3. Equivalent circuit of (a) approach I and (b) approach II.
Figure 3. Equivalent circuit of (a) approach I and (b) approach II.
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Figure 4. Switching states when (a) approach I is realized and C1 is used, (b) approach I is realized and C2 is used, and (c) approach II is realized.
Figure 4. Switching states when (a) approach I is realized and C1 is used, (b) approach I is realized and C2 is used, and (c) approach II is realized.
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Figure 5. Redundant switching states of the proposed three-phase SCMLI structure at (a) 0 V, (b) 0.5 Vdc, (c) Vdc, (d) −0.5 Vdc, and (e) −Vdc.
Figure 5. Redundant switching states of the proposed three-phase SCMLI structure at (a) 0 V, (b) 0.5 Vdc, (c) Vdc, (d) −0.5 Vdc, and (e) −Vdc.
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Figure 6. The new modulation wave in the positive half cycle (switching frequency fs = 5 kHz).
Figure 6. The new modulation wave in the positive half cycle (switching frequency fs = 5 kHz).
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Figure 7. (a) The bus voltage, (b) DC-link capacitor voltages and (c) floating capacitor voltages of the A-phase under the resistive–inductive load condition.
Figure 7. (a) The bus voltage, (b) DC-link capacitor voltages and (c) floating capacitor voltages of the A-phase under the resistive–inductive load condition.
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Figure 8. (a) The output voltage of each phase under the resistive–inductive load condition. (b) The FFT result of the A-phase output voltage.
Figure 8. (a) The output voltage of each phase under the resistive–inductive load condition. (b) The FFT result of the A-phase output voltage.
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Figure 9. (a) The output current of each phase under the resistive–inductive load condition. (b) The FFT result of the A-phase output current.
Figure 9. (a) The output current of each phase under the resistive–inductive load condition. (b) The FFT result of the A-phase output current.
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Figure 10. (a) The bus voltage, (b) DC-link capacitor voltages and (c) floating capacitor voltages of the A-phase during a resistive–inductive load transient.
Figure 10. (a) The bus voltage, (b) DC-link capacitor voltages and (c) floating capacitor voltages of the A-phase during a resistive–inductive load transient.
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Figure 11. (a) The output voltage of each phase during a resistive–inductive load transient. (b) The FFT result of the A-phase output voltage.
Figure 11. (a) The output voltage of each phase during a resistive–inductive load transient. (b) The FFT result of the A-phase output voltage.
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Figure 12. The output current of each phase during a resistive–inductive load transient.
Figure 12. The output current of each phase during a resistive–inductive load transient.
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Figure 13. (a) The bus voltage, (b) DC-link capacitor voltages and (c) floating capacitor voltages of the A-phase when the disturbance load was added to the A-phase.
Figure 13. (a) The bus voltage, (b) DC-link capacitor voltages and (c) floating capacitor voltages of the A-phase when the disturbance load was added to the A-phase.
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Figure 14. (a) The output voltage of each phase when the disturbance load was added to the A-phase. (b) The FFT result of the A-phase output voltage.
Figure 14. (a) The output voltage of each phase when the disturbance load was added to the A-phase. (b) The FFT result of the A-phase output voltage.
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Figure 15. The output current of each phase when the disturbance load was added to the A-phase.
Figure 15. The output current of each phase when the disturbance load was added to the A-phase.
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Figure 16. Recorded efficiency of different topologies.
Figure 16. Recorded efficiency of different topologies.
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Figure 17. The share of switching loss and total conduction loss.
Figure 17. The share of switching loss and total conduction loss.
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Figure 18. (a) The bus voltage, (b) DC-link capacitor voltages and (c) floating capacitor voltages of the A-phase during a resistive–inductive load transient.
Figure 18. (a) The bus voltage, (b) DC-link capacitor voltages and (c) floating capacitor voltages of the A-phase during a resistive–inductive load transient.
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Figure 19. (a) The output voltage of each phase during a resistive–inductive load transient. (b) The FFT result of the A-phase output voltage.
Figure 19. (a) The output voltage of each phase during a resistive–inductive load transient. (b) The FFT result of the A-phase output voltage.
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Figure 20. The output current of each phase during a resistive–inductive load transient.
Figure 20. The output current of each phase during a resistive–inductive load transient.
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Table 1. All switching states of the proposed three-phase SCMLI.
Table 1. All switching states of the proposed three-phase SCMLI.
STATESVoltageFigure PositionSwitches
LevelS1S2S3S4S5S6S7S8S9S10S11S12S13
11.5 VdcFigure 21000001011000
2VdcFigure 21000001010110
3VdcFigure 50001100011000
40.5 VdcFigure 41000010111000
50.5 VdcFigure 40110010011000
60.5 VdcFigure 41110000101000
70.5 VdcFigure 51000000101000
80.5 VdcFigure 20110000001000
90.5 VdcFigure 20001100010110
100 VFigure 41000010110110
110 VFigure 40110010010110
120 VFigure 41110000100110
130 VFigure 51000000100110
140 VFigure 50000010010110
150 VFigure 20110000000110
16−0.5 VdcFigure 41000010110001
17−0.5 VdcFigure 40110010010001
18−0.5 VdcFigure 41110000100001
19−0.5 VdcFigure 50000010010001
20−0.5 VdcFigure 20110000000001
21−0.5 VdcFigure 20001101100110
22−VdcFigure 20000011100110
23−VdcFigure 50001101100001
24−1.5 VdcFigure 20000011100001
Table 2. Control strategies of the capacitor voltages.
Table 2. Control strategies of the capacitor voltages.
CapacitorsControl Strategy
C1 and C2Approach II, path selection
Cdc1 and Cdc2Approach I, path selection
Table 3. Parameters of the proposed three-phase SCMLI.
Table 3. Parameters of the proposed three-phase SCMLI.
ParametersValue
Vdc200 V
Capacitor rated voltage100 V
Modulation ratio0.95
Output voltage285 V
C1, C2, Cdc1, and Cdc2200 μF
Output power1884 W
Resistive–inductive load Z140 Ω, 100 mH
uα8 V
Filter capacitor80 μF
Filter inductor4 mH
Switching frequency20 kHz
Output frequency50 Hz
Table 4. Comparison of different topology results.
Table 4. Comparison of different topology results.
[19][20][26][27][30][31][32][33]Proposed Topology
CDC-link4700
4700
-----1000
1000
4700
4700
200
200
Cfloating4700
4700
6800
6800
3300
4330
4320
2190
1000
1000
2200
2200
2200
2200
/2200
10004700200
200
Nca_3p899696558
TRVca_3p41515363444
εca100%100%80%100%50%100%100%100%100%
NDC_3p133333111
Load condition40 Ω
100 mH
50 Ω
30 mH
42.2 Ω
79 mH
200 Ω30 Ω
30 mH
10 Ω
100 mH
160 Ω40 Ω
100 mH
40 Ω
100 mH
m1.00.90.911.01.01.01.01.00.95
Suffering from imbalance yesnonoyesyesyesyesyesno
Aboost1.5642221.51.51.5
Nlevel7139999777
Nsd1015121111109913
TSVsw933241210118811
CDC-link is the DC-link capacitance (μF). Cfloating is the floating capacitance (μF). Nca_3p is the number of capacitors in the three-phase applications. TRVca_3p is the total rated voltage of capacitors (Vdc) in the three-phase applications. εca is the share of the floating capacitors voltages that are used to generate the top voltage level. NDC_3p is the number of DC sources in the three-phase applications. Nlevel is the number of voltage levels. Nsd is the number of power switches and diodes in each phase. TSVsw is the total standing voltage of switches (Vdc) in each phase.
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Xun, Z.; Ding, H.; He, Z. A Novel Switched-Capacitor Inverter with Reduced Capacitance and Balanced Neutral-Point Voltage. Electronics 2021, 10, 947. https://doi.org/10.3390/electronics10080947

AMA Style

Xun Z, Ding H, He Z. A Novel Switched-Capacitor Inverter with Reduced Capacitance and Balanced Neutral-Point Voltage. Electronics. 2021; 10(8):947. https://doi.org/10.3390/electronics10080947

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Xun, Zhuyu, Hongfa Ding, and Zhou He. 2021. "A Novel Switched-Capacitor Inverter with Reduced Capacitance and Balanced Neutral-Point Voltage" Electronics 10, no. 8: 947. https://doi.org/10.3390/electronics10080947

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