# A Novel Switched-Capacitor Inverter with Reduced Capacitance and Balanced Neutral-Point Voltage

^{*}

## Abstract

**:**

## 1. Introduction

- (1)
- Less capacitance (200 μF) is used.
- (2)
- There is no problem of neutral-point voltage imbalance.
- (3)
- Good performance is achieved in not only a three-phase four-wire system but also a three-phase three-wire system.
- (4)
- Only one DC source is used as a three-phase topology.
- (5)
- All floating capacitors are used to generate the top voltage level.

## 2. Proposed SCMLI and Operating Principle

_{dc}, V

_{dc}, 1.5 V

_{dc}, −0.5 V

_{dc}, −V

_{dc}, −1.5 V

_{dc}) under different kinds of load conditions. The capacitors’ rated voltage is U

_{N}= 0.5 V

_{dc}. Bidirectional switches are used to block positive and negative voltage stress. The floating capacitors C

_{1,2}are used to generate the top voltage level. They can also balance the voltages of the DC-link capacitors C

_{dc1,2}when needed. Furthermore, the proposed topology is used in a three-phase four-wire system when O and N are connected and is used in a three-phase three-wire system when O and N are not connected.

_{2}, S

_{3}, S

_{11}, and S

_{12}need to be ON, as shown in Figure 2a. In Figure 2b,e, the black and red devices represent two different paths. Both C

_{1}and C

_{2}can be used to generate not only 0.5 V

_{dc}but also −0.5 V

_{dc}. Selecting the right path can make u

_{C1}approach u

_{C2}. In Figure 2c,f, the capacitors C

_{dc1}, C

_{2}and C

_{dc2}, C

_{1}are used to generate V

_{dc}and −V

_{dc}, respectively. To generate 1.5 V

_{dc}, S

_{1}, S

_{7}, S

_{9}, and S

_{10}need to be ON, as shown in Figure 2d. Similarly, to generate −1.5 V

_{dc}, S

_{6}, S

_{7}, S

_{8}, and S

_{13}need to be ON, as shown in Figure 2g. For multilevel inverters, there are several modulation strategies. In this paper, the phase opposition disposition PWM is adopted, which is shown in Figure 2h.

## 3. Capacitor Charging Approaches

_{dc1}, R

_{dc2}, R

_{1}, and R

_{2}are the equivalent resistances of the devices.

#### 3.1. Approach I

_{dc1,2}and one of the floating capacitors C

_{1,2}were used to realize approach I in this paper. The circuit mode with C

_{1}, C

_{dc1}and C

_{dc2}in Figure 3a is taken as an example to illustrate approach I. The approximation that C

_{dc1}= C

_{dc}

_{2}= C

_{1}= C

_{0}and R

_{dc1}= R

_{dc}

_{2}= R

_{1}= R

_{0}is introduced to simplify the analysis. The following analysis is based on this approximation. According to the topology, the equivalent capacitance C

_{eq}and the equivalent resistance R

_{eq}can be expressed as follows:

_{dc2}can be expressed as

_{dc1}satisfies the following differential equation:

_{dc1}initial voltage is u

_{Cdc1}(0) and final voltage is (V

_{dc}+ u

_{Cdc1}(0) − u

_{Cdc2}(0) + u

_{C1}(0))/3. According to the full response theory of the first order circuit, u

_{Cdc1}can be expressed as

_{C1}can be expressed as

_{Cdc1}(0) > 0.5 V

_{dc}> u

_{Cdc2}(0) and u

_{C1}(0) < 0.5 V

_{dc}, capacitors C

_{1}and C

_{dc2}will be charged, and capacitor C

_{dc1}will be discharged according to Equations (4), (6) and (7). When u

_{Cdc1}(0) < 0.5 V

_{dc}< u

_{Cdc2}(0) and u

_{C1}(0) > 0.5 V

_{dc}, capacitors C

_{1}and C

_{dc2}will be discharged, and capacitor C

_{dc1}will be charged similarly. If approach I is adopted, all relevant capacitor voltages will move toward 0.5 V

_{dc}. Furthermore, these voltages will reach 0.5 V

_{dc}if u

_{Cdc1}(0) − u

_{Cdc2}(0) + u

_{C1}(0) = 0.5 V

_{dc}. As shown in Figure 4a, S

_{1}, S

_{8}, S

_{2}, and S

_{3}are ON. C

_{1}and C

_{dc1}are connected in parallel, and approach I is realized. To generate 0 V at the same time, S

_{11}and S

_{12}should be ON. Moreover, 0.5 V

_{dc}and −0.5 V

_{dc}can be generated when S

_{10}and S

_{13}are ON, respectively. As shown in Figure 4b, S

_{2}, S

_{3}, S

_{6}, and S

_{9}are ON. C

_{2}and C

_{dc2}are connected in parallel, and approach I is realized. Similarly, 0 V, 0.5 V

_{dc}, and −0.5 V

_{dc}can be generated at the same time.

#### 3.2. Approach II

_{1}= C

_{2}= C

_{0}and R

_{1}= R

_{2}= R

_{0}. According to the topology, R

_{eq}= 2R

_{0}and C

_{eq}= 0.5C

_{0}. Therefore, i

_{s}is given by

_{eq}(0) = u

_{C1}(0) + u

_{C2}(0). u

_{C1}can be calculated as follows:

_{C2}can be expressed as follows:

_{C1}and u

_{C2}reach 0.5 V

_{dc}, according to Equations (9) and (10). Moreover, u

_{C1}and u

_{C2}will reach 0.5 V

_{dc}if u

_{C1}(0) = u

_{C2}(0). Approach II can be realized when S

_{1}, S

_{8}, S

_{6}, and S

_{9}are ON, as shown in Figure 4c. Any one of 0 V, 0.5 V

_{dc}, and −0.5 V

_{dc}can be generated at the same time. These two charging approaches can be realized, which is an important feature of the proposed three-phase SCMLI.

## 4. Control Strategies to Limit Voltage Ripples

_{1}and C

_{2}, the control strategies can be divided into two aspects. The first aspect involves using approach II and making the average of u

_{C1}and u

_{C2}return to 0.5 V

_{dc}. Approach II is taken when |0.5(u

_{C1}+ u

_{C2}) − 0.5 V

_{dc}| > u

_{γ}. u

_{γ}is an adjustable parameter. The second aspect involves selecting the right path and making u

_{C1}approach u

_{C2}. The path selection for C

_{1,2}is used if |0.5(u

_{C1}+ u

_{C2}) − 0.5 V

_{dc}| < u

_{γ}.

_{dc1}and C

_{dc2}, the control strategies can be divided into two aspects. The first aspect involves using approach I and making u

_{Cdc1}and u

_{Cdc2}move toward 0.5 V

_{dc}. Approach I is taken when |u

_{Cdc1}− u

_{Cdc2}| > u

_{α}. u

_{α}is also an adjustable parameter. The second aspect involves selecting the right path and making u

_{Cdc1}approach u

_{Cdc2}. As u

_{Cdc1}+ u

_{Cdc2}= V

_{dc}, u

_{Cdc1}and u

_{Cdc2}return to 0.5 V

_{dc}when u

_{Cdc1}reaches u

_{Cdc2}. The path selection for C

_{dc1,2}is used if |u

_{Cdc1}− u

_{Cdc2}| < u

_{α}.

_{1}, S

_{8}, S

_{11}, and S

_{12}are ON, and the capacitors C

_{dc1}and C

_{1}are used to generate 0 V. Similarly, S

_{6}, S

_{9}, S

_{11}, and S

_{12}are ON, and capacitors C

_{dc2}and C

_{2}are used to generate 0 V. Moreover, 0.5 V

_{dc}is generated when S

_{1}, S

_{8}, and S

_{10}are ON, as shown in Figure 5b, whereas −0.5 V

_{dc}is generated when S

_{6}, S

_{9}, and S

_{13}are ON, as shown in Figure 5d. In Figure 5c,e, capacitors C

_{1}and C

_{2}can be used to generate not only V

_{dc}but also level −V

_{dc}. For capacitors in the proposed topology, path selection is an important control strategy. As shown in Figure 2 and Figure 5, there are various paths for selection at several voltage levels, and the capacitors used are different, making it easier to balance the capacitor voltages. This is one of the main advantages of the proposed topology.

_{C1,2}and the control strategies of u

_{C}

_{dc1,2}. It is important to make a comprehensive decision according to the latest status. In this paper, the top priority is to decide whether to take approach II. |0.5(u

_{C1}+ u

_{C2}) − 0.5 V

_{dc}| > u

_{γ}, and this is the criterion that u

_{C1}and u

_{C2}have to meet if approach II is to be taken. After that, approach I is taken when |u

_{Cdc1}− u

_{Cdc2}| > u

_{α}. This will make u

_{Cdc1}and u

_{Cdc2}move toward 0.5 V

_{dc}. Then, the path selection for C

_{dc1,2}is used if |u

_{Cdc1}− u

_{Cdc2}| > u

_{β}. u

_{α}is larger than u

_{β}. Lastly, the path selection for C

_{1,2}is used.

## 5. Capacitance Determination

_{dc}, and −0.5 V

_{dc}. Thus, capacitors C

_{1}and C

_{2}are discharged when u

_{ref}> V

_{dc}and i

_{bus}> 0 in the positive half cycle. To address this problem, an important change to the original modulation method is made in this paper, and the new modulation wave in the positive half cycle is shown in Figure 6.

_{ref}> V

_{dc}. These choices are u

_{bus}= V

_{dc}and u

_{bus}= 1.5 V

_{dc}. In this paper, this condition is expressed as u

_{bus}ϵ {V

_{dc}, 1.5 V

_{dc}}. u

_{bus}ϵ {0.5 V

_{dc}, 1.5 V

_{dc}} is added when t

_{1}≤ t ≤ t

_{4}because the abovementioned control strategies can be realized at 0.5 V

_{dc}. Specifically, u

_{bus}ϵ {0.5 V

_{dc}, 1.5 V

_{dc}} is used in half of the switching periods when t

_{1}≤ t ≤ t

_{2}or t

_{3}≤ t ≤ t

_{4}. u

_{bus}ϵ {0.5 V

_{dc}, 1.5 V

_{dc}} is used in all the switching periods when t

_{2}≤ t ≤ t

_{3}.

_{ldt}of floating capacitors in the proposed three-phase SCMLI can be expressed as

_{s}is the switching period, and t

_{c}is the minimum duration of 0.5 V

_{dc}when t

_{1}≤ t ≤ t

_{2}or t

_{3}≤ t ≤ t

_{4}. According to Equation (11), the longest discharging time of floating capacitors in the proposed topology is smaller than 2T

_{s}, which is much shorter than that in other traditional SCMLIs. During the longest discharging time, the current that flows through floating capacitors is i

_{bus}. The voltage variation of floating capacitors that comes from i

_{bus}can be calculated as follows:

_{boost}is the voltage gain. t

_{start}and t

_{end}are the start time and end time of the longest discharging time, respectively. Z

_{MN}is the total impedance between point M and point N. Considering that approach I is adopted, Equation (12) needs to satisfy

_{Cdc1}and u

_{Cdc2}move toward 0.5 V

_{dc}, is taken if |u

_{Cdc1}− u

_{Cdc2}| > u

_{α}. Thus, u

_{Cdc1}and u

_{Cdc2}can be limited to 0.5 V

_{dc}± 0.5 u

_{α}with less DC-link capacitance. Similarly, the voltage variation of the DC-link capacitors between t

_{begin}(the end time of the first approach I) and t

_{finish}(the start time of the second approach I) can be calculated as follows:

_{s}= t

_{finish}− t

_{begin}. To coincide with approach I, Equation (15) needs to satisfy

_{1,2}= C

_{dc12}in this paper.

## 6. Efficiency Calculation

_{con1}can be expressed as

_{si}, r

_{si}, and V

_{si}are the current, internal resistance, and voltage drop of the i-th switch, respectively. N

_{swi}is the number of power switches. T

_{o}and f

_{o}are the period and frequency of the output voltage, respectively. The conduction loss P

_{con2}that comes from the DC-link capacitors and the floating capacitors can be calculated as follows:

_{Ci}and r

_{Ci}are the current and the internal resistance of the i-th capacitor, respectively. N

_{ca}is the number of capacitors. The conduction loss of the output filters P

_{con3}can be calculated as follows:

_{Lfi}and r

_{Lfi}are the current and the internal resistance of the i-th filter inductor, respectively. i

_{Cfi}and r

_{Cfi}are the current and the internal resistance of the i-th filter capacitor, respectively. N

_{fil}is the number of filters.

_{off(i,j)}that is caused by the j-th turning OFF process of the i-th switch is given by

_{off(i,j)}and I

_{off(i,j)}are the voltage after the turning OFF process and the current before the turning OFF process, respectively. Similarly, switching loss P

_{on(i,j)}that is caused by the j-th turning ON process of the i-th switch is given by

_{on(i,j)}and I

_{on(i,j)}are the voltage before the turning ON process and the current after the turning ON process, respectively. According to Equations (21) and (22), the total switching loss P

_{sw}can be calculated by

_{on(i)}and N

_{off(i)}are the number of i-th switch turning ON processes and turning OFF processes, respectively.

## 7. Simulation Results and Comparison

#### 7.1. Simulation Results

_{1}was 40 Ω, 100 mH. u

_{α}was 8 V since the maximum allowable voltage ripple of capacitors was 10 V (10% of the rated voltage). The filter capacitor was 80 μF, and the filter inductor was 4 mH. The switching frequency was 20 kHz. This frequency can reduce the requirement of capacitance according to Equation (15). The output frequency was 50 Hz.

#### 7.1.1. Performance in Three-Phase Four-Wire System

_{o}= Z

_{1}is given. Figure 7a shows the observed A-phase bus voltage. The top voltage level was 300 V, and the proposed three-phase SCMLI could boost the input voltage. Because u

_{α}was equal to 8 V, the voltages of the DC-link capacitors in the A-phase were limited to 96–104 V, as shown in Figure 7b. Approach I could move the voltage of DC-link capacitors toward 100 V when they were larger than 104 V or smaller than 96 V. Figure 7c shows the floating capacitor voltages in the A-phase, which were approximately 96–103 V. It can be seen in this figure that the longest discharging time of floating capacitors was shorter than 2T

_{s}. These waveforms meet the voltage ripple requirement, which should be less than 10% of the rated voltage.

_{o}= 2Z

_{1}to Z

_{o}= Z

_{1}was 0.12 s. The bus voltage of the A-phase is shown in Figure 10a. The difference between the waveform before 0.12 s and the waveform after 0.12 s was not notable. Figure 10b shows the A-phase DC-link capacitor voltages. The voltage ripple of these capacitors was 8 V during the entire process (u

_{α}= 8 V). Figure 10c shows the A-phase floating capacitor voltages. The transient process only lasted for a short period of time (approximately 0.01 s). After that, the floating capacitor voltages quickly returned to the steady state. These waveforms also meet the voltage ripple requirements and are in good agreement with the abovementioned theoretical analysis.

_{o}= 2Z

_{1}. A disturbance load R

_{d}= 100 Ω was only added to the A-phase when 0.8 s < t < 0.85 s. Under this condition, Figure 13a shows the A-phase bus voltage, and there was no obvious change in the waveform when 0.8 s < t < 0.85 s or t > 0.85 s. Figure 13b shows the A-phase DC-link capacitor voltages. Similarly, the transient process only lasted for a short period of time (approximately 0.01 s). During this transient process, u

_{Cdc2}was momentarily larger than 104 V, and u

_{Cdc1}was momentarily smaller than 96 V. After that, the DC-link capacitor voltages were limited to 96–104 V, as before. Figure 13c shows the A-phase floating capacitor voltages. During the same transient process, u

_{C2}was momentarily larger than 105 V. After that, the floating capacitor voltages quickly returned to the steady state.

_{oA}increased because of the disturbance load when 0.8 s < t < 0.85 s. After that (t > 0.85 s), the A-phase output current i

_{oA}quickly returned to the steady state. As for i

_{oB}and i

_{oC}, the disturbance load had no effect because it was only added to the A-phase.

#### 7.1.2. Performance in Three-Phase Three-Wire System

_{NO}was not always equal to 0, the bus voltage had more voltage levels. The resistive–inductive load transient had no effect on the bus voltage. Figure 18b shows the DC-link capacitor voltages of the A-phase. The voltage ripple of these capacitors was 10 V. Figure 18c shows the floating capacitor voltages of the A-phase. They changed from 98–101 V to 96–104 V. All these waveforms met the voltage ripple requirements during the entire process.

#### 7.2. Comparison

- (1)
- Less capacitance (200 μF) is used.

- (2)
- There is no problem of neutral-point voltage imbalance.

- (3)
- Good performance is achieved in not only the three-phase four-wire system but also the three-phase three-wire system.

- (4)
- Only one DC source is used as a three-phase topology.

- (5)
- All floating capacitors are used to generate the top voltage level.

_{dc}, which reaches the average level of other SCMLIs. Two DC-link capacitors and two floating capacitors in each phase are used, and the sum of their rated voltages is 4 V

_{dc}, which is not larger than that of the other three-phase SCMLIs. The proposed topology can generate seven voltage levels under different kinds of load conditions.

## 8. Conclusions

## Author Contributions

## Funding

## Conflicts of Interest

## Nomenclature

u_{N} | Rated voltage of capacitors. |

V_{dc} | Input DC voltage. |

f_{s} and T_{s} | Switching frequency and switching period. |

A_{c} | Amplitude of the carrier waveform. |

u_{ref} | Reference voltage. |

u_{bus} | Bus voltage. |

R_{dc1}, R_{dc2}, R_{1} and R_{2} | Equivalent resistance of the devices. |

R_{0} and C_{0} | It is assumed that R_{dc1} = R_{dc2} = R_{1} = R_{2} = R_{0} and C_{dc1} = C_{dc2} = C_{1} = C_{2} = C_{0}. |

R_{eq} and C_{eq} | Equivalent resistance and equivalent capacitance of the charging topology. |

i_{s} | Current that flows through the DC source in the charging topology. |

u_{Cd1}, u_{Cd2}, u_{C1}, u_{C2} | Voltage of capacitors. |

i_{Cd1}, i_{Cd2}, i_{C1}, i_{C2} | Current of capacitors. |

u_{Cdc1}(0), u_{Cdc2}(0), u_{C1}(0), u_{C2}(0) | Initial voltage of capacitors. |

u_{eq}(0) | Initial voltage of the equivalent capacitor. |

u_{α}, u_{β}, u_{γ} | Adjustable parameters that represent the requirements of selecting the appropriate control strategy. |

i_{bus} | Bus current that flows through the filter inductor. |

t_{ldt} | The longest discharging time of floating capacitors. |

t_{c} | Minimum duration of 0.5 V_{dc} voltage level. |

m | Modulation index. |

A_{boost} | Voltage gain. |

t_{start} and t_{end} | Start time and end time of the longest discharging time. |

Z_{MN} | Total impedance between point M and point N (can be calculated by the filter parameter and the load condition). |

t_{begin} and t_{finish} | End time of the first approach I and Start time of the next approach I. |

k | A parameter that satisfies the equation kT_{s} = t_{finish} − t_{begin}. |

P_{con1} | Conduction loss of the power switches. |

i_{si}, r_{si}, and V_{si} | Current, internal resistance and voltage drop of the ith switch. |

N_{swi} | Number of power switches. |

f_{o} and T_{o} | Frequency and period of the output voltage. |

P_{con2} | Conduction loss that comes from DC-link and floating capacitors. |

i_{Ci} and r_{Ci} | Current and internal resistance of the ith capacitor. |

N_{cap} | Number of capacitors. |

P_{con3} | Conduction loss of the output filters. |

i_{Lfi} and r_{Lfi} | Current and internal resistance of the i-th filter inductor. |

i_{Cfi} and r_{Cfi} | Current and internal resistance of the i-th filter capacitor. |

N_{fil} | Number of filters. |

P_{off(i,j)} | Switching loss caused by the j-th turning OFF process of the i-th switch. |

V_{off(i,j)} and I_{off(i,j)} | Voltage after the j-th turning OFF process of the i-th switch and current before the j-th turning OFF process of the i-th switch |

P_{on(i,j)} | Switching loss caused by the j-th turning ON process of the i-th switch. |

V_{on(i,j)} and I_{on(i,j)} | Voltage before the j-th turning ON process of the i-th switch and current after the j-th turning ON process of the i-th switch. |

P_{sw} | Total switching loss. |

N_{on(i)} and N_{off(i)} | Number of i-th switch turning ON processes and turning OFF processes. |

η | Overall efficiency of the proposed topology. |

P_{o} | Output power. |

Z_{o} | Load impedance. |

Z_{1} | Load condition that is adopted in this paper. |

R_{d} | A disturbance load that is only added to the A-phase temporarily. |

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**Figure 2.**Main switching states of the proposed three-phase SCMLI at (

**a**) 0 V, (

**b**) 0.5 V

_{dc}, (

**c**) V

_{dc}, (

**d**) 1.5 V

_{dc}, (

**e**) −0.5 V

_{dc}, (

**f**) −V

_{dc}, and (

**g**) −1.5 V

_{dc}. (

**h**) The waveform of the phase opposition disposition PWM in the positive quarter cycle (switching frequency f

_{s}= 5 kHz).

**Figure 4.**Switching states when (

**a**) approach I is realized and C

_{1}is used, (

**b**) approach I is realized and C

_{2}is used, and (

**c**) approach II is realized.

**Figure 5.**Redundant switching states of the proposed three-phase SCMLI structure at (

**a**) 0 V, (

**b**) 0.5 V

_{dc}, (

**c**) V

_{dc}, (

**d**) −0.5 V

_{dc}, and (

**e**) −V

_{dc}.

**Figure 7.**(

**a**) The bus voltage, (

**b**) DC-link capacitor voltages and (

**c**) floating capacitor voltages of the A-phase under the resistive–inductive load condition.

**Figure 8.**(

**a**) The output voltage of each phase under the resistive–inductive load condition. (

**b**) The FFT result of the A-phase output voltage.

**Figure 9.**(

**a**) The output current of each phase under the resistive–inductive load condition. (

**b**) The FFT result of the A-phase output current.

**Figure 10.**(

**a**) The bus voltage, (

**b**) DC-link capacitor voltages and (

**c**) floating capacitor voltages of the A-phase during a resistive–inductive load transient.

**Figure 11.**(

**a**) The output voltage of each phase during a resistive–inductive load transient. (

**b**) The FFT result of the A-phase output voltage.

**Figure 13.**(

**a**) The bus voltage, (

**b**) DC-link capacitor voltages and (

**c**) floating capacitor voltages of the A-phase when the disturbance load was added to the A-phase.

**Figure 14.**(

**a**) The output voltage of each phase when the disturbance load was added to the A-phase. (

**b**) The FFT result of the A-phase output voltage.

**Figure 18.**(

**a**) The bus voltage, (

**b**) DC-link capacitor voltages and (

**c**) floating capacitor voltages of the A-phase during a resistive–inductive load transient.

**Figure 19.**(

**a**) The output voltage of each phase during a resistive–inductive load transient. (

**b**) The FFT result of the A-phase output voltage.

STATES | Voltage | Figure Position | Switches | ||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|

Level | S_{1} | S_{2} | S_{3} | S_{4} | S_{5} | S_{6} | S_{7} | S_{8} | S_{9} | S_{10} | S_{11} | S_{12} | S_{13} | ||

1 | 1.5 V_{dc} | Figure 2 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 0 | 0 | 0 |

2 | V_{dc} | Figure 2 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 1 | 1 | 0 |

3 | V_{dc} | Figure 5 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 |

4 | 0.5 V_{dc} | Figure 4 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 1 | 0 | 0 | 0 |

5 | 0.5 V_{dc} | Figure 4 | 0 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | 0 | 0 | 0 |

6 | 0.5 V_{dc} | Figure 4 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 |

7 | 0.5 V_{dc} | Figure 5 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 |

8 | 0.5 V_{dc} | Figure 2 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 |

9 | 0.5 V_{dc} | Figure 2 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 0 |

10 | 0 V | Figure 4 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 0 | 1 | 1 | 0 |

11 | 0 V | Figure 4 | 0 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 1 | 1 | 0 |

12 | 0 V | Figure 4 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | 0 |

13 | 0 V | Figure 5 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | 0 |

14 | 0 V | Figure 5 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 1 | 1 | 0 |

15 | 0 V | Figure 2 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 |

16 | −0.5 V_{dc} | Figure 4 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 1 |

17 | −0.5 V_{dc} | Figure 4 | 0 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 1 |

18 | −0.5 V_{dc} | Figure 4 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 |

19 | −0.5 V_{dc} | Figure 5 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 1 |

20 | −0.5 V_{dc} | Figure 2 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |

21 | −0.5 V_{dc} | Figure 2 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 1 | 0 | 0 | 1 | 1 | 0 |

22 | −V_{dc} | Figure 2 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 0 | 0 | 1 | 1 | 0 |

23 | −V_{dc} | Figure 5 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 1 |

24 | −1.5 V_{dc} | Figure 2 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 1 |

Capacitors | Control Strategy |
---|---|

C_{1} and C_{2} | Approach II, path selection |

C_{dc1} and C_{dc2} | Approach I, path selection |

Parameters | Value |
---|---|

V_{dc} | 200 V |

Capacitor rated voltage | 100 V |

Modulation ratio | 0.95 |

Output voltage | 285 V |

C_{1}, C_{2}, C_{dc1}, and C_{dc2} | 200 μF |

Output power | 1884 W |

Resistive–inductive load Z_{1} | 40 Ω, 100 mH |

u_{α} | 8 V |

Filter capacitor | 80 μF |

Filter inductor | 4 mH |

Switching frequency | 20 kHz |

Output frequency | 50 Hz |

[19] | [20] | [26] | [27] | [30] | [31] | [32] | [33] | Proposed Topology | |
---|---|---|---|---|---|---|---|---|---|

C_{DC-link} | 4700 4700 | - | - | - | - | - | 1000 1000 | 4700 4700 | 200 200 |

C_{floating} | 4700 4700 | 6800 6800 3300 | 4330 4320 2190 | 1000 1000 | 2200 2200 2200 | 2200 /2200 | 1000 | 4700 | 200 200 |

N_{ca_3p} | 8 | 9 | 9 | 6 | 9 | 6 | 5 | 5 | 8 |

TRV_{ca_3p} | 4 | 15 | 15 | 3 | 6 | 3 | 4 | 4 | 4 |

ε_{ca} | 100% | 100% | 80% | 100% | 50% | 100% | 100% | 100% | 100% |

N_{DC_3p} | 1 | 3 | 3 | 3 | 3 | 3 | 1 | 1 | 1 |

Load condition | 40 Ω 100 mH | 50 Ω 30 mH | 42.2 Ω 79 mH | 200 Ω | 30 Ω 30 mH | 10 Ω 100 mH | 160 Ω | 40 Ω 100 mH | 40 Ω 100 mH |

m | 1.0 | 0.9 | 0.91 | 1.0 | 1.0 | 1.0 | 1.0 | 1.0 | 0.95 |

Suffering from imbalance | yes | no | no | yes | yes | yes | yes | yes | no |

A_{boost} | 1.5 | 6 | 4 | 2 | 2 | 2 | 1.5 | 1.5 | 1.5 |

N_{level} | 7 | 13 | 9 | 9 | 9 | 9 | 7 | 7 | 7 |

N_{sd} | 10 | 15 | 12 | 11 | 11 | 10 | 9 | 9 | 13 |

TSV_{sw} | 9 | 33 | 24 | 12 | 10 | 11 | 8 | 8 | 11 |

_{DC}

_{-link}is the DC-link capacitance (μF). C

_{floating}is the floating capacitance (μF). N

_{ca_3p}is the number of capacitors in the three-phase applications. TRV

_{ca_3p}is the total rated voltage of capacitors (Vdc) in the three-phase applications. ε

_{ca}is the share of the floating capacitors voltages that are used to generate the top voltage level. N

_{DC_3p}is the number of DC sources in the three-phase applications. N

_{level}is the number of voltage levels. N

_{sd}is the number of power switches and diodes in each phase. TSV

_{sw}is the total standing voltage of switches (V

_{dc}) in each phase.

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## Share and Cite

**MDPI and ACS Style**

Xun, Z.; Ding, H.; He, Z.
A Novel Switched-Capacitor Inverter with Reduced Capacitance and Balanced Neutral-Point Voltage. *Electronics* **2021**, *10*, 947.
https://doi.org/10.3390/electronics10080947

**AMA Style**

Xun Z, Ding H, He Z.
A Novel Switched-Capacitor Inverter with Reduced Capacitance and Balanced Neutral-Point Voltage. *Electronics*. 2021; 10(8):947.
https://doi.org/10.3390/electronics10080947

**Chicago/Turabian Style**

Xun, Zhuyu, Hongfa Ding, and Zhou He.
2021. "A Novel Switched-Capacitor Inverter with Reduced Capacitance and Balanced Neutral-Point Voltage" *Electronics* 10, no. 8: 947.
https://doi.org/10.3390/electronics10080947