# Memristor-Based Loop Filter Design for Phase Locked Loop

^{*}

## Abstract

**:**

## 1. Introduction

## 2. Memristor

_{2}) memristor model in this work.

_{source}= Asin(wt), where A = 1.2 V and w = 2 π rad/s. However, the basic characteristics of a memristor are described in Figure 3, Figure 4 and Figure 5.

_{v}= (10

^{-12}) m

^{2}/V-sec and $p=10$. $\mathrm{The}\text{}{R}_{init}\text{}and\text{}p$ parameters denote the initial resistance and exponent of window function, respectively. ${R}_{ON}$ is the resistance of the doped memristor and ${R}_{OFF}$ is for the undoped memristor. D is the width of the thin film and ${\mathsf{\mu}}_{v}$ is the dopant mobility.

## 3. PLL Building Blocks

#### 3.1. Phase Detector

#### 3.2. Charge Pump/Loop Filter

#### 3.3. Voltage Controlled Oscillator

#### 3.4. Frequency Divider

## 4. Results and Discussion

## 5. Conclusions

## Author Contributions

## Funding

## Conflicts of Interest

## References

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**Figure 2.**Simulation output of the memristor model: (

**a**) Voltage output of the memristor; (

**b**) current output of the memristor.

Control Voltage (V) | VCO Frequency (GHz) |
---|---|

4.450 | 0.741 |

4.726 | 0.846 |

4.876 | 0.926 |

4.955 | 0.971 |

4.992 | 1.010 |

Control Voltage (V) | K_{VCO} (GHz/V) |
---|---|

4.450 | 0.594 |

4.726 | 0.550 |

4.876 | 0.592 |

4.955 | 0.908 |

4.992 | 1.022 |

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**MDPI and ACS Style**

Adesina, N.O.; Srivastava, A.
Memristor-Based Loop Filter Design for Phase Locked Loop. *J. Low Power Electron. Appl.* **2019**, *9*, 24.
https://doi.org/10.3390/jlpea9030024

**AMA Style**

Adesina NO, Srivastava A.
Memristor-Based Loop Filter Design for Phase Locked Loop. *Journal of Low Power Electronics and Applications*. 2019; 9(3):24.
https://doi.org/10.3390/jlpea9030024

**Chicago/Turabian Style**

Adesina, Naheem Olakunle, and Ashok Srivastava.
2019. "Memristor-Based Loop Filter Design for Phase Locked Loop" *Journal of Low Power Electronics and Applications* 9, no. 3: 24.
https://doi.org/10.3390/jlpea9030024