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Sizing of SRAM Cell with Voltage Biasing Techniques for Reliability Enhancement of Memory and PUF Functions^{ †}

^{*}

^{†}

## Abstract

**:**

## 1. Introduction

## 2. Impact of Process Variations (PV) on Different Operation Modes

#### 2.1. Impact of PV on Physical Unclonable Function (PUF) Quality

#### 2.1.1. Mismatch of INV-1 and INV-2

#### 2.1.2. Loop-Gain at Trip Point

#### 2.2. Impact of PV on SRAM Read/Write Failures

## 3. Proposed Design Method for Dual-Mode PUF

#### 3.1. Circuit-Level Techniques

#### 3.1.1. WLM

#### 3.1.2. DVS

#### 3.1.3. NBL

#### 3.1.4. ABB

#### 3.1.5. Comparison of Different Reliability Enhancement Techniques

#### 3.2. Problem Formulation

#### 3.2.1. Failure Probability

#### 3.2.2. Reliability

#### 3.2.3. Area

#### 3.2.4. Power Consumption

## 4. Simulation Results and Discussions

#### 4.1. Uniqueness

#### 4.2. Randomness

## 5. Conclusions

## Acknowledgments

## Author Contributions

## Conflicts of Interest

## References

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**Figure 1.**(

**a**) Architectural diagram of an SRAM-based PUF (SPUF); (

**b**) PUF and memory modes of operation of a 6-transistor Static Random Access Memory (SRAM) cell in an SPUF.

**Figure 2.**Design conflict of a SRAM cell for dual-mode applications. Increasing the variation of ${V}_{th}$ improves the quality of PUF at the expense of higher failure rates in regular memory read/write operations.

**Figure 3.**(

**a**) BIT and BITB node voltages of SRAM cell during power-up process. The two curves set apart when one of them reaches the trip point of the inverter; (

**b**) state evolution at power-up.

**Figure 4.**(

**a**) Changes in ${\sigma}_{{V}_{th}}$ with transistor effective channel length [10]; (

**b**) relationship between the percentage of unreliable bits and the scaling factor of SRAM cell template, where the widths of pull-down, pull-up and access transistors of a unit-size SRAM cell are ${W}_{M1}=180\phantom{\rule{3.33333pt}{0ex}}\text{nm}$, ${W}_{M2}=90\phantom{\rule{3.33333pt}{0ex}}\text{nm}$ and ${W}_{M3}=135\phantom{\rule{3.33333pt}{0ex}}\text{nm}$, respectively, and all transistors have $L=45\phantom{\rule{3.33333pt}{0ex}}\text{nm}$.

**Figure 6.**(

**a**) Read and (

**b**) write failure effects in an SRAM cell. The original bit preserved in the cell is 1.

**Figure 7.**The relationship between the failure probability and the transistor widths (

**a**) M1; (

**b**) M2; (

**c**) M3.

**Figure 12.**Static noise margins by applying different circuit-level techniques: (

**a**) Word-Line Voltage Modulation (WLM); (

**b**) Dynamic Voltage Scaling (DVS); (

**c**) Negative Bit-Line (NBL); (

**d**) Adaptive Body Bias (ABB) (NMOS only) (

**e**) ABB (PMOS only); (

**f**) ABB (both NMOS and PMOS).

Technique | Column-Based | S(Read) | S(Write) | Other Drawbacks |
---|---|---|---|---|

WLM | × | $0.325$ | 0 | - |

DVS | √ | $0.323$ | $0.006$ | - |

NBL | √ | 0 | $0.908$ | - |

ABB (NMOS only) | × | $0.009$ | $0.016$ | Triple-well process, Large area overhead |

ABB (PMOS only) | × | $0.026$ | $0.006$ | |

ABB (Both MOSFETs) | × | $0.114$ | $0.015$ |

**Table 2.**Simulation results @${V}_{DD}=0.9$ V, temperature $=25{\phantom{\rule{3.33333pt}{0ex}}}^{\circ}$C.

Description | Design | X | M | $\mathbf{Pr}\mathbf{\left(}\mathbf{RF}\mathbf{\right)}$ | $\mathbf{Pr}\mathbf{\left(}\mathbf{WF}\mathbf{\right)}$ | $\mathbf{Pr}\mathbf{\left(}\mathbf{RF},\mathbf{WF}\mathbf{\right)}$ | BER | Area | Leakage | Power |
---|---|---|---|---|---|---|---|---|---|---|

Single-mode PUF | 1 | $(180,\phantom{\rule{4pt}{0ex}}90,\phantom{\rule{4pt}{0ex}}135)$ | $N.A.$ | $0.131$ | $0.136$ | $0.249$ | $1.37\times {10}^{-7}$ | $0.45$ | $25.2$ | 140 |

Single-mode memory | 2 | $(500,\phantom{\rule{4pt}{0ex}}250,\phantom{\rule{4pt}{0ex}}375)$ | $N.A.$ | $0.022$ | $0.047$ | $0.068$ | $3.29\times {10}^{-2}$ | $1.28$ | $73.2$ | 405 |

Dual-mode SPUF | 3 | $(202,\phantom{\rule{4pt}{0ex}}101,\phantom{\rule{4pt}{0ex}}152)$ | $N.A.$ | $0.118$ | $0.125$ | $0.229$ | $9.73\times {10}^{-7}$ | $0.49$ | $28.5$ | 158 |

4 | $(202,\phantom{\rule{4pt}{0ex}}101,\phantom{\rule{4pt}{0ex}}152)$ | $WLM$ | $0.021$ | $0.125$ | $0.143$ | $9.73\times {10}^{-7}$ | $0.49$ | $28.5$ | 154 | |

5 | $(202,\phantom{\rule{4pt}{0ex}}101,\phantom{\rule{4pt}{0ex}}152)$ | $DVS$ | $0.027$ | $0.036$ | $\mathbf{0}.\mathbf{062}$ | $9.73\times {10}^{-7}$ | $0.49$ | $19.8$ | 143 | |

6 | $(202,\phantom{\rule{4pt}{0ex}}101,\phantom{\rule{4pt}{0ex}}152)$ | $NBL$ | $0.118$ | $0.004$ | $0.122$ | $9.73\times {10}^{-7}$ | $0.49$ | $28.5$ | 155 | |

Dual-mode RO PUF | 7 | − | − | $0.51$ | $1.46\times {10}^{-10}$ | − | − | − |

Test Description | Passed/Total | P-value | Pass? |
---|---|---|---|

Frequency | 98/100 | 0.145 | √ |

Block Frequency ($m=128$) | 100/100 | 0.262 | √ |

Cusum-Forward | 98/100 | 0.249 | √ |

Cusum-Reverse | 99/100 | 0.817 | √ |

Runs | 97/100 | 0.102 | √ |

Longest Run of Ones | 98/100 | 0.868 | √ |

Rank | 100/100 | 0.015 | √ |

Spectral DFT | 100/100 | 0.024 | √ |

Non-overlapping Templates ($m=9,B=000000001$) | 99/100 | 0.367 | √ |

Overlapping Templates ($m=9$) | 99/100 | 0.898 | √ |

Approximate Entropy $(m=4)$ | 98/100 | 0.475 | √ |

Linear Complexity ($m=1000$) | 96/100 | 0.035 | √ |

Serial $(m=16,\u25bd{\mathrm{\Psi}}_{m}^{2})$ | 100/100 | 0.038 | √ |

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**MDPI and ACS Style**

Chang, C.-H.; Liu, C.Q.; Zhang, L.; Kong, Z.H.
Sizing of SRAM Cell with Voltage Biasing Techniques for Reliability Enhancement of Memory and PUF Functions. *J. Low Power Electron. Appl.* **2016**, *6*, 16.
https://doi.org/10.3390/jlpea6030016

**AMA Style**

Chang C-H, Liu CQ, Zhang L, Kong ZH.
Sizing of SRAM Cell with Voltage Biasing Techniques for Reliability Enhancement of Memory and PUF Functions. *Journal of Low Power Electronics and Applications*. 2016; 6(3):16.
https://doi.org/10.3390/jlpea6030016

**Chicago/Turabian Style**

Chang, Chip-Hong, Chao Qun Liu, Le Zhang, and Zhi Hui Kong.
2016. "Sizing of SRAM Cell with Voltage Biasing Techniques for Reliability Enhancement of Memory and PUF Functions" *Journal of Low Power Electronics and Applications* 6, no. 3: 16.
https://doi.org/10.3390/jlpea6030016