# Stochastic-Based Spin-Programmable Gate Array with Emerging MTJ Device Technology

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## Abstract

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## 1. Introduction

- We invented a new curve-based method to reinterpret and redefine Boolean logic functions, therefore can efficiently implement multiple-input-multiple-output logic block without noticeable hardware usage overheads. This technique compounds the overall performance benefits resulting from the MTJ devices.
- Taylor expansion, although mathematically elegant and powerful, has never been considered in hardware-assisted functional evaluation due to its excessive hardware cost. Our stochastic-based approach natively exploits the inherent Gaussian-like stochastic switching behavior of the emerging spintronic devices, therefore bypassing the excessive hardware overhead of Boolean-based methodology.
- Due to the SPGA’s unconventional architectural features, we have made several modifications to the existing academic-grade software flow of logic synthesis, technology mapping, placement, and routing. In particular, given the freedom of configuring the output number of SLBs, we developed a variant of the conventional technology mapping algorithm based on computing (k, l)-feasible cuts.

## 2. Architecture Overview

## 3. Stochastic-Based Logic Block (SLB)

#### 3.1. Algebraically Reinterpreting K-Map

#### 3.2. Stochastic Switching with MTJ Devices

#### 3.3. Detailed Circuit Design of SLB

## 4. Interconnect Architecture

## 5. CAD Algorithms

#### 5.1. Logic Synthesis and Technology Mapping Algorithm

Algorithm 1 Algorithm of computing (k, l)-feasible cuts. | |

1: | kcuts ← $\mathtt{compute\_kcuts}$(AIG, k) |

2: | lcuts ← $\mathtt{compute\_lcuts}$(AIG, l) |

3: | for each lcut ∈ lcuts do |

4: | P ← $\mathtt{combine\_kcuts}$(lcuts) |

5: | for each π∈P do |

6: | klcut ← $\mathtt{create\_klcut}$(π, lcut) |

7: | if $\mathtt{check\_and\_fix}$(klcut) then |

8: | klcuts.add(klcut) |

9: | end if |

10: | end for |

11: | end for |

12: | return klcut |

#### 5.2. Placement Algorithm

Algorithm 2 The placement algorithm of SPGA. | |

1: | $p\leftarrow $ RandomPlacement() |

2: | $T\leftarrow $ InitialTemperature() |

3: | $g\leftarrow $ g($\mathcal{A}$,p) |

4: | freeze_count < 50 |

5: | while (ExitCriterion() is FALSE) do |

6: | changes ← 0 |

7: | trials ← 0 |

8: | $c\leftarrow $ EvaluateCost(g,b) |

9: | while (InnerLoopCriterion() is FALSE) do |

10: | trials ← trials + 1 |

11: | ${p}_{\mathrm{new}}\leftarrow $ RandomSwap(p) |

12: | IncrementalRoute(g($\mathcal{A}$,${p}_{\mathrm{new}}$), b) |

13: | $\Delta c\leftarrow $ EvaluateCost(g($\mathcal{A}$, ${p}_{\mathrm{new}}$)) −c |

14: | if $\Delta c<0$ /*downhill move*/ then |

15: | changes ← changes + 1 |

16: | $p\leftarrow {p}_{\mathrm{new}}$ |

17: | $g\leftarrow $ g($\mathcal{A}$, p) |

18: | ${c}^{*}\leftarrow $ EvaluateCost(g($\mathcal{A}$, ${p}_{\mathrm{new}}$)) |

19: | end if |

20: | if $\Delta c>0$ /*uphill move*/ then |

21: | $r\leftarrow $ Random(0,1) |

22: | if $r<{e}^{-\frac{\Delta c}{T}}$ then |

23: | $s\leftarrow {p}_{\mathrm{new}}$ |

24: | $g\leftarrow $ g($\mathcal{A}$, p) |

25: | end if |

26: | end if |

27: | end while |

28: | $T\leftarrow $ UpdateTemperature() |

29: | if ${c}^{*}$ changes then |

30: | freeze_count ← 0 |

31: | end if |

32: | if $\frac{changes}{trials}<0.01$ then |

33: | freeze_count ← freeze_count + 1 |

34: | end if |

35: | end while |

#### 5.3. Routing Algorithm

## 6. Performance Analysis and Comparison

## 7. Error Analysis

## 8. Conclusions

## Acknowledgments

## Author Contributions

## Conflicts of Interest

## References

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**Figure 1.**(

**a**) Cross-section of a Magnetic Tunnel Junctions (MTJ)-CMOS hybrid chip; (

**b**) Monolithically stacked 3D-Field Programmable Gate Arrays (FPGA) [7].

**Figure 2.**(

**a**) 2-D Island-style FPGA architecture; (

**b**) Spin-programmable Gate Array (SPGA) architecture with hybrid MTJ-CMOS devices.

**Figure 3.**(

**a**) Logic diagram of a 4:2 encoder; (

**b**) Truth table; (

**c**) Encoded inputs and outputs; (

**d**) Logic curve interpretation.

**Figure 5.**Circuit design of random bit stream generation. (

**a**) Configuration mode; (

**b**) Operation mode. Devices in gray area are active for each mode. Red curves depict signal directions.

**Figure 6.**(

**a**) Simple conventional LB; (

**b**) Architecture of stochastic-based logic block (SLB); (

**c**) Programmable random bit generator.

**Figure 12.**The logic synthesis of large fanin and multible fanout Loop-Up table is shown and simulated through logic synthesis tool ABC. The 4 benchmark circuits are taken into consideration. In this Figure, we can see to deceasing trends, one is with Look-Up table size increasing, another is with output increasing. The results show that with the Look-Up table size and output number increasing. The number of nodes in logic network is significantly decreasing. The ratio of decreasing is trending slow, since the small input and output node is decreasing.

**Figure 13.**Layout area measuring model. (

**a**) Conventional transistor layout; (

**b**) 3D MTJ and control transistor layout.

**Figure 15.**(

**a**) The mean square error (MSE) simulation of stochastic bit stream with increasing of bit flip error rate both in analytical and simulation method; (

**b**) The MSE simulation of stochastic bit stream with different probability both in analytical and simulation method [43].

**Figure 16.**(

**a**) Simulation of theoretical and simulated results; (

**b**) Random bit stream error with different bit length.

**Table 1.**Delay of proposed new stochastic FPGA architecture. The CMOS device is using $0.18$ $\mathsf{\mu}\mathrm{s}$ process.

$\mathbf{A}\mathbf{\to}\mathbf{B}\mathbf{(}\mathbf{ps}\mathbf{)}$ | $\mathbf{B}\mathbf{\to}\mathbf{C}\mathbf{(}\mathbf{ps}\mathbf{)}$ | $\mathbf{C}\mathbf{\to}\mathbf{D}\mathbf{(}\mathbf{ps}\mathbf{)}$ | $\mathbf{D}\mathbf{\to}\mathbf{E}\mathbf{(}\mathbf{ps}\mathbf{)}$ | $\mathbf{E}\mathbf{\to}\mathbf{F}\mathbf{(}\mathbf{ps}\mathbf{)}$ |
---|---|---|---|---|

301.3 | 305.1 | 250.2 | 522.4 | 478.1 |

STT-MRAM | Proposed | |
---|---|---|

transistor count | 154 MOS + 32 MTJ | 6 MOS + 32 MTJ |

active power ($\mathsf{\mu}\mathrm{W}$) | 13.4 | 3.22 |

standby power ($\mathsf{\mu}\mathrm{W}$) | 0 | 0 |

**Table 3.**Benchmark circuit synthesis using propose Look-Up table architecture with large input and output number.

Design | Conv. 2D Arch. | RRAM FPGA [39] | 3D CMOS FPGA [10,40] | 3D rFPGA [41] | Proposed SPGA Arch. | |||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|

# of | Area | Delay | Power | # of | Area | Delay | Power | # of | Area | Delay | Power | # of | Area | Delay | Power | # of | Area | Delay | Power | |

LUTs | $\mathbf{(}{\mathbf{10}}^{\mathbf{5}}$ $\mathsf{\mu}{\mathbf{m}}^{\mathbf{2}}$) | (ns) | (mW) | LUTs | $\mathbf{(}{\mathbf{10}}^{\mathbf{5}}$ $\mathsf{\mu}{\mathbf{m}}^{\mathbf{2}}$) | (ns) | (mW) | LUTs | $\mathbf{(}{\mathbf{10}}^{\mathbf{5}}$ $\mathsf{\mu}{\mathbf{m}}^{\mathbf{2}}$) | (ns) | (mW) | LUTs | $\mathbf{(}{\mathbf{10}}^{\mathbf{5}}$ $\mathsf{\mu}{\mathbf{m}}^{\mathbf{2}}$) | (ns) | (mW) | LUTs | $\mathbf{(}{\mathbf{10}}^{\mathbf{5}}$ $\mathsf{\mu}{\mathbf{m}}^{\mathbf{2}}$) | (ns) | (mW) | |

alu4 | 512 | 1.37 | 7.13 | 62 | 512 | 0.87 | 17.5 | 54 | 512 | 6.88 | 3.64 | 56.2 | 512 | 5.86 | 3.64 | 46.6 | 63 | 1.44 | 4.13 | 10.78 |

apex2 | 706 | 1.66 | 8.6 | 67 | 706 | 0.88 | 18.77 | 55 | 706 | 8.3 | 4.38 | 62.1 | 706 | 6.18 | 4.38 | 53.1 | 109 | 2.11 | 4.34 | 11.22 |

apex4 | 618 | 4.14 | 7.3 | 42 | 618 | 2.01 | 17.6 | 37 | 618 | 20.73 | 3.74 | 40.3 | 618 | 11.54 | 3.74 | 29.8 | 131 | 3.18 | 4.22 | 12.2 |

mise3 | 500 | 4.62 | 7.42 | 51.3 | 500 | 2.88 | 17.42 | 47.02 | 500 | 6.2 | 3.37 | 49.9 | 500 | 4.76 | 3.37 | 38.4 | 97 | 1.98 | 4.11 | 10.98 |

diffeq | 526 | 3.91 | 5.56 | 24 | 526 | 2.05 | 15.77 | 19 | 526 | 5.01 | 3.24 | 25.2 | 526 | 4.38 | 3.24 | 23.2 | 139 | 3.19 | 4.23 | 12.36 |

elliptic | 133 | 2.30 | 10.7 | 69 | 133 | 1.65 | 21 | 58 | 133 | 10.68 | 5.96 | 70.2 | 133 | 7.19 | 5.96 | 58.7 | 158 | 3.58 | 5.37 | 20.6 |

ex1010 | 612 | 1.24 | 14.6 | 113 | 612 | 0.75 | 25.6 | 105 | 612 | 19.56 | 5.94 | 116 | 612 | 11.32 | 5.94 | 97.9 | 113 | 2.38 | 4.85 | 11.31 |

frisc | 1905 | 1.6 | 13.3 | 62.7 | 1905 | 0.8 | 24.5 | 56.5 | 1905 | 11.5 | 6.95 | 67.2 | 1905 | 8.54 | 6.95 | 68.3 | 176 | 4.33 | 4.58 | 30.83 |

seq | 739 | 2.64 | 8.4 | 65 | 739 | 1.82 | 19.5 | 55 | 739 | 7.5 | 3.74 | 62 | 739 | 5.5 | 3.74 | 50.2 | 118 | 2.41 | 4.15 | 11.86 |

spla | 449 | 1.37 | 13.3 | 87 | 449 | 16.3 | 5.67 | 95.4 | 449 | 0.74 | 24.3 | 78 | 449 | 9.03 | 5.67 | 55.7 | 116 | 2.39 | 4.51 | 11.45 |

pdc | 276 | 4.38 | 16.8 | 101 | 276 | 2.77 | 18.8 | 96 | 276 | 18.4 | 7.69 | 107 | 276 | 10.76 | 7.69 | 77.5 | 141 | 3.22 | 5.75 | 15.81 |

tseng | 539 | 1.66 | 6.96 | 29 | 539 | 0.83 | 3.48 | 25 | 539 | 3.92 | 3.54 | 30.1 | 539 | 3.89 | 3.54 | 29.8 | 108 | 2.05 | 3.88 | 11.12 |

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**MDPI and ACS Style**

Bai, Y.; Lin, M.
Stochastic-Based Spin-Programmable Gate Array with Emerging MTJ Device Technology. *J. Low Power Electron. Appl.* **2016**, *6*, 15.
https://doi.org/10.3390/jlpea6030015

**AMA Style**

Bai Y, Lin M.
Stochastic-Based Spin-Programmable Gate Array with Emerging MTJ Device Technology. *Journal of Low Power Electronics and Applications*. 2016; 6(3):15.
https://doi.org/10.3390/jlpea6030015

**Chicago/Turabian Style**

Bai, Yu, and Mingjie Lin.
2016. "Stochastic-Based Spin-Programmable Gate Array with Emerging MTJ Device Technology" *Journal of Low Power Electronics and Applications* 6, no. 3: 15.
https://doi.org/10.3390/jlpea6030015