# Performance Limits of Nanoelectromechanical Switches (NEMS)-Based Adiabatic Logic Circuits

^{*}

## Abstract

**:**

## 1. Introduction

## 2. Adiabatic Charging of an RC Circuit

_{dd}. This constant voltage charging results in dissipative energy losses of for a charge-discharge cycle. This remains the case regardless of the values of the series resistance or load capacitance.

_{S}is added to represent the change in the NEMS device capacitance upon commutation (the origin of this change in capacitance will be detailed in Section 4). Also shown is the typical four-phase power clock (ϕ) used, where the ramp-up, hold, and the ramp-down times are shown each having a period T. In a typical adiabatic circuit, both the power clock and the input have the same waveform with a T phase shift between the two [4].

**Figure 1.**Schematic representation of an equivalent logic circuit showing the four phase power clock with equal length segments: F represents the block logic function; R

_{S}is the series resistance dominated by the switch resistance; C

_{L}represents the load capacitance that is mainly due to interconnect capacitance; and C

_{S}represents the nanoelectromechanical switches (NEMS) variable capacitance. The current provided by the power clock is labeled i; the current going into the static interconnect capacitance (C

_{L}) is labeled i

_{1}; and that going into the variable capacitance of the NEMS switch (C

_{S}) is labeled i

_{2}.

## 3. CMOS-Based Adiabatic Logic Circuits

#### 3.1. Classical CMOS Circuits

_{dd}is the voltage of the hold phase as shown in Figure 1.

_{leak}represents the average leakage current over a complete clock period.

**Figure 2.**Schematic representation of a CMOS implementation of an adiabatic logic function F, also identifying the leakage current. This architecture is known as the Positive Feedback Adiabatic Logic (PFAL) architecture [4]; however, the obtained results apply as a first order approximation to other architectures as well.

_{leakage}given by:

_{0}is a function of the transistor size and parameters; V

_{t}is the thermal voltage ; and V

_{DS}is the source-drain voltage which is assumed to perfectly follow the power clock.

_{leakage}is the leakage energy dissipation, and the first, second and third integrals correspond to the rising phase, the hold phase, and the decreasing phase of the power clock respectively.

_{S}of a MOSFET is also a function of the transistor properties and the operating voltage, and is given by:

_{n}and C

_{n}are device dependent parameters; and V

_{th}is the transistor threshold voltage.

_{optimum}, that can be obtained by solving dE/dT = 0, and an optimum voltage equal to 3 V

_{th}. This optimum is visible in the energy-performance plot shown in Figure 3.

#### 3.2. Sub-Threshold CMOS Circuits

_{t}the thermal voltage.

**Figure 3.**Comparison between the performance of adiabatic circuits using: conventional CMOS (solid red line) as given by Equation (2), and sub-threshold CMOS (dashed blue line) as given by Equation (7), both done for the same device parameters. The non-adiabatic residue in classical CMOS circuit is also shown for comparison (solid black line).

## 4. NEMS-Based Adiabatic Logic Circuits

_{pi}), is larger than the voltage at which the structure breaks contact, known as the pull-out voltage V

_{po}. In case the contact is established before the onset of pull-in, i.e., , then there is only a contact voltage V

_{contact}= V

_{pi}= V

_{po}.

_{Total}in a NEMS-based adiabatic circuit may be expressed as:

_{Total}= E

_{Electrical}+ E

_{Mechanical}

_{Electrical}and E

_{Mechanical}are the energy dissipated by the electrical resistance and the energy dissipated through mechanical damping respectively. While the mechanical energy dissipation may depend on the ramp period T, it will be considered as a constant second order residue throughout this work.

_{Electrical}may be expressed as:

_{1}and i

_{2}are the currents going through the series resistance R

_{S}, the load capacitance C

_{L}and NEMS capacitance C

_{S}respectively, as shown in Figure 1. An expression for the current in each branch may be derived as follows:

_{S}and the time-dependent capacitance value of the NEMS switch . Furthermore, the minimum values of V

_{dd}and T are set by the switch and therefore also dependent on the NEMS device.

**Figure 4.**Schematic illustration of a reduced order model of a nanoelectromechanical switch (

**a**) showing the source (S), drain (D) and gate (G). Also visible are the actuation and contact gaps, g and d respectively; V and I represent the actuation voltage and the source-to-drain current respectively; and ϕ represents the power clock signal; (

**b**) Typical I-V plots in a NEMS switch operating in the pull-in mode, where Isat represents the saturation current of the device.

#### 4.1. Contact Resistance in Nanomechanical Switches

_{applied}will be used.

_{H}of the circular contact spot between two asperities shown schematically in Figure 5, is given by:

_{1}R

_{2}/(R

_{1}+ R

_{2}) where R

_{1}and R

_{2}are the radii of the first and second asperities respectively; and E

^{*}is the effective elastic modulus given by , where E

_{1}, ν

_{1}, E

_{2}, ν

_{2}, are the Young moduli and Poisson ratios of the first and second asperities respectively.

_{applied}applied to the contacting asperities may be expressed as:

_{0}is the minimum electrostatic contact force when V

_{dd}= V

_{pi}, and α represents the restoring elastic force; the exact values of both F

_{0}and α depend on the device design and fabrication. Note that Equation (12) only applies once contact is established, i.e., V

_{dd}≥ V

_{contact}, regardless of whether the switch is operating in the pull-in or non-pull-in regimes.

_{JKR}is the contact radius for a JKR type contact, R and K take the same values as expressed previously, and Δγ is the net adhesion energy between the two surfaces.

_{Maxwell}) in the diffusive transport regime, and Sharvin (R

_{Sharvin}) in the ballistic transport regime are respectively expressed as:

_{e}is the electron mean free path.

**Figure 5.**Schematic illustration of two asperities in contact, deformed under the effect of an applied load.

#### 4.2. Switching Behavior of Nanomechanical Switches

_{S}, is inversely proportional to the time-dependent position X(t) of the movable mass, as given by the parallel plate capacitor value:

_{0}as the NEMS switch capacitance in the initial position, i.e., for X = 0.

_{Mech}), the electrical time constant (τ

_{Elec}), and the rise time of the clock signal (T).

_{Mech}>> T >> τ

_{Elec}): in this scenario, that we will also refer to as “dynamic mode”, the electric time constant is considered to be several orders of magnitude smaller than the mechanical time constant. The rise time of the clock signal is also much smaller than the mechanical time constant, such that from a mechanical point of view, the voltage would be ramped up to its hold value of V

_{dd}, before the mechanical structure even begins to move. Therefore, the structure responds in a manner that is similar to that when subjected to a step voltage. The net effect of this form of operation is to have a hold time that is significantly longer than the rise time, as shown in Figure 6.

_{Mech}, the switch capacitance is assumed to be a time-independent constant equal to C

_{0}. While the second term represents the effect of a varying switch capacitance, which takes place upon mechanical commutation, under the effect of the now stable bias voltage V

_{dd}. For each of these terms, the currents are defined differently, given by:

_{0}is the mechanical resonance frequency of the spring-mass system that models the NEMS switch. The ramp subscript is meant to represent the dissipation during the ramp-up and ramp-down phases of the power clock cycle.

**Figure 6.**Schematic representation of the necessary clock signal for NEMS-adiabatic circuits working in the limit of (τ

_{Mech}>> T >> τ

_{Elec}) with the hold phase lasting longer than the ramp-up and ramp-down phases. Also shown in the figure is the required synchronization between two phase clocks.

_{Mech}>> τ

_{Elec}): another limit case to consider is when the rise time of the clock signal is slow compared to the mechanical time constant: therefore, the mechanical structure is assumed to move slowly. We will refer to this case as the “quasi-static mode”. Both the power clock rise time and the mechanical time constant are considered to be significantly longer than the electrical time constant.

_{0}, where Q is the mechanical quality factor, a solution based on static equilibrium equations is considered to be a good approximation. Such a solution is explicitly derived in [19], and gives an expression for the total energy dissipation as:

## 5. Results and Discussion

_{0}V

_{dd}². The energy dissipation curves are calculated for C

_{L}= 10C

_{0}, a value chosen by industry standards [20]. Additionally, the contact gap to electrostatic gap ratio is taken to be d/g = 2/3. The horizontal axis of the graph in Figure 7 represents the operating frequency of the circuit normalized to the nominal resonance frequency of the NEMS structure.

**Figure 7.**Comparison of the performance of NEMS-based adiabatic circuits shown for: the dynamic mode of operation (black line) as given by Equation (18a–c), and the quasi-static mode of operation (red line) as given by Equation (20), both done for d/g = 2/3, and C

_{L}= 10C

_{0}.

^{2}[15], electrical resistivity and electron mean free path of gold are ρ = 22 × 10

^{−9}Ω·m, and λ

_{e}= 38 nm respectively.

**Figure 8.**Plots of the contact resistance, described by Equations (11–14b), given by the different models on the performance of NEMS-based adiabatic circuits operating in the dynamic mode. The quasi-static mode is similarly affected (not shown) by the value of contact resistance values.

_{dd}> V

_{pull-in}, does not interfere with the proper operation of the circuit provided that the different phases of the power clock are well synchronized, and that is the case for both “dynamic mode” and “quasi-static mode”. This is because if the second power clock phase does not commence until the first one has started its hold value, the switch will already be in the close or open position (depending on the state) regardless of the supply voltage (as long as that is at least equal to the pull-in voltage) which is the purpose in exploring these limit case scenarios.

**Figure 9.**Plots comparing the performance of the classical (black) and sub-threshold (blue) CMOS adiabatic logic circuits (for 45 nm technology node and a 1fF load capacitance), and the performance of a NEMS-based adiabatic logic circuit (also with a 1fF load capacitance).

## 6. Conclusions

## Acknowledgments

## Conflicts of Interest

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**MDPI and ACS Style**

Houri, S.; Poulain, C.; Valentian, A.; Fanet, H.
Performance Limits of Nanoelectromechanical Switches (NEMS)-Based Adiabatic Logic Circuits. *J. Low Power Electron. Appl.* **2013**, *3*, 368-384.
https://doi.org/10.3390/jlpea3040368

**AMA Style**

Houri S, Poulain C, Valentian A, Fanet H.
Performance Limits of Nanoelectromechanical Switches (NEMS)-Based Adiabatic Logic Circuits. *Journal of Low Power Electronics and Applications*. 2013; 3(4):368-384.
https://doi.org/10.3390/jlpea3040368

**Chicago/Turabian Style**

Houri, Samer, Christophe Poulain, Alexandre Valentian, and Hervé Fanet.
2013. "Performance Limits of Nanoelectromechanical Switches (NEMS)-Based Adiabatic Logic Circuits" *Journal of Low Power Electronics and Applications* 3, no. 4: 368-384.
https://doi.org/10.3390/jlpea3040368