# A Low-Power, 65 nm 24.6-to-30.1 GHz Trusted LC Voltage-Controlled Oscillator Achieving 191.7 dBc/Hz FoM at 1 MHz

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## Abstract

**:**

_{T}) reaches 197.6 dBc/Hz and 205.0 dBc/Hz at 1 MHz and 10 MHz offset, respectively. The analog PUF consists of CMOS cross-coupled pairs in the main VCO to change analog characteristics. Benefiting from the impedance change and parasitic capacitance of the cross-coupled pairs, the AC and DC responses of the VCO are utilized for multiple responses for each input. The PUF consumes 0.83 pJ/bit when operating at 1.5 Gbps. The proposed PUF exhibits a measured Inter-Hamming Distance (HD) of 0.5058b and 0.4978b, with Intra-HD reaching 0.0055b and 0.0053b for the current consumption and f

_{osc}, respectively. The autocorrelation function (ACF) of 0.0111 and 0.0110 is obtained for the current consumption and f

_{osc}, respectively, at a 95% confidence level.

## 1. Introduction

_{osc}, amplitude, and PN, resulting in increased entropy with the same number of challenges. The remainder of this paper is structured as follows. Section 2 describes the threat model and provides more details on the design of the embedded analog PUF. The proposed low-power trusted LC VCO design is presented in Section 3 and is followed by the characterization results in Section 4. Section 5 provides the concluding remarks.

## 2. RFFE Threats and Embedded Analog PUF Design

#### 2.1. Security Threats in RFFEs

#### 2.2. Embedded Analog PUFs for RFFEs

_{osc}are sensitive to process artifacts and parasitics, and, hence, can be used for authentication. By adding additional cross-coupled pairs whose device sizes are slightly different than the main pair, in parallel to the main CMOS cross-coupled pair, the VCO current consumption changes (Figure 2b). The additional parasitic capacitance from the cross-coupled pair also causes a shift in the f

_{osc}. By adjusting the gate-source voltage (V

_{GS}) in each pair or adding multiple pairs with different W/L, the variation in the current consumption and f

_{osc}can be controlled, creating a proper CRP space for authentication. The additional cross-coupled pairs can be turned off so as to not impact the performance of the VCO during the normal operation of the VCO. This is easily performed by pulling up or down the gate voltages for the PMOS and NMOS pairs, respectively. Unlike conventional PUFs, where the input and output vectors have similar dimensions, here, each challenge vector generates multiple response vectors, of which the current consumption and f

_{osc}are used in this proof-of-concept prototype. The proposed prototype uses 64 challenges (six bits: 3-bit NMOS and 3-bit PMOS), resulting in 128 (2

^{7}) output responses (Figure 2c). Responses of the 6-bit challenges are analog values but they are digitized for PUF characterization and analysis. In this work, responses are converted into codewords for PUF characterization and analysis. The codeword generation from responses is discussed as part of the PUF characterization efforts discussed in Section 4.

## 3. Design of the Trusted CMOS LC VCO

_{D}) because it determines the mode of operation, i.e., the voltage-limited or current-limited regime [17,18]. In addition to the g

_{m}of the NMOS and PMOS cross-coupled pairs, the LC tank plays a key role in the power consumption, PN, and TR performance of an LC VCO, requiring a careful design of tank components, particularly the inductance [17,18,19]. Knowing that the PN is proportional to (L

_{tank})

^{2}[19], a small inductance with the highest quality factor (Q) is chosen for the tank. Moreover, the TR is inversely proportional to the L

_{tank}, further incentivizing the use of a small inductor. To further increase the inductor Q and save chip area, the VCOs use differential inductors with a floating center tap [19]. The 420 pH inductor designed for the CVCO exhibits a Q~15 at 28 GHz with 69.2 GHz self-resonance frequency (SRF), while the 315 pH inductor designed for the trusted VCO (Figure 3) shows Q~17.2 at 28 GHz with SRF > 80 GHz. The trust features are embedded within the VCO as six cross-coupled pairs, three NMOS and three PMOS. These additional cross-coupled pairs are only used for authentication; they are turned off during the normal operation of the VCO and primarily act as parasitic capacitance in this mode.

_{m}). Then, the trust features that can be embedded into the VCO core are identified. An important consideration for the design of the embedded PUF is the compatibility of the PUF architecture with the VCO core architecture without a significant hit to the power consumption and size of the VCO. At the same time, the PUF should generate the required entropy for the authentication process [10]. For this design, a cross-coupled PUF topology, which relies on the variation in the impedance, is utilized to generate the change in the current consumption and the oscillation frequency as the unique identifiers for the authentication process. During the normal operation, the trust features are disabled, leaving only the main cross-coupled pair active, which resembles a conventional CMOS LC VCO. In this case, the VCO core design procedure will be straightforward. The cross-coupled pair generates the required G

_{m}to compensate for the loss of the LC tank (modeled by R

_{p}). The oscillation frequency, ω, is set by the tank as follows:

_{m}is the total transconductance in the system that is equal to the transconductance of a CMOS device (g

_{m}), ${R}_{P}$ is equivalent parallel resistance of the LC tank used in the VCO, ${C}_{T}$ is the total equivalent capacitance of the tank, ${C}_{in}$ is the total parasitic capacitance from a cross-coupled pair, ${C}_{V}$ is the capacitance from tuning varactors, C

_{pd}is the parasitic capacitance from the inactive cross-coupled pairs used for the PUF, ${C}_{Pa}$ is the parasitic capacitance from the active cross-coupled pairs used for the PUF, ${C}_{VCO}$ is the parasitic capacitance from the CMOS devices that is equal to ${C}_{GS}+4{C}_{GD}$, and ${C}_{GS}$ and ${C}_{GD}$ are the gate-source and drain-source MOS capacitance of the CMOS device. In this design, the power consumption is reduced by increasing the Q of the inductor to generate a larger R

_{p}, leading to a smaller required G

_{m}for oscillation. Moreover, the stacked combination of NMOS and PMOS pairs used in the VCO core and the PUF allows for reusing the current from the PMOS into the NMOS pair, generating larger overall G

_{m}without increasing the current consumption. When the VCO operates in authentication mode, additional cross-coupled pairs are enabled. Consequently, the current consumption and the frequency are lowered due to larger parasitic capacitance from these pairs.

_{osc}when the temperature is varied from −40 °C to 85 °C for the first challenge, 000000, and the last challenge, 111111. The changes to the current consumption are reasonable and follow the MOS threshold variation with temperature. Since the change in current consumption is almost linear, it can be easily compensated for using adaptive biasing (i.e., changing the supply with temperature) or calibrated out in post-measurement calculations. The changes to the f

_{osc}are very small (<±0.1%), as expected, since f

_{osc}is mainly determined by the frequency of the LC tank whose variations with temperature are negligible. Expecting a unique response for each input challenge, the accuracy of the analog PUF should be investigated. The amount of mismatch and its impact on the PUF resolution can be found by performing post-layout Monte Carlo (MC) simulations on the trusted VCO when the embedded analog PUF is turned on.

_{osc}at −40 °C, 27 °C (room temperature), and 85 °C for the first challenge, 000000. As expected, the PDF of the output results resembles those of a Gaussian/normal function for all three temperatures. For a 200-sample MC simulation, the current consumption and f

_{osc}show reasonable variations with the standard deviation (σ)~67 µA and ~15 MHz at 27 °C (Figure 5). The PDF also remains close to Gaussian when temperature changes with σ for the current consumption and f

_{osc}~70 µA and ~14 MHz at −40 °C, and ~63 µA and ~22 MHz at 85 °C, respectively. The MC simulations are repeated for the last challenge, 111111, showing a similar Gaussian/normal behavior (Figure 6). The MC results are then used to evaluate the randomness of the proposed PUF using the Hamming Distance (HD) function, which is a metric to show the difference between two data strings. There are two HD measurements: Intra-HD and Inter-HD. Intra-HD measures the randomness of a single PUF design (or a single chip) when one bit of the input challenge changes, while the Inter-HD demonstrates the randomness between different PUF designs (or different chips) when the same challenge is applied to the PUFs. For each challenge, a single MC simulation can be used to find Inter-HD since MC simulations based on the device mismatch show the PUF output difference between different samples (i.e., dies). Ideally, the Intra-HD and Inter-HD of a PUF should be 0 and 0.5, respectively. Simulating Intra-HD in an ideal simulation environment where circuit parameters, the supply voltage, biasing, and output load do not experience any variation during the simulation is very challenging since the simulator only uses the mathematical models for the analysis. To emulate a realistic environment for Intra-HD simulations, reasonable uncertainty is added to the test bench by adding randomness to the DC sources and temperature. The DC sources used in the test bench are randomly varied by considering ±5 mV error. This is consistent with testing conditions in our lab where the DC voltages are set manually. In addition to variations of the DC voltages, the temperature randomly varied from room temperature by ±1 °C (from 26 °C to 28 °C) to emulate fluctuations in the room temperature during the measurement. Figure 7a–f show the Inter-HD and Intra-HD results for the current consumption and f

_{osc}at −40 °C, 27 °C, and 85 °C based on the 200-sample post-layout MC simulations. Since the PDF of the current consumption and f

_{osc}are reasonably close to Gaussian for both challenges, as shown in Figure 5 and Figure 6, the Inter- and Intra-HD results are only presented for the first challenge, 000000. Ideally, Inter-HD for PUFs should be 0.5 and Intra-HD should be 0 [10,11,12,13,14,15]. The challenge for defining Inter-HD and Intra-HD is to create accurate and reliable bit representations (i.e., codeword) for responses. Codeword generation for this work is based on the Huffman coding algorithm [20] and will be discussed in more detail in Section 4. Using these codewords, the Inter-HD of the simulated responses are 0.4997 at −40 °C, 0.4995 at 27 °C, and 0.5004 at 85 °C for the current consumption, and 0.5010 at −40 °C, 0.4991 at 27 °C, and 0.5090 at 85 °C for f

_{osc}, respectively. The Intra-HD of the simulated responses are 0.0107 at −40 °C, 0.0085 at 27 °C, and 0.0092 at 85 °C for the current consumption, and 0.0036 at −40 °C, 0.0029 at 27 °C, and 0.0043 at 85 °C for f

_{osc}, respectively. Both simulated Intra- and Inter-HD are very close to the ideal values for a PUF.

## 4. Measurement Results

#### 4.1. VCO Performance Measurement and Comparison

_{DD}) is raised to 0.8 V with the power consumption (P

_{DC})~0.72 mW. For P

_{DC}~1.75 mW, the output power is increased to −9.7 dBm and the VCO exhibits a TR ≈ 5.5 GHz (Figure 9a), from ≈24.6 GHz to 30.1 GHz. Under such conditions, the PN measures better than −104.8 dBc/Hz and −132.2 dBc/Hz at 1 MHz and 10 MHz offset, respectively (Figure 9b), when the frequency is tuned to the upper end of the range (≈29.3 GHz). These results correspond to FoM~191.7 dBc/Hz and ~199.1 dBc/Hz @1MHz and @10MHz, respectively. When TR is considered, the FoM

_{T}of ~197.6 dBc/Hz and ~205 dBc/Hz are obtained at 1 MHz and 10 MHz, respectively. On the other hand, the CVCO sustains oscillation when the supply voltage (V

_{DD}) is raised to 0.8 V with the power consumption (P

_{DC})~0.6 mW. For P

_{DC}~1.5 mW; the output power is increased to −10.1 dBm, and it exhibits a frequency tuning range (TR) of ≈6.1 GHz, from ≈25 GHz to 31.1 GHz (Figure 9a). Under such conditions, the PN measures better than −101.1 dBc/Hz and −130.4 dBc/Hz at 1 MHz and 10 MHz offset, respectively (Figure 9b), when the frequency is tuned to the upper end of the range (≈29.6 GHz). The CVCO PN results correspond to FoM~188.7 dBc/Hz and ~198 dBc/Hz @ 1 MHz and @ 10 MHz, respectively. When TR is considered, the FoM

_{T}of ~194.7 dBc/Hz and ~204 dBc/Hz are obtained at 1 MHz and 10 MHz, respectively. These results clearly show that the proposed trusted VCO exhibits similar performance (esp. PN), if not better, when compared against the CVCO under a similar power consumption.

_{offset}< 1 MHz) in the proposed trusted VCO compared to the CVCO requires a more detailed analysis.

^{3}and 1/f

^{2}regions. Considering this time variant PN model [21], calculating the change in the Impulse Sensitivity Function (ISF), which is a periodic and dimensionless function, is necessary [21]. Since the ISF is periodic, it can be represented by Fourier coefficients as follows:

_{n}) are real values and θ

_{n}is the phase of the nth harmonic. θ

_{n}is small and can be ignored at random input noise [21], and the coefficients can be estimated analytically or calculated from the simulation. Given its similarities with the ISF, the Perturbation Projection Vector (PPV), which represents the sensitivity of the per cycle jitter variance to current perturbations at the nodes of the oscillator [23], can be used to estimate the ISF changes [21,22,23]. PPV results can be obtained via periodic simulations. Figure 10 gives the PPV results obtained from Cadence Harmonic Balance (HB) and HB noise simulations for both VCOs. HB PPV results are shown in V and HB noise PPV results are shown in 1/V. Then, the PN of the LC VCO can be expressed as follows [24,25]:

_{max}is the maximum charge displacement across the equivalent output capacitance where the impulse was injected, i.e., q

_{max}= V

_{max}C (V

_{max}is the maximum voltage swing at the output). ${\mathsf{\Gamma}}_{id,rms}^{2}$ is the ISF from active devices and can be expressed in several forms, e.g., ${\mathsf{\Gamma}}_{id,rms}^{2}=2{V}_{TH}^{2}/\pi {V}_{max}^{2}$ [24] or ${\mathsf{\Gamma}}_{id,rms}^{2}=2{I}_{DS}/\pi \beta {V}_{max}^{2}$ [25], where β = µ

_{e}C

_{ox}W/L, µ

_{e}is the electron mobility, C

_{ox}the gate oxide capacitance per unit area, and W and L are the transistor width and length, respectively. ${\mathsf{\Gamma}}_{R,rms}^{2}$ is the ISF from the thermal noise source of the oscillator (R), which is mostly produced by the tank. It is assumed to be 1/2 for single-ended output and 1/8 for differential outputs [25]. $\overline{{i}_{d}^{2}}/\Delta f$ is the power spectral density of active devices’ noise current. The portion associated with the thermal noise can be expressed as $\overline{{i}_{d,thermal}^{2}}/\Delta f=4kT\gamma \beta {V}_{max}$, where k is the Boltzmann constant, $\gamma $ is the fitting parameter, and T is the temperature as Kelvin. In most cases, $\beta {V}_{max}\approx {g}_{m}$ of the device. The portion associated with the flicker noise can be expressed as $\overline{{i}_{d,flicker}^{2}}/\Delta f={K}_{F}{g}_{m}^{2}/({C}_{OX}.W.L.\Delta f)$, where ${K}_{F}$ is the flicker noise fitting parameter. $\overline{{i}_{R}^{2}}/\Delta f$ is the power spectral density of the thermal noise current due to R and can be expressed as $\overline{{i}_{R}^{2}}/\Delta f=4kT/R$. Equation (6) includes the thermal and flicker noise sources [19,21,22,23,24,25,26,27,28,29,30] for both active and passive devices in the VCO. Since the flicker and thermal noises of MOS devices are considered uncorrelated, their impact on the PN can be studied separately, and the results can be superimposed [22]. Knowing that flicker noise is dominant at low offset frequencies, the impact of the flicker noise on the PN should be studied in more detail. Hajimiri et al. [21] expresses the flicker noise-dominant region of the PN (i.e., 1/f

^{3}region) in terms of the 1/f noise corner, ω

_{1/f}. In this case, the 1/f

^{3}corner frequency, ${\omega}_{1/{f}^{3}}$, can be expressed as follows:

^{3}corner frequency, ${\omega}_{1/f}$ is 1/f corner frequency, and ${\Gamma}_{DC}$ and ${\Gamma}_{rms}$ are DC and root mean square (RMS) values of the ISF coefficients, respectively. Using (7), the flicker noise-dominant portion of the PN can be expressed as follows:

_{DC}, and $\overline{{i}_{n}^{2}}/\Delta f$ is the total noise current, $\overline{{i}_{R}^{2}}/\Delta f+\overline{{i}_{d}^{2}}/\Delta f$. At low offset frequencies, the flicker noise will be dominant; hence, $\overline{{i}_{n}^{2}}/\Delta f$ can be expressed as ${K}_{F}{g}_{m}^{2}/({C}_{OX}.W.L.\Delta f)$. Knowing the flicker and thermal noise of the MOS devices and the tank, the flicker noise- and thermal noise-dominant portions of the PN can be derived separately as follows [31,32,33]:

_{DD}is the RMS current consumption of the VCO. Superimposing (9) to (10) leads to a simplified PN expression that covers both the flicker noise- and thermal noise-dominant regions of the PN as follows:

_{0}obtained from the HB noise simulation is 1.085 1/V and −1.44 1/V for the differential outputs of the CVCO and 0.36 1/V and −0.19 1/V for the differential outputs of the trusted VCO, respectively (Figure 10). Utilizing HB simulations reveals Γ

_{0}~−0.16 V and 0.14 V for the differential outputs of the CVCO and ~0.0049 V and 0.058 V for the differential outputs of the trusted VCO, respectively (Figure 10). The minimum ratio between Γ

_{0}for two VCOs is ~2.4×, which amounts to a ~7 dB improvement in the close-in PN for the trusted VCO. Additionally, the trusted VCO exhibits larger q

_{max}compared to the CVCO due to larger parasitic capacitors from the additional cross-coupled pairs and the resulting on-chip metal wiring. This larger q

_{max}further improves the close-in PN performance of the proposed trusted VCO. The measured PN results presented in Figure 9 reveal up to a 9 dB improvement in the PN at 100 kHz offset for the trusted VCO compared to the CVCO. As the frequency increases, the effect of flicker noise diminishes, and the thermal noise of active devices and the Q of the LC tank become the dominant factor affecting the PN [18]. In this region, the PN can be better modeled with (11). Considering (11), it is evident that the difference between the PN of two VCOs gradually narrows until it becomes negligible at high offset frequencies near the PN floor. To conclude this study, the performance of the trusted VCO is summarized and presented in Table 1. Compared with the state-of-the-art VCOs [26,27,28,29] operating in a similar frequency range and built with the 65 nm CMOS process, the proposed trusted VCO exhibits competitive FoMs while consuming lower power.

#### 4.2. PUF Characterization and Randomness Analysis

_{osc}for a trusted VCO chip operating under V

_{DD}= 1.2 V at room temperature (27 °C). Since the current consumption and f

_{osc}are directly affected by the device size, which follows the near-Gaussian mismatch profile of CMOS devices, a normal distribution is expected. To perform HD analysis, the measured current consumption and f

_{osc}should be converted to binary strings. The conversion is customized considering the accuracy of the measurement equipment and biasing (which sets the minimum resolution) and the variation range of the measured parameters (current consumption and f

_{osc}). In this work, measurement devices have 1 MHz and 1 µA accuracy. However, the accuracy of biasing voltage sources used for the challenge pairs is ~10 mV and, hence, sets the minimum resolution for the responses. During the authentication, each challenge input based on the

**“C**codeword produces its own unique response as current consumption and f

_{N3}C_{N2}C_{N1}C_{P3}C_{P2}C_{P1}”_{osc}. Knowing that the length of the output bit string should be equal to or greater than that of the challenge codeword [20], a lower bound (six bits) on the length of the bit string is found. However, accurate conversion of the output analog response to bit strings is a challenge for this work since multiple outputs are generated for each challenge input. Unlike most analog PUFs [10,11,12,13,14,15], setting a fixed decision threshold is difficult for all chips given normal PVT variations affecting the high-frequency path. As such, the soft decision technique [12] is used for output bit string generation before the HD analysis.

_{osc}(i.e., the AC response) varies from ~29 GHz to ~29.4 GHz, respectively. Then, the weight of each digit in the decimal number is considered. Knowing the accuracy of the measurement equipment, both current (in mA) and f

_{osc}(in GHz) readings can be expressed with three decimal digit accuracy, i.e., A.XYZ for current and BC.TVU for frequency. A level change for the current response can be 2 or 3, other level changes can be from 0 to 9, indicating that the changes have an unequal impact on the response. In such conditions, coding theory approaches, such as Huffman coding [20], where higher probability represents fewer bits and vice versa, are desired. Due to the limited accuracy of the biasing network (~10 mV), the least significant digits, i.e., Z and U, require soft decision thresholds. Finally, the proposed customized coding can be expressed as 1-bit for A, 4-bit for X, 4-bit for Y, 1-bit for Z, 1-bit for B, 1-bit for C, 3-bit for T, 4-bit for V, and 1-bit for U. The result will be two 10-bit codewords, one for the current consumption response and the other for f

_{osc}. Using this customized code, a sample set consisting of eight dies operating under similar conditions (V

_{DD}= 1.2 V and T ≈ 27 °C) is evaluated for Inter-HD and Intra-HD analyses (Figure 12). The measured average Inter-HD of the current consumption and f

_{osc}are ~0.5058b and 0.4978b, respectively, which are very close to the ideal value of 0.5b. Similarly, the measured average Intra-HD of the current consumption and f

_{osc}are 0.0055b and 0.0053b, respectively, which are very close to the ideal value of 0, demonstrating acceptable randomness for the proposed analog embedded PUF.

_{osc}, which make up the output responses to each challenge. To compute ACF, a stochastic time series of measured responses is created since the ACF aims to detect the correlation between two random responses in a sample set. To this end, 40K responses are gathered for each output to create the required stochastic time series for the eight chips. Then, the ACF of both 40K sample sets, one for current consumption and the other for f

_{osc}, is calculated when considering 10K lags (Figure 13). The ACF of the responses for the current consumption and f

_{osc}at a 95% confidence level are 0.0111 and 0.0110, respectively, which are very close to the ideal value of zero, demonstrating a desired level of randomness for the proposed PUF (Table 2).

_{settling}is the slowest settling time from the first challenge to the last challenge (i.e., ~4 ns for the proposed PUF). Such a high data rate allows for reducing the time needed for the authentication process and reducing the unwanted latency when trying to establish a trusted data link. Using (12), the energy per bit can be calculated by subtracting the VCO power during the authentication with the one during the normal operation (i.e., challenge set to 000000), revealing a competitive performance compared to the state-of-the-art (Table 2). The very high data rate achieved for the proposed embedded PUG along with its low power consumption allows for delivering an energy/bit as low as 0.83 pJ, which is comparable to the state-of-the-art PUFs [12,14,15] implemented in a similar CMOS technology. Moreover, the larger CRP size made available by the generation of multiple outputs for a single challenge has created a relatively compact design compared to other analog PUFs implemented in similar CMOS process nodes, making the design well-suited for integration with communication transceivers.

## 5. Conclusions

_{T}reaches 197.6 dBc/Hz and 205.0 dBc/Hz @ 1 MHz and @ 10 MHz, respectively. The embedded PUF consumes as low as 0.83 pJ/b and is capable of running at 1.5 Gb/s. It exhibits sufficient uniqueness with the measured Inter-HD of 0.5113b and 0.489b and measured Intra-HD of 0.0055b and 0.0053b for the current consumption and f

_{osc}, respectively. Moreover, an ACF of 0.0111 and 0.110 is achieved for the current consumption and f

_{osc}responses of the proposed PUF, respectively, at a 95% confidence level. Compared with the state-of-the-art LC VCOs operating in the same frequency range, the proposed trusted VCO shows competitive performance at lower power with added device security and authentication features.

## Author Contributions

## Funding

## Data Availability Statement

## Conflicts of Interest

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**Figure 2.**Block diagram of the proposed design showing (

**a**) the PUF concept, (

**b**) the VCO schematic, and (

**c**) the CRP mechanism.

**Figure 4.**Changes to the normalized (

**a**) current consumption (red) and (

**b**) f

_{osc}for the first challenge (blue), 000000, when the temperature is varied; a similar trend is observed for (

**c**) current consumption (red) and (

**d**) f

_{osc}(blue) for the last challenge, 111111.

**Figure 5.**PDFs of the current consumption and f

_{osc}of the proposed trusted VCO for the first challenge, 000000; PDF of the current consumption (red) at (

**a**) −40 °C, (

**b**) 27 °C, (

**c**) 85 °C, and PDF of f

_{osc}(blue) at (

**d**) −40 °C, (

**e**) 27 °C, (

**f**) 85 °C.

**Figure 6.**PDFs of the current consumption and f

_{osc}of the proposed trusted VCO for the last challenge, 111111; PDF of the current consumption (red) at (

**a**) −40 °C, (

**b**) 27 °C, (

**c**) 85 °C, and PDF of f

_{osc}(blue) at (

**d**) −40 °C, (

**e**) 27 °C, (

**f**) 85 °C.

**Figure 7.**Intra-HD, and Inter-HD of the proposed trusted VCO for the current consumption at (

**a**) −40 °C, (

**b**) 27 °C, and (

**c**) 85 °C, along with those of f

_{osc}at (

**d**) −40 °C, (

**e**) 27 °C, and (

**f**) 85 °C for the first challenge, 000000.

**Figure 8.**Intra-HD micrographs of the (

**a**) proposed trusted VCO and (

**b**) CVCO dies alongside (

**c**) the measurement bench.

**Figure 9.**(

**a**) TR and (

**b**) PN comparison of the trusted VCO with the CVCO. The spectrum of the trusted VCO is also shown.

**Figure 10.**PPV results: HB noise results for (

**a**) the CVCO and (

**b**) trusted VCO; HB results for (

**c**) the CVCO and (

**d**) trusted VCO.

**Figure 12.**Measured Intra- and Inter-HD of the (

**a**) current consumption (

**a**) and (

**b**) f

_{osc}of the trusted VCO for eight dies.

**Figure 13.**Autocorrelation of the 40K sample set with 10K lags: (

**a**) current consumption, (

**b**) f

_{osc}responses.

**Figure 14.**Transient simulation results of the trusted VCO showing the settling time when input challenge changes criterion and the number of bits for each symbol.

This Work (CVCO/Trusted VCO) | [26] | [27] | [28] | [29] | |
---|---|---|---|---|---|

P_{DC} (mW) | 1.5/1.75 | 3.4 | 3.8 | 7.2 | 3.8 |

f_{osc} (GHz) | 29.6/29.3 | 27.45 | 25.48 | 28.11 | 19.7 |

Tuning Range (GHz) | 25–31.2/24.6–30.1 | 26.1–29.9 | 25.48–29.92 | 28.11–31.46 | 19.3–22.0 |

PN@1MHz (dBc/Hz) | −101/−104.8 | −105.7 | −109.3 * | −107.2 | −106.33 |

PN@10MHz (dBc/Hz) | −130.4/−132.2 | −127.5 | −128 * | −123 ^{#} | −127.82 |

FoM@1MHz (dBc/Hz) | 188.7/191.7 | 189.1 | 191.6 | 187.6 | 186.4 |

FoM_{T}@1Mz (dBc/Hz) | 194.7/197.6 | 191.7 | 195.7 | 189.13 | 188.8 |

FoM@10MHz (dBc/Hz) | 198/199.1 | 191 | 190.3 | N/A | N/A |

FoM_{T}@10Mz (dBc/Hz) | 204/205 | 193.4 | 194.4 | N/A | N/A |

Core Area (mm^{2}) | 0.018/0.018 | 0.038 | 0.08 | 0.11 | 0.064 |

Technology | 65 nm/65 nm | 65 nm | 65 nm | 65 nm | 65 nm |

This Work | [12] | [14] | [15] | |
---|---|---|---|---|

Technology | 65 nm | 65 nm | 65 nm | 55 nm |

PUF type | Weak | Weak | Weak | Weak |

Chip area | 594 um^{2} | 40,000 um^{2} | 37,511 um^{2} | 997 um^{2} |

CRP space | (64,2) | (16,8) | (16,20) | (128,1) |

Entropy Source | Capacitance and Impedance mismatch | Process variation | Impedance mismatch | Process variation |

Bit rate | 1.5 Gbps | 100 Mbps | 320 Kbps | 40 Kbps |

ACF | 0.0111/0.0110 | 0.0108 | 0.0123 | 0.0142 |

Energy/bit | 0.83 pJ | 0.36 pJ | 6 pJ | 0.91 pJ |

Intra-HD | 0.0055/0.0054 | 0.0906 | 0.0031 | N/A |

Inter-HD | 0.5113/0.4892 | 0.4859 | 0.4986 | 0.4681 |

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## Share and Cite

**MDPI and ACS Style**

Kurtoglu, A.; Shirazi, A.H.M.; Mirabbasi, S.; Miri Lavasani, H.
A Low-Power, 65 nm 24.6-to-30.1 GHz Trusted LC Voltage-Controlled Oscillator Achieving 191.7 dBc/Hz FoM at 1 MHz. *J. Low Power Electron. Appl.* **2024**, *14*, 10.
https://doi.org/10.3390/jlpea14010010

**AMA Style**

Kurtoglu A, Shirazi AHM, Mirabbasi S, Miri Lavasani H.
A Low-Power, 65 nm 24.6-to-30.1 GHz Trusted LC Voltage-Controlled Oscillator Achieving 191.7 dBc/Hz FoM at 1 MHz. *Journal of Low Power Electronics and Applications*. 2024; 14(1):10.
https://doi.org/10.3390/jlpea14010010

**Chicago/Turabian Style**

Kurtoglu, Abdullah, Amir H. M. Shirazi, Shahriar Mirabbasi, and Hossein Miri Lavasani.
2024. "A Low-Power, 65 nm 24.6-to-30.1 GHz Trusted LC Voltage-Controlled Oscillator Achieving 191.7 dBc/Hz FoM at 1 MHz" *Journal of Low Power Electronics and Applications* 14, no. 1: 10.
https://doi.org/10.3390/jlpea14010010