#
A Time-Mode PWM 1st Order Low-Pass Filter^{ †}

^{*}

^{†}

^{−1}Implementation. In Proceedings of the 2022 6th Panhellenic Conference on Electronics and Telecommunications (PACET), Tripolis, Greece.

## Abstract

**:**

## 1. Introduction

_{in}into a time-mode signal T

_{in}[4,5]. The VTC consists of a sample-and-hold circuit that samples the continuous voltage signal with a sampling period T

_{s}and a pulse-width modulator that converts every voltage sample into a rectangular pulse. The input signal of the time-mode unit will actually be a pulse train in which every pulse will have the same frequency as the sampling signal, but the pulse width will be equal to a linear function of the corresponding voltage sample. After the conversion, the information is processed in the time mode. The time-mode processing unit could include many simple operations like a z

^{−1}operation, addition, subtraction, amplification [6], or multiplication [7,8]. Furthermore, a combination of these simple operations can be achieved if more complex processing is needed (e.g., time-mode filtering [9,10,11] and time-mode integrators [12,13,14]). Finally, the processed time-mode signal is converted back to the voltage mode via a time-to-voltage converter (TVC). It should be mentioned that the processed time-mode information can be quantized via a time-to-digital converter (TDC) if further processing is needed by a digital signal processing unit [15,16,17].

^{−1}operator and a z

^{−1}weighted time-mode adder with gain ½. All the building blocks of the z

^{−1}operator and the weighted time adder are based on the time-register circuit. The low-pass filter is achieving the desired operation over process and temperature corners. Lastly, it is characterized by modular design, so it can be used as a building block for higher-order filters.

## 2. Implementation of the Time-Mode PWM Low-Pass Filter

#### 2.1. Top-Level Architecture

^{−1}operator and a z

^{−1}time adder with a gain equal to ½. The operation principle is based on the application of z-transformation to the analog circuits and systems [18]. The timing diagram of the circuit is presented in Figure 2c. The first input of the time adder receives the input signal directly and so the T

_{int.}

_{1}(k) signal will be equal to the T

_{in}(k) signal. It is assumed that the input signal is basically a pulse train in which every pulse has the same frequency as the sampling signal and is synchronous with it. On the second input of the time adder, the input pulse train is first passed through a z

^{−1}operator which delays every input pulse by one sampling clock and then it is connected on the second input of the time adder. Hence, the node T

_{int.}

_{2}(k) will be equal to:

^{−1}operation. As a result, the relationship between the output pulse width T

_{out}and the input pulse width T

_{in}of the low-pass filter is:

^{−1}operation, is small compared to the period of the input signal. Hence, for those frequencies, the z

^{−1}variable of Equation (3) is approximately equal to unity and therefore the gain of the impulse response that is described by Equation (3) will be approximately equal to 1. As the frequency increases, the time delay of the input signal becomes comparable to the sampling period. At the point where the frequency of the input signal becomes half the sampling frequency, the input signals of the time adder will have a 180° difference in phase. Therefore, their sum will be neglected and the gain of the transfer function will be zero. Therefore, the z-domain transfer function that was mentioned in Equation (3) describes a low-pass filter behavior in which, for frequencies sufficiently lower than the sampling frequency, the input signal will pass to the output and, for frequencies compared to the sampling frequency, the input signal will be attenuated [18]. It should be mentioned that for frequencies above half of the sampling frequency, the transfer function rebounds due to the aliasing effect as happens in many discrete-time systems. Thus, an anti-aliasing filter is needed during the reconstruction of the information to the voltage mode [18].

^{−1}+ 1) because it is assumed that the time adder does not add a time delay. Comparing the aforementioned equation with Equation (3), an extra phase difference between the output and input signals will be expected due to the additional delay added by the time adder.

#### 2.2. Time-Mode PWM Building Blocks

#### 2.2.1. Time Register Based on Gate-Controlled Current Source

_{set}signal is equal to the sampling signal. During the time where T

_{set}= ‘0’ (‘0’ means asserted to the ground), the capacitor is connected to the supply via transistor M1 which acts as a switch. Hence, the capacitor is charged to the voltage supply V

_{DD}. On the other hand, when T

_{set}= ‘1’ (‘1’ means asserted to the voltage supply), there are three distinct operations of the circuit. During the time interval of which T

_{in}= ‘1’, the capacitor is discharged via transistor M2 which acts as a current source, delivering constant discharging current equal to I

_{ref}. The current I

_{ref}that the current source delivers is controlled by its’ gate voltage V

_{CTRL}. The gate voltage of M2 is controlled through switches in order to be connected to V

_{CTRL}or to the ground with respect to digital control signal TR

_{in}, where TR

_{in}= T

_{in}+ T

_{clk}due to the OR gate. The value of the discharging capacitors’ slope is equal to:

_{in}= ‘0’ and T

_{clk}= ‘0’ (they are both equal to zero voltage), the capacitor is floating and hence voltage V

_{cap}remains constant. Finally, during the time interval of which T

_{clk}= ‘1’, the capacitor is also discharging with the constant slope described in Equation (4). During T

_{clk}= ‘1’ and when the voltage on the top plate of capacitor C crosses the reference voltage V

_{tp}of the comparator, the latter changes state. The digital logic that follows the comparator results in an output pulse with a frequency equal to T

_{set}while the phase between those two is equal to 180°. The pulse width of the output will be:

#### 2.2.2. Time-Adder Core Implementation with Gain ½

_{ref}/2, I

_{ref}/2, and I

_{ref}, respectively. For this option, there are three different operations that affect the value of the discharging slope. At the time interval where T

_{in}

_{1}= ‘1’ and T

_{in}

_{2}= ‘1’, transistors M3 and M4 are both open and deliver constant discharging current. As a result, the total discharging current of the capacitor will be equal to I

_{ref}and the value of the discharging slope will be given by Equation (4). When only one of the two inputs is connected to the supply, then the discharging current will drop to half and so will decrease the value of the discharging slope. Finally, during T

_{clk}= ‘1’, the circuit will have the same behavior as it had on the simple time register. Hence, every input signal will result in half of the voltage drop across the capacitor compared with the voltage drop from the T

_{clk}signal. As a result, on the output of the time adder with gain ½, a pulse will be generated which will be delayed by half of a period of the T

_{set}signal and with an output pulse width equal to:

#### 2.2.3. Implementation of a z^{−1} Operator Using a Time Register

^{−1}operation is achieved by employing two cascaded time registers as presented in Figure 5. For the z

^{−1}operation, the architecture which employs two cascaded time registers is selected instead of the architecture which uses four, in order to achieve less layout area, lower power consumption, and larger resolution [19].

_{set}

_{1}signal (sampling signal) and the T

_{set}

_{2}signal have the same pulse width but with a phase difference equal to 180°. Furthermore, the T

_{clk}

_{1}and T

_{clk}

_{2}signals have the same pulse width but with phases equal to 180° and 0°, respectively, with respect to the sampling signal (T

_{set}

_{1}signal).

_{in}, synchronous with the sampling signal, and produces an output pulse T

_{internal}delayed by half of a period of the T

_{set}

_{1}signal and with a pulse width equal to the complementary value of T

_{in}in respect to T

_{clk}:

_{internal}and produces output pulses delayed by half of a period of the T

_{set}

_{2}signal and with a pulse width equal to the complementary value of T

_{internal}with respect to T

_{clk}. As a result, the output pulse of the whole z

^{−1}operator will be a pulse delayed by one T

_{set}

_{1}clock and with a pulse width equal to the inputs’ pulse width:

#### 2.2.4. Implementation of the z^{−1} Time Adder with Gain ½

^{−1}time adder with time gain ½ is illustrated in Figure 6. The T

_{set}

_{1}signal is the sampling signal. In the implementation of the time adder, the time register is replaced by the time-adder core with gain ½ that was described earlier. As a result, the internal signal of the circuit will also be a pulse delayed by half of a period of the sampling signal but with a pulse width equal to the complementary value of half of the sum of the two inputs T

_{in}

_{1}and T

_{in}

_{2}of the time-adder core with respect to the T

_{clk}signal:

^{−1}operation, shifting the T

_{internal}signal by half of a period of the T

_{set1}signal and producing an output pulse with a pulse width equal to:

## 3. Discharging Slope Digital Calibration

_{clk}signal, the capacitor voltage drops from the voltage supply to the triple point of the leading comparator. At this point, the digital code stops increasing and locks to a specific value, delivering the desirable constant discharging current to achieve maximum input range.

## 4. Simulation Results

_{ref}, I

_{ref}/2, and I

_{ref}/2 accordingly.

_{in}= 0.5${V}_{DD}+{V}_{in.peak}$sin(2πf

_{in}$\xb7$t), where 0.5 V

_{DD}is the average voltage, V

_{in.peak}is the amplitude, and f

_{in}is the input frequency. The VTC converts this signal into a pulse train in which every pulse has magnitude:

_{in.peak}is the corresponding pulse magnitude width and ranges from 0 to 25 ns. Therefore, the width of every pulse ranges from 0 to 50 ns in a sinusoidal manner.

^{−1}operation which is inherent to the time adder.

_{0}is the fundamental frequency of the input signal, and A

_{in.f}

_{0}and A

_{out.f}

_{0}are the magnitudes on the fundamental frequency of input and output signals, respectively.

_{in.f}

_{0}and θ

_{out.f}

_{0}are the phases of the input and output signals, respectively. The phase difference between the output and input of the system has a linear relationship with the frequency of the input signal, as is expected by discrete-time system theory. It should be mentioned that, in relation to the phase response of an ideal discrete z-domain low-pass filter, an additional phase difference is added due to the inherent z

^{−1}operation of the time adder. As a result, the proposed system presents a phase difference of −135° at the cut-off frequency instead of −45° of the ideal discrete low-pass filter in which the time adder does not add additional time delay.

## 5. Conclusions

^{−1}operator and a time adder with gain ½. The circuit achieves the desired frequency response, cut-off frequency, and phase response over process and temperature corners. Due to its modular design and the fact that is synchronous with the sampling signal of the system, it can be used as a fundamental building block in the field of time-mode z-domain circuits and systems. As a result, this topology is going to be employed in the implementation of more complex filters suitable for time-mode z-domain signal processing, such as z-domain filters based on bilinear approximation and analog FIR/IIR filters. The implementation of time-mode z-domain filters is an interesting approach because it uses mainly digital standard cells while the analog part is minimized. Hence, it is characterized by low power consumption, high speed, and adaptation of technology scaling, in which the conventional pure analog approach fails [21].

## Author Contributions

## Funding

## Data Availability Statement

## Conflicts of Interest

## References

- Asada, K.; Nakura, T.; Iizuka, T.; Ikeda, M. Time-Domain Approach for Analog Circuits in Deep Sub-Micron LSI. IEICE Electron. Express
**2018**, 15, 20182001. [Google Scholar] [CrossRef] - Roberts, G.W.; Ali-Bakhshian, M. A Brief Introduction to Time-to-Digital and Digital-to-Time Converters. IEEE Trans. Circuits Syst. II Express Briefs
**2010**, 57, 153–157. [Google Scholar] [CrossRef] - Lee, D.; Lee, D.; Lee, T.; Kim, Y.H.; Kim, L.S. An Integrated Time Register and Arithmetic Circuit with Combined Operation for Time-Domain Signal Processing. In Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, Lisbon, Portugal, 24–27 May 2015; pp. 1830–1833. [Google Scholar] [CrossRef]
- Elgreatly, A.; Dessouki, A.; Mostafa, H.; Abdalla, R.; El-Rabaie, E. A Novel Highly Linear Voltage-to-Time Converter (VTC) Circuit for Time-Based Analog-to-Digital Converters (ADC) Using Body Biasing. Electronics
**2020**, 9, 2033. [Google Scholar] [CrossRef] - Pekau, H.; Yousif, A.; Haslett, J.W. A CMOS Integrated Linear Voltage-to-Pulse-Delay-Time Converter for Time Based Analog-to-Digital Converters. In Proceedings of the IEEE International Symposium on Circuits and Systems, Kos, Greece, 21–24 May 2006; pp. 2373–2376. [Google Scholar] [CrossRef]
- Kwon, H.J.; Lee, J.S.; Kim, B.; Sim, J.Y.; Park, H.J. Analysis of an Open-Loop Time Amplifier with a Time Gain Determined by the Ratio of Bias Current. IEEE Trans. Circuits Syst. II Express Briefs
**2014**, 61, 481–485. [Google Scholar] [CrossRef] - Yuan, F. Design Techniques of All-Digital Arithmetic Units for Time-Mode Signal Processing. IET Circuits Devices Syst.
**2018**, 12, 753–763. [Google Scholar] [CrossRef] - Ali-Bakhshian, M.; Roberts, G.W. Digital Storage, Addition and Subtraction of Time-Mode Variables. Electron. Lett.
**2011**, 47, 910–911. [Google Scholar] [CrossRef] - Panetas-Felouris, O.; Vlassis, S. A 3rd-Order FIR Filter Implementation Based on Time-Mode Signal Processing. Electronics
**2022**, 11, 902. [Google Scholar] [CrossRef] - Abdelfattah, M.; Roberts, G.W.; Chodavarapu, V.P. All-Digital Time-Mode Elliptic Filters Based on the Operational Simulation of LC Ladders. In Proceedings of the IEEE International Symposium on Circuits and Systems, Melbourne, VIC, Australia, 1–5 June 2014; pp. 2125–2128. [Google Scholar] [CrossRef]
- Abdelfattah, M.; Roberts, G.W. All-Digital Time-Mode Direct-Form All-Pole Biquadratic Filter Realization. IEEE Trans. Circuits Syst. II Express Briefs
**2017**, 64, 1262–1266. [Google Scholar] [CrossRef] - Ali-Bakhshian, M.; Roberts, G.W. A Digital Implementation of a Dual-Path Time-to-Time Integrator. IEEE Trans. Circuits Syst. I Regul. Pap.
**2012**, 59, 2578–2591. [Google Scholar] [CrossRef] - Karmakar, A.; De Smedt, V.; Leroux, P. Pseudo-Differential Time-Domain Integrator Using Charge-Based Time-Domain Circuits. In Proceedings of the 2021 IEEE 12th Latin America Symposium on Circuits and System (LASCAS), Arequipa, Peru, 21–24 February 2021; IEEE: Piscataway, NJ, USA; pp. 1–4. [Google Scholar]
- Park, Y.J.; Jarrett-Amor, D.; Yuan, F. Time Integrator for Mixed-Mode Signal Processing. In Proceedings of the IEEE International Symposium on Circuits and Systems, Montreal, QC, Canada, 22–25 May 2016; pp. 826–829. [Google Scholar] [CrossRef]
- Kim, D.; Kim, K.; Yu, W.; Cho, S. A Second-Order ΔΣ Time-to-Digital Converter Using Highly Digital Time-Domain Arithmetic Circuits. IEEE Trans. Circuits Syst. II Express Briefs
**2019**, 66, 1643–1647. [Google Scholar] [CrossRef] - Yuan, F. CMOS Time-to-Digital Converters for Mixed-Mode Signal Processing. J. Eng.
**2014**, 2014, 140–154. [Google Scholar] [CrossRef] - Ziabakhsh, S.; Gagnon, G.; Roberts, G.W. A Second-Order Bandpass ΔΣ Time-to-Digital Converter with Negative Time-Mode Feedback. IEEE Trans. Circuits Syst. I Regul. Pap.
**2019**, 66, 1355–1368. [Google Scholar] [CrossRef] - Razavi, B. The Z-Transform for Analog Designers [The Analog Mind]. IEEE Solid-State Circuits Mag.
**2020**, 12, 8–14. [Google Scholar] [CrossRef] - Pagkalos, K.P.; Panetas-Felouris, O.; Vlassis, S. Charge-Based Time Registers for z
^{−1}Implementation. In Proceedings of the Panhellenic Conference on Electronics & Telecommunications, Tripolis, Greece, 2–3 December 2022; pp. 1–6. [Google Scholar] [CrossRef] - Panetas-Felouris, O.; Vlassis, S. A Time-Domain Z−1 Circuit with Digital Calibration. J. Low Power Electron. Appl.
**2022**, 12, 3. [Google Scholar] [CrossRef] - Ravinuthula, V.; Garg, V.; Harris, J.G.; Fortes, J.A.B. Time-Mode Circuits for Analog Computation. Int. J. Circuit Theory Appl.
**2009**, 37, 631–659. [Google Scholar] [CrossRef]

**Figure 1.**(

**a**) Conceptual system block of the PWM time-mode low-pass filter, (

**b**) Signal flow of the PWM time-mode filter.

**Figure 3.**(

**a**) Intuitive circuit schematic of the gate-controlled time register, (

**b**) timing diagram, and (

**c**) symbol.

**Figure 4.**(

**a**) Implementation of the time-adder core circuit with gain ½, (

**b**) timing diagram, and (

**c**) symbol.

**Figure 5.**(

**a**) Symbol of z

^{−1}operator, (

**b**) architecture with two cascaded time registers, and (

**c**) timing diagram.

**Figure 6.**(

**a**) Symbol of z

^{−1}time-adder with gain ½. (

**b**) architecture with the TADD ½ in series with time register, and (

**c**) timing diagram.

Units | Min. | Typ. | Max. | |
---|---|---|---|---|

F_{sampling} | MHz | 5 | ||

Gain @ 58.59 kHz | dB | −0.045 | −0.031 | 0.106 |

f_{cut.off} | MHz | 1.2273 | 1.2323 | 1.2352 |

Power Consumption | μW | 59.04 |

Disclaimer/Publisher’s Note: The statements, opinions and data contained in all publications are solely those of the individual author(s) and contributor(s) and not of MDPI and/or the editor(s). MDPI and/or the editor(s) disclaim responsibility for any injury to people or property resulting from any ideas, methods, instructions or products referred to in the content. |

© 2023 by the authors. Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (https://creativecommons.org/licenses/by/4.0/).

## Share and Cite

**MDPI and ACS Style**

Pagkalos, K.P.; Panetas-Felouris, O.; Vlassis, S.
A Time-Mode PWM 1st Order Low-Pass Filter. *J. Low Power Electron. Appl.* **2023**, *13*, 32.
https://doi.org/10.3390/jlpea13020032

**AMA Style**

Pagkalos KP, Panetas-Felouris O, Vlassis S.
A Time-Mode PWM 1st Order Low-Pass Filter. *Journal of Low Power Electronics and Applications*. 2023; 13(2):32.
https://doi.org/10.3390/jlpea13020032

**Chicago/Turabian Style**

Pagkalos, Konstantinos P., Orfeas Panetas-Felouris, and Spyridon Vlassis.
2023. "A Time-Mode PWM 1st Order Low-Pass Filter" *Journal of Low Power Electronics and Applications* 13, no. 2: 32.
https://doi.org/10.3390/jlpea13020032