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A 0.6 V Bulk-Driven Class-AB Two-Stage OTA with Non-Tailed Differential Pair

DIEEI (Dipartimento di Ingegneria Elettrica Elettronica e Informatica), University of Catania, I-95125 Catania, Italy
*
Author to whom correspondence should be addressed.
J. Low Power Electron. Appl. 2023, 13(2), 24; https://doi.org/10.3390/jlpea13020024
Submission received: 24 February 2023 / Revised: 16 March 2023 / Accepted: 24 March 2023 / Published: 28 March 2023

Abstract

:
This work presents a two-stage operational transconductance amplifier suitable for sub-1 V operation. This characteristic is achieved thanks to the adoption of a bulk-driven non-tailed differential pair. Local positive feedback is exploited to boost the equivalent transconductance of the first stage and the quasi-floating gate approach enables the class AB operation of the second stage. Implemented in a standard 180 nm CMOS technology and supplied at 0.6 V, the amplifier exhibits a 350 kHz gain bandwidth product and a phase margin of 69° while driving a 150 pF load. Compared to other solutions in the literature, the proposed one exhibits a considerable performance improvement, especially for large signal operation.

1. Introduction

In applications that require low power consumption, such as implantable biomedical devices, sensor nodes for the Internet of Things, and energy-harvesting battery-less devices, the design of analog circuits has become a challenging task. Indeed, while in these applications the digital part benefits from the technological scaling in terms of energy consumption reduction and performance enhancement, the performance of analog circuits decreases when technology is scaled down due to the reduced intrinsic gains of transistors and of the signal-to-noise ratios [1,2]. These disadvantages are exacerbated when the supply voltage is reduced below 1V, in which the design of the operational transconductance amplifier (OTA), representing the universal and fundamental building block of any analog front-end, is particularly difficult.
Below the 1V supply, the most widely used design approach is the sub-threshold bias (also known as the weak reverse bias) [3,4,5,6,7,8,9,10]. Inverter-based OTAs represent another viable alternative [11,12,13]. However, the main disadvantage of operating the digital inverter as an amplifier is the high variation of the dc gain and gain bandwidth (GBW), with temperature and process corners. Moreover, only pseudo-differential operation is achievable.
When input rail-to-rail capability is required, the bulk driving (body driving) technique is an effective solution, even in combination with sub-threshold operation [14,15,16,17,18,19,20,21,22,23,24,25,26,27,28]. However, when compared to conventional gate-driven circuits, body-driven counterparts exhibit a lower voltage gain due to the reduced value of the bulk transconductance, which accounts for only 10–20% of the gate transconductance [1]. Moreover, if the bulk of NMOS transistors must also be driven, the body-driven approach mandates for a triple-well process. However, since most of the modern CMOS technologies provide such feature, this point is not a real limitation.
To overcome the low gain of bulk-driven OTAs, we exploit in this work local positive feedback to improve first-stage transconductance [26,29,30,31]. The class AB operation of the second stage is enabled by exploiting the quasi-floating gate approach [32]. Moreover, the tail bias current of the input gain stage is avoided while maintaining differential operation.
This paper is structured as follows.Section 2 discusses the circuit operation principle and analytical design equations are carried out. Section 3 describes the design and simulation of the OTA, while in Section 4 the experimental measurements and a comparison with other amplifiers in the literature are reported. Finally, concluding remarks are drawn in Section 5.

2. The Proposed Circuit

Figure 1 shows the schematic diagram of the designed amplifier. Where not represented, the transistor bulk terminal is considered to be connected to the corresponding source. The first OTA stage is a bulk-driven non-tailed differential pair M1-M2 loaded by the current mirror M3-M4 and M5-M6. Differential to single-ended conversion is implemented by the additional current mirror M9-M10. The diode-connected transistor MB1 generates the voltage VB1 to be applied to the gates of M1-M2, thus setting their bias current. It is worth noting that the bulk terminal of MB1 is biased through the voltage divider R1-R2, which sets the analog ground [26].
Due to the lack of the tail current generator, the couple M1-M2 works as a pseudo-differential pair; however, as detailed in [26], the overall OTA input stage exhibits a quasi-differential behavior due to the action of M7 and M8 that make voltages at node 1 and 2, as seen in in Figure 1, dependent on the difference of the inverting and noninverting input voltages.
Thanks to the action of the local positive feedback implemented by transistors M7 and M8, the equivalent differential transconductance of the first stage is expressed by [26]:
G m = β 1 α g m b 1 , 2
where
α = W / L 7 W / L 3 = W / L 8 W / L 5
β = W / L 4 W / L 3 = W / L 6 W / L 5 ,
and gmb1,2 is the bulk transconductance of M1 and M2 and it is assumed that (W/L)9 = (W/L)10.
From (1), it is apparent that the first-stage transconductance can be boosted by appropriately choosing the aspect ratios α and β from (2) and (3), respectively. In particular, to avoid the magnitude of the positive feedback being higher than one (and, consequently, the amplifier becoming a latch), parameter α must be lower than 1. As a general rule of thumb, it is desirable to set α less than 0.9 to guarantee an adequate margin against process mismatches [31].
The second stage is made up of the common source stage M11 and M12. Class AB operation is enabled by adding resistor RBATT, connected between the gate of the load transistor M12 and the diode-connected transistor MB3, and capacitor CBATT which adds a path for the signal during dynamic operation [32]. Under quiescent conditions and considering that no DC current flows through RBATT, the voltage at the gate of M12 is the same as at the gate of MB3. Consequently, the quiescent current in M12 can be precisely set like in a conventional current mirror. During dynamic operation, the voltage at the output of the first stage is subject to a large variation. Capacitor CBATT, which cannot discharge/charge rapidly through RBATT, acts as a floating battery and transfers the voltage changes to the gate of M12, thus providing class AB operation to the second stage.
The frequency compensation branch is implemented by the conventional Miller capacitor CC in series with the resistor RC connected across node 1 and the output node.
Neglecting the parasitic capacitance contribution at nodes 1, 2, and 3 in Figure 1, the open-loop transfer function of the OTA can be approximated as
A s A 0 1 + s z 1 + s p D 1 + s p 2
being A 0 = G m b g m 11 + g m 12 r o 1 r o 2 the DC gain, with ro1 = rd10//rd6 and ro2 = rd11//rd12, and the zero and poles expressed by
z = α + 2 C C 1 g m 3 , 5 + 2 R C
p D = 1 α 2 r o 2 C L + 1 + α β g m 11 + g m 12 r o 1 C C 1 α β g m 11 + g m 12 r o 1 r o 2 C C
p 2 = C L + 1 + α β g m 11 + g m 12 r o 1 C C C C C L 1 g m 3 , 5 + R C 1 + α β g m 11 + g m 12 r o 1 C L 1 g m 3 , 5 + R C
where the rightmost approximation in (6) and (7) holds if the following relation is satisfied:
C L 1 + α β g m 11 + g m 12 r o 1 C C
It is worth noting that, thanks to the adopted compensation strategy which exploits the embedded current buffer M3-M4-M9-M10, the non-dominant pole p2 is moved at high frequency by a factor equal to (1 + α)β as compared to a conventional two-stage Miller OTA.
The evaluation of the phase margin (PM) yields
P M 90 ° tan 1 G B W p 2 + tan 1 G B W z
where GBW is the gain bandwidth product equal to gmb1,2/CC.
The slew rate (SR) of an amplifier is determined by the maximum available charging/discharging currents of capacitors in the circuit. By inspection of Figure 1 and neglecting the effect of parasitic capacitors, the overall SR can be expressed as
S R min I 1 C C , I o u t C L I o u t C L
where I1 is the maximum current provided by M1 and Iout is the charging/discharging current of the class AB output stage. Being CC << CL, the rightmost approximation in (10) holds.

3. Design and Simulation Results

Using a standard 180 nm CMOS process supplied by STMicroelectronics, the amplifier shown in Figure 1 was designed using the transistor dimensions, bias conditions, passive components values, and small-signal parameters reported in Table 1, Table 2 and Table 3 and assuming a nominal supply voltage equal to 0.6 V. The resistors were implemented using high-resistance polysilicon resistors with a square resistance of 3 kΩ.
Considering the transistor dimensions reported in Table 1, parameters α and β are equal to 0.83 and 15, respectively. Therefore, the bulk transconductance of M1 and M2, equal to 3.98 μA/V, is boosted by about 88 times.
Corner simulations and Monte Carlo analysis are executed to assess the robustness of the amplifier over process, temperature, and mismatch variations. The results are reported in Table 4, Table 5 and Table 6 for three different temperatures (i.e., −10 °C, 27 °C, and 85 °C) for all transistor corners. The results show that the amplifier is stable in all conditions. Furthermore, Monte Carlo simulation results over 1000 runs show a relative standard deviation lower than 25% for all parameters.
Figure 2 shows the simulated input referred noise versus frequency. The white noise level is equal to 1.3 μV/√Hz.
Figure 3 shows the magnitude of the power supply rejection ratio (PSRR) and the common mode rejection ratio (CMRR) versus frequency.
Figure 4 depicts the DC transfer characteristic of the amplifier in unity-gain configuration, showing a rail-to-rail input common mode range (ICMR). In the same figure, it can be also noted that the input current is lower than 13 nA.

4. Measurement Results and Comparison

The OTA in Figure 1 has been fabricated and experimentally tested. The layout and the chip microphotograph of the circuit are shown in Figure 5. The occupied area is 1329 μm2.
The circuit has been characterized at a 0.6 V supply and a 150 pF capacitive load. Figure 6 reports the measured Bode plot in open-loop configuration, showing a GBW equal to 350 kHz and a PM equal to 69°. The transient response to a 100 mVpp input step, with the OTA in unity gain, is shown in Figure 7.
Table 6 summarizes the OTA main performance parameters and a comparison with other sub-1 V amplifiers taken form the literature. To evaluate the performance trade-off between bandwidth, load capacitance, slew rate (SR), and total bias quiescent, IT, we use in Table 6, the following conventional figures of merit:
I F O M S = G B W I T C L
I F O M L = S R I T C L .
Among the considered solutions, only the single-stage in [26] exhibits a higher value of IFOMS but with a DC gain equal to 38 dB only. As compared to the remaining solutions, the increase in (11a) is equal to about 3.45. The proposed topology shows an increase in IFOML equal to 4.36× against all the other solutions.
Two other traditional figures of merit, which take into account the silicon area, are included in Table 7:
I F O M A S = ω G B W A r e a I T C L
I F O M A L = S R A r e a I T C L .
Additionally, in this case the proposed solution outperforms the other amplifiers, except for the IFOMAS of [26]. It is worth noting, however, that the tail-less structure does not offer a CMRR and PSRR as high as tailed ones, but the values are still acceptable and comparable with other solutions.

5. Conclusions

In this paper, a two-stage OTA exploiting local positive feedback, a non-tailed differential pair, and a class AB second stage are discussed, analyzed, and experimentally tested. A comparison with the state-of-the-art reveals that the proposed solution is suitable for area-constrained low-voltage low-power applications such as battery-less IoT nodes.

Author Contributions

Conceptualization, A.D.G.; methodology, A.D.G. and S.P.; data curation, A.B. and A.D.G.; writing—original draft preparation, A.D.G.; writing—review and editing, A.D.G. and S.P.; visualization, A.B.; supervision, A.D.G. and S.P. All authors have read and agreed to the published version of the manuscript.

Funding

This work has been funded by European Union (NextGeneration EU), through the MUR-PNRR project SAMOTHRACE (ECS00000022).

Institutional Review Board Statement

Not applicable.

Informed Consent Statement

Not applicable.

Data Availability Statement

No new data were created or analyzed in this study. Data sharing is not applicable to this article.

Conflicts of Interest

The authors declare no conflict of interest.

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Figure 1. OTA schematic.
Figure 1. OTA schematic.
Jlpea 13 00024 g001
Figure 2. Input referred noise versus frequency.
Figure 2. Input referred noise versus frequency.
Jlpea 13 00024 g002
Figure 3. Magnitude of PSRR and CMRR versus frequency.
Figure 3. Magnitude of PSRR and CMRR versus frequency.
Jlpea 13 00024 g003
Figure 4. DC transfer characteristics in unity-gain configuration.
Figure 4. DC transfer characteristics in unity-gain configuration.
Jlpea 13 00024 g004
Figure 5. Chip microphotograph and layout of the amplifier.
Figure 5. Chip microphotograph and layout of the amplifier.
Jlpea 13 00024 g005
Figure 6. Measured open-loop Bode plot.
Figure 6. Measured open-loop Bode plot.
Jlpea 13 00024 g006
Figure 7. Measured unity-gain step response.
Figure 7. Measured unity-gain step response.
Jlpea 13 00024 g007
Table 1. Transistor dimensions.
Table 1. Transistor dimensions.
DeviceValue (µm/µm)
MB1, MB2, M1, M23/0.26 (×2)
MB1, M3, M56/0.26
M4, M6, M126/0.26 (×15)
M7, M85/0.26
M9, M106/0.26 (×4)
M116/0.26 (×8)
Table 2. Component values.
Table 2. Component values.
DeviceValue
R1, R2300 kΩ
RBATT1 MΩ
RC100 kΩ
CBATT800 fF
CC500 fF
CL150 pF
IBias180 nA
Table 3. Small-signal parameters.
Table 3. Small-signal parameters.
Param.ValueParameterValue
gm1,23.98 μA/Vgm9,1031.38 μA/V
gmb1,21.197 μA/Vgm1155.97 μA/V
gm3,52.71 μA/Vgm1262.89 μA/V
gm4,636.04 μA/Vro11.03 MΩ
gm7,81.848 μA/Vro2764 kΩ
Table 4. Corner and Monte Carlo (1000 iterations) analysis results for T = −10 °C.
Table 4. Corner and Monte Carlo (1000 iterations) analysis results for T = −10 °C.
Param.TTSSSFFSFFMC
µσ
Power (µW)3.293.113.193.313.443.270.24
DC Gain (dB)64.859.66756.767.167.40.8
GBW (kHz)357313.7349.6302.3370.1481.834.6
Phase Margin (deg)67.667.56769.668.867.62.1
Pos. Slew Rate (V/µs)0.170.090.340.080.30.170.04
Neg. Slew Rate (V/µs)6.615.985.476.76.626.580.57
VOS (µV)18.6−756.6−108.530.3−78.113.5·10−3
Table 5. Corner and Monte Carlo (1000 iterations) analysis results for T = 27 °C.
Table 5. Corner and Monte Carlo (1000 iterations) analysis results for T = 27 °C.
Param.TTSSSFFSFFMC
µΣ
Power (µW)3.713.563.643.363.863.690.28
DC Gain (dB)67.465.768.564.268.167.20.5
GBW (kHz)341.6333.1332.9337.2343.6471.924.2
Phase Margin (deg)66.665.466.367.16866.51.8
Pos. Slew Rate (V/µs)0.310.180.540.150.490.320.06
Neg. Slew Rate (V/µs)4.64.723.924.994.354.580.37
VOS (µV)53.850.667.837.258.8−30.513.4·10−3
Table 6. Corner and Monte Carlo (1000 iterations) analysis results for T = 85 °C.
Table 6. Corner and Monte Carlo (1000 iterations) analysis results for T = 85 °C.
Param.TTSSSFFSFFMC
µΣ
Power (µW)4.224.174.224.244.233.910.21
DC Gain (dB)68.16868.467.26866.40.4
GBW (kHz)304.3304.6295.9310.3303423.718.1
Phase Margin (deg)65.46465.365.766.865.41.5
Pos. Slew Rate (V/µs)0.570.390.880.350.840.580.08
Neg. Slew Rate (V/µs)2.152.421.552.711.862.150.22
VOS (µV)95.289107.78610516.913.4·10−3
Table 7. Comparison with others Sub-1 V experimentally tested OTAs.
Table 7. Comparison with others Sub-1 V experimentally tested OTAs.
Ref.[5][16][15][6][18][7][19][9][20][21][22][23][24][26][28][27]This Work
Year20052007200720122013201420152016201620182020202020202022202220232023
Technology (μm)0.180.350.350.180.350.180.0650.180.180.180.180.180.0650.180.180.130.18
Area (mm2)170.060.05320.0570.15750.0570.004950.0360.01980.00820.00850.00980.0028.66·10−47.9·10−32.34·10−31.33·10−3
Supply (V)0.50.610.810.50.50.50.70.30.30.30.250.40.40.30.6
CL (pF)2015178153034020203030151503035150
DC gain (dB)626976.2518870467757636598.17038608767
Ibias (μA)1500.93581.51970.153660.14360.0560.0420.043330.104000.081350.00960.010196.17
Power (μW)750.543581.21970.0751830.0725.20.01680.01260.0130.0260.032540.0240.033733.70
GBW (MHz)100.0118.10.05711.670.018380.00430.00280.002960.00310.00950.005560.0070.01030.3503
PM (°)6065 6066555756606152548879605869
SR (V/μs) a20.0153.880.141.950.003430.0022.80.00710.004150.00910.0020.00740.0790.003742.45
CMRR (dB)6574.570.56540--355519721106062.536855845.4
PSRR (dB)43--45--40--3752526256613830764750.8
Op. mode bGDBDBDGDBDGDBDGDBDBDBDBDBDBDBDBDBD
Stage #22112232322331232
IFOMS (MHz·pF/μA)1.330.180.380.300.893.600.311.141.671.002.112.151.3710.253.503.217.42
IFOML ((V/μs)·pF/μA)0.270.250.180.750.150.600.350.571.562.542.966.300.2913.6439.501.1659.56
IFOMAS (MHz·pF/μA·mm2)78.433.067.235.335.6463.1662.9231.7584.18121.95248.74219.00685.1011,838.33443.041372.895584.80
IFOMAL ((V/μs)·pF/μA·mm2)15.694.173.4613.100.9410.5371.2015.8778.56309.23348.74642.86144.2315,745.415000.00497.5444,817.46
a average value; b GD: gate drive, BD: bulk driven.
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Ballo, A.; Grasso, A.D.; Pennisi, S. A 0.6 V Bulk-Driven Class-AB Two-Stage OTA with Non-Tailed Differential Pair. J. Low Power Electron. Appl. 2023, 13, 24. https://doi.org/10.3390/jlpea13020024

AMA Style

Ballo A, Grasso AD, Pennisi S. A 0.6 V Bulk-Driven Class-AB Two-Stage OTA with Non-Tailed Differential Pair. Journal of Low Power Electronics and Applications. 2023; 13(2):24. https://doi.org/10.3390/jlpea13020024

Chicago/Turabian Style

Ballo, Andrea, Alfio Dario Grasso, and Salvatore Pennisi. 2023. "A 0.6 V Bulk-Driven Class-AB Two-Stage OTA with Non-Tailed Differential Pair" Journal of Low Power Electronics and Applications 13, no. 2: 24. https://doi.org/10.3390/jlpea13020024

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