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Article

Minimum Active Component Count Design of a PIλDμ Controller and Its Application in a Cardiac Pacemaker System †

1
Department of Physics, Electronics Laboratory, University of Patras, GR-26504 Rio Patras, Greece
2
Department of Electrical and Computer Engineering, University of Sharjah, Sharjah P.O. Box 27272, United Arab Emirates
3
Nanoelectronics Integrated Systems Center (NISC), Nile University, Giza 12677, Egypt
4
Department of Electrical and Software Engineering, University of Calgary, Calgary, AB T2N 1N4, Canada
*
Author to whom correspondence should be addressed.
This paper is an extended version of our paper published in the 2022 Panhellenic Conference on Electronics & Telecommunications (PACET), Nako J.; Psychalinos C. Heart Rate Controller Design for Cardiac Pacemaker, 2022 Panhellenic Conference on Electronics & Telecommunications (PACET), Tripolis, Greece, 2–3 December 2022; pp. 1–4, doi:10.1109/PACET56979.2022.9976347.
J. Low Power Electron. Appl. 2023, 13(1), 13; https://doi.org/10.3390/jlpea13010013
Submission received: 9 January 2023 / Revised: 26 January 2023 / Accepted: 31 January 2023 / Published: 2 February 2023

Abstract

:
A generalized structure for implementing fractional-order controllers is introduced in this paper. This is achieved thanks to the consideration of the controller transfer function as a ratio of integer and non-integer impedances. The non-integer order impedance is implemented using RC networks, such as the Foster and Cauer networks. The main offered benefit, with regards to the corresponding convectional implementations, is the reduced active and, also, passive component count. To demonstrate the versatility of the proposed concept, a controller suitable for implementing a cardiac pacemaker control system is designed. The evaluation of the performance of the system is performed through circuit simulation results, using a second-generation voltage conveyor as the active element.

1. Introduction

The functional block diagram of a fractional-order proportional-integral-derivative (PI λ D μ ) controller is demonstrated in Figure 1. Assuming that K p , K i and K d are constants associated with the proportional, integral, and derivative stages, respectively, and 0 < λ , μ < 1 , being the order of the integration and differentiation stages, respectively, then the transfer function of a PI λ D μ controller is given by (1)
C ( s ) = K p + K i s λ + K d s μ .
The extra degrees of freedom, originating from the non-integer order of the integration and differentiation stages of fractional-order controllers, offer the capability of easily and accurately adjusting the shape of the open-loop frequency response of control systems in order to meet the specifications related to the phase margin and settling time. This is in contrast to their integer-order counterparts, where only the associated time constants of the integration and differentiation stages can be adjusted [1,2,3,4,5,6,7,8]. A detailed discussion about the performance of the fractional-order controllers with regards to their integer-order counterparts has been provided in [9,10,11].
The realization of the functional block diagram in Figure 1 can be performed by the following ways:
(a)
utilizing RC networks (e.g., Cauer or Foster type) for approximating the behavior of fractional-order capacitors of the corresponding integration and/or differentiation stages, which are derived form their integer-order ones through the substitution of conventional capacitors by fractional-order capacitors [12]. This has been followed in [1,13,14,15]. The problem is that each-one of the required fractional-order capacitors must be substituted by a RC network, resulting in complicated structures in terms of passive component count. Although this is an easy procedure, in the sense that just only one design step is required for deriving the structure of the fractional-order controller, there is not capability of electronic adjustment of the characteristics of the controller.
(b)
utilizing approximation tools, such as Oustaloup [16], continued fraction expansion etc., of the fractional-order Laplacian operator in order to approximate the behavior of the intermediate fractional-order transfer functions of the controller (i.e., integrator and differentiator). The resulting integer-order rational transfer functions are implemented using conventional filter design techniques, such as the employment of multi-feedback or cascaded structures. This procedure has been followed in [17,18,19,20]. Considering an nth–order approximation of the Laplacian operator s r , with 0 < r < 1 being the order of the operator, the resulting transfer function has the form of (2)
s r P n s n + P n 1 s n 1 + + P 1 s + P 0 s n + Q n 1 s n 1 + + Q 1 s + Q 0 ,
with P i and Q j ( i = 0 n , j = 0 n 1 ) being positive and real coefficients. Taking into account that a PI λ D μ controller is constructed from stages of different orders, the resulting transfer function that describes the behavior of the controller will have an order equal to 2n, where n is the order of the approximation. Therefore, this solution suffers from the increased active and passive component count, worsening the performance of the system in terms of circuit complexity and power dissipation. On the other hand, it might be useful in the case where electronic adjustment of the characteristics of the controller would be required.
The motivation of this work is the development of PI λ D μ controllers structures, which have almost halved circuitry of that required in the cases where the conventional synthesis methods are followed. The main contributions made in this work can be summarized as follows: (a) the consideration of the controller’s transfer function as a ratio of integer and non-integer impedances, instead as a sum of the outputs of scaling, integration, and differentiation stages, and (b) the approximation of the frequency behavior of the fractional-order impedance using a curve-fitting based approximation tool available in MATLAB. The approximation impedance function can be implemented by Cauer or Foster RC networks. An attractive feature is that only one RC network is required for implementing the whole structure of the controller.
With regards to our previously published paper in [21] the enhancements are the following: (a) a detailed comparison of the proposed structure with the conventional implementations is performed, (b) possible RC networks for approximating fractional-order impedances are considered, (c) possible implementations of the introduced concept are presented, and (d) the implementation of the controller has been performed using an alternative active element and, therefore, new simulation results are presented. The employed active element is the second generation voltage conveyor (VCII), which contributes to further reduce the power dissipation of the circuits, because of its relatively simple structure. As an application design example, a heart rate control system suitable for pacemakers is designed, and its performance is evaluated using the Cadence IC Design suite and MOS transistor models provided by the Austria Mikro Systeme (AMS) 0.35 μ m CMOS process.
This work is organized as follows: the conventional implementations as well as the proposed one, using various types of active elements, are presented in Section 2, where the offered benefits are also discussed. The application example is provided in Section 3, while its behavior is evaluated in Section 4 through simulation results.

2. Proposed Implementation of Generalized Controller

2.1. Conventional Topologies

A typical implementation of the functional block diagram in Figure 1, using operational amplifiers (op-amps) as active elements, is demonstrated in Figure 2a [1]. As the impedance of a fractional-order capacitor is given by the general expression in (3)
Z α ( s ) = 1 C α s α ,
with 0 < α < 1 being the order of the element and C α being the pseudo-capacitance (in Farad/s1- α ) [22], the realized transfer function is
C ( s ) = R p 2 R p 1 + 1 R λ C λ s λ + R μ C μ s μ .
Equalizing the coefficients of (1)–(4) the design equations, summarized in (5), are readily obtained
K p = R p 2 R p 1 , K i = 1 R λ C λ , K d = R μ C μ .
Another alternative is the employment of second-generation current conveyors (CCIIs) as active elements, and the resulting structure is shown in Figure 2b. Considering the basic properties of the terminals of CCII (i.e., υ X = υ Y , i Y = 0 , i X = ± i Z ) , the realized transfer function as well as the design equations are the same as those in (4) and (5). A drawback of this structure is the requirement of employing extra voltage buffers, in order to avoid the effect of loading from subsequent stages. This can be resolved using Current Feedback Operational Amplifiers (CFOAs), which are actually CCIIs with an extra buffer internally embedded in their structure. The behavior of CFOAs is described by the formulas: υ X = υ Y , i Y = 0 , i X = i Z , υ Z = υ O and, therefore, the topology in Figure 2c implements the transfer function in (4).
The last active element which will be considered is the second-generation voltage conveyor (VCII), which is described by the following set of equations: υ Y = 0 , i X = ± i Z , υ Z = υ X . In other words, it can be considered as a special case of a CFOA with its Y terminal grounded, offering the aforementioned benefits of the CFOA. In addition, thanks to its internal structure constructed from one voltage and one current buffer, in contrast to the CFOA where 2 voltage buffers and one current buffer are required, its circuitry is simpler to that of the CFOA, offering also reduced power consumption [23,24,25,26,27,28]. The topology depicted in Figure 2d, realizes the same transfer function as the aforementioned ones and, consequently, the design equations in (5) are still valid.
Due to the absence of fractional-order capacitors in the market, their behavior will be emulated through the utilization of appropriately configured Foster or Cauer RC networks. Following this procedure and choosing among a variety of approximation tools, such as the Oustaloup, continued fraction expansion etc., the expression of the impedance of a fractional-order capacitor ( C α ) is approximated by an n th –order rational integer-order impedance function of the form in (6)
Z a p p r o x s B n s n + B n 1 s n 1 + + B 1 s + B 0 s n + A n 1 s n 1 + + A 1 s + A 0 ,
with A i i = 0 n 1 and B j j = 0 n being positive and real coefficients.
The impedance function in (6) can be implemented by the Cauer or Foster networks depicted in Figure 3. In the case of the Cauer type-I and type-II networks, the associated design equations are summarized in (7) and (8) respectively.
R 0 = q 0 R i = q i C j = q j , i = 2 , 4 2 n j = 1 , 3 2 n 1 ,
R 0 = 1 q 0 R i = 1 q i C j = 1 q j , i = 2 , 4 2 n j = 1 , 3 2 n 1 ,
where q i ( j ) are the coefficients of the continued fraction expansion of the Z a p p r o x s in (6) [22].
Accordingly, the design equations of the Foster type-I and type-II networks are given by (9) and (10)
R 0 = B n R i = r i p i C i = 1 r i , ( i = 1 , 2 n ) ,
R 0 = 1 B n R i = 1 r i C i = r i p i , ( i = 1 , 2 n ) ,
with r i and p i being the residues and poles of Z a p p r o x s .
Considering an nth–order approximation, the number of required active and passive elements for implementing a PI λ D μ controller following the conventional methods are summarized in Table 1. It is obvious that the complexity of the structure rapidly increases with the order of the approximation.

2.2. Proposed Generalized Structure

In order to overcome the aforementioned problem, the transfer function in (1) is written as
C ( s ) = R e x · K p + K i s λ + K d s μ R e x ,
with R e x being an arbitrary value resistance.
The associated design equations are provided in (12)
Z 1 = R e x Z 2 ( s ) = R e x · C ( s ) ,
with C ( s ) given by (1).
Another option is writing the transfer function in (1) as
C ( s ) = R e x R e x K p + K i s λ + K d s μ ,
with the associated design equations summarized in (14)
Z 1 ( s ) = R e x / C ( s ) Z 2 = R e x .
Generalizing, the transfer function of the controller can be expressed as a ratio of two impedances Z 1 and Z 2
C ( s ) = Z 2 Z 1 .
The choice of the impedance which will have fractional-order form depends on the behavior of the frequency response of the controller. Taking into account that the frequency behavior of the RC networks in Figure 3 is capacitive (i.e., the magnitude of the impedance decreases with the frequency) because they intend to approximate the behavior of fractional-order capacitors, then Z 2 ( s ) = R e x · C ( s ) in the case that the controller has such behavior. In the opposite case, Z 1 ( s ) = R e x / C ( s ) in order to ensure that the fractional-order impedance is realizable by the RC networks in Figure 3.
The implementation of (15), using op-amps, CCIIs, CFOAs, and VCIIs as active elements is demonstrated in Figure 4a–d.
The implementation of the fractional-order impedance function can be performed by the following techniques:
(a)
Approximating the intermediate terms that form the impedance using suitable tools such as the Oustaloup and the continued fraction expansion methods. Considering a nth–order approximation, the resulting order of the impedance Z 1 ( s ) or Z 2 ( s ) will be equal to 2 n and therefore the number of passive components of the RC networks will be equal to 4 n + 2 .
(b)
Approximating the magnitude and phase frequency characteristics of the impedance. The approximation is performed using the Sanathanan-Koerner (S-K) least square iterative method based on the following steps [21,29].
  • Obtain the frequency response data of the impedance, within the desired frequency range, using the MATLAB freqresp and frd functions.
  • Assuming an approximation order, obtain the state-space model of the data using the command fitfrd, and then convert this model to a transfer function using the MATLAB command ss2tf.
The resulting integer-order rational impedance function will be given by (6) and, consequently it always has an order equal to the order of the employed approximation (i.e., equal to n). Therefore, the number of passive components of the RC networks will be equal to 2 n + 1 . In other words, the number of resistors and capacitors required for constructing the Cauer of Foster networks is halved, compared to those required by employing the approximation of the intermediate terms of the impedance. In order to compare the implementations depicted in Figure 4a–d, in terms of complexity, Table 2 is established.
Inspecting Table 1 and Table 2, it is readily concluded that the proposed concept offers significant reduction in terms of active and passive component count, making it attractive for implementing control systems with reduced circuit complexity and, also, power dissipation. According to the results of Table 2, it seems that CFOAs and VCIIs implementations are the most beneficial ones. Taking into account that the internal structure of a CFOA is constructed by two voltage buffers and a current follower, while the VCII is formed by only one voltage buffer and a current follower, the VCII will be utilized in the next Section, where a design example will be provided, due to its simpler structure.

3. Design Example: Controlling the Heart Rate in a Pacemaker

A pacemaker is a battery-operated implantable device used to overcome arrhythmia situation, and uses slow electrical pulses for sustaining the heart rhythm at a normal rate. It is constructed from the sensing unit which senses the patient’s heart rate, and the output unit, which sends out electrical signals to heart muscles. In the case of bradycardia (the heart rate becomes slow) the output unit starts sending excitation signals to the heart muscles for maintaining the heart rate at the normal rhythm.
Let us consider for example the closed-loop system of the cardiac pacemaker, where C ( s ) is the transfer function of the controller, P ( s ) is the product of the transfer functions which describe the dynamics of the pacemaker and the heart [30,31,32]. The transfer function of the controller in [32] has been derived using the Particle Swarm Optimization (PSO) algorithm. The objective of the PSO algorithm is to minimize systems’ several error functions, including integral absolute error (IAE), integral time absolute error (ITAE), integral square error (ISE), and integral time square error (ITSE), subject to time or frequency domain constraints, such as the maximum overshoot, rise time and settling time, or system’s gain and phase margins. The resulting transfer function is given by the expression in (16)
C ( s ) = 0.72594 + 0.1 s 0.01 + 0.1 s 0.9786 ,
while the dynamics of the heart and pacemaker are described by (17)
P ( s ) = 1352 s ( s + 20.8 ) ( s + 8 ) .
The transfer function C ( s ) has such behavior that the choice Z 2 = R e x and Z 1 ( s ) = R e x / C ( s ) is the suitable one, according to the discussion provided in Section 2.2.
Assuming that R e x = 10 k Ω and utilizing a 3rd–order Oustaloup approximation in the range [10−1, 102] rad/s, then the resulting expression of Z 1 ( s ) is the following
Z 1 ( s ) = 15.76 s 3 + 1.114 · 10 5 s 2 + 4.958 · 10 6 s + 2.199 · 10 7 s 3 + 55.96 s 2 + 626.8 s + 1822 .
The magnitude and phase responses obtained through the MATLAB software are provided in the plots of Figure 5, where the corresponding ideal ones are also plotted by dashes. In addition, the accuracy of the utilized approximation is evaluated at transfer function level and the results are provided in Table 3, where it is evident that a satisfactory level of accuracy is achieved.

4. Simulation Results

The performance of the controller will be evaluated using the Cadence IC design suite and the design kit provided by the AMS 0.35 μ m CMOS process. The circuitry of the employed VCII- is depicted in Figure 6 [26]. The dc power supply voltages are V D D = V S S = 1.5 V, and the dc bias current ( I 0 ) is equal to 20 μ A. The dc power dissipation of the controller is 613 μ W. The aspect ratios of the MOS transistors are summarized in Table 4.
The values of the passive elements of the RC networks in Figure 3 calculated using (7)–(10), rounded to the E96 series defined in IEC 60063 standard, are summarized in Table 5 and Table 6.
Choosing, for demonstration purposes, the Foster type-I network in order to implement the impedance Z 1 ( s ) , the obtained magnitude and phase responses are demonstrated in Figure 7, where the theoretically predicted ones are also plotted as dashes. The sensitivity performance of the RC network is evaluated using the Monte-Carlo analysis tool offered by the Analog design Environment of the IC design suite. The obtained statistical plots of the magnitude and phase of the impedance at the gain crossover frequency (i.e., 6.34 rad/s), for N = 500 runs and 10% random tolerances of the passive elements values, are demonstrated in Figure 8. As the values of the standard deviation of the magnitude and phase are 6.8 Ω and 0.04 , and the associated mean values are 9.72 k Ω and −35.2 , it is verified the robustness of the employed network.
The magnitude and phase frequency responses of the controller are provided in Figure 9, with the corresponding theoretically predicted ones given as dashes, confirming the accurate operation of the introduced scheme of the controller. The open-loop responses of the controller-plant system are demonstrated in Figure 10.
The closed-loop behavior of the system is evaluated by stimulating it by a step voltage and the derived output waveform is provided in Figure 11. The derived performance simulation results for both open-loop and closed-loop configuration are given in Table 7, where it is readily obtained that the system behaves in a satisfactory level of accuracy.
The sensitivity of the system is evaluated using the Monte-Carlo analysis tool and considering the effect of mismatching of MOS transistors, as well as of the process parameters variations. The obtained statistical plots of the phase margin and gain crossover frequency are demonstrated in Figure 12a,b, where the associated values of the standard deviation are 0.2 , and 0.07 rad/s. Taking into account that the corresponding mean values are 71.14 and 6.42 rad/s, it is concluded that the proposed implementation offers reasonable sensitivity characteristics.
In addition, a corner analysis is performed considering ±10% variation of the dc power supply voltages, corners of the temperature equal to 0 C and 40 C, and worst case transistor models determines as slow NMOS and slow PMOS. The derived step responses are demonstrated in Figure 13, where the worst case values of the rise-time and settling-time are 226 ms and 320.3 ms, with the nominal values being 230.6 ms and 341.5 ms, respectively. The above results confirm the robustness of the designed system.

5. Conclusions

The novel concept, where the transfer function of a PI λ D μ controller is expressed as an impedance ratio has been presented in this paper. The main offered benefit is that the resulting structures are very simple, in the sense that the number of active and passive components is minimized, with regards to the conventional procedure where each one of the fractional-order Laplacian operator terms is approximated. This is achieved because, in the presented procedure, the whole impedance transfer function is approximated instead of the intermediate terms of the transfer function. Thanks to this approach, the resulting rational-order transfer function has half of the order of that derived by the conventional approach.
As a demonstration example, a heart rate control system for pacemakers has been realized and the derived simulation results confirm the correct operation of the controller and, also, its attractive sensitivity performance. A 3rd–order approximation has been chosen for implementing the resulting approximation function; generally, the order of the approximation depends on the frequency range of interest and a trade-off between the level of accuracy and the circuit complexity is performed for choosing the optimal value of the order.
It must be also mentioned at this point that the presented procedure is general and, therefore, future research steps could include the following: (a) application of the procedure in other types of fractional-order controllers, such as PI λ , PD μ , (b) application of the procedure in the case of power-law controllers, and (c) exploitation of possible Field Programmable Gate Array (FPGA) or Field Programmable Analog Array based (FPAA) implementations [33,34,35,36,37] of the controller, where digital programmability will be offered. Last point is the following: the presented procedure is oriented to the MATLAB software and the exploitation of the suitability of open-source software, such as the SciLab software [7] or the development of a Python language based routine, might be useful for further enhancing its versatility and availability.

Author Contributions

Conceptualization, C.P., J.N. and A.S.E.; methodology, J.N. and C.P.; software, J.N.; validation, J.N.; formal analysis, J.N.; investigation, J.N. and C.P.; writing—original draft preparation, C.P.; writing—review and editing, C.P. and A.S.E.; project administration, C.P. and A.S.E. All authors have read and agreed to the published version of the manuscript.

Funding

This research received no external funding.

Institutional Review Board Statement

Not applicable.

Informed Consent Statement

Not applicable.

Data Availability Statement

No new data were created or analyzed in this study. Data sharing is not applicable to this article.

Conflicts of Interest

The authors declare no conflict of interest.

Abbreviations

The following abbreviations are used in this manuscript:
AMSAustria Mikro Systeme
CCIISecond-Generation Current Conveyor
CFOACurrent Feedback Operational Amplifier
CMOSComplimentary Metal-Oxide Semiconductor
FPAAField Programmable Analog Array
FPGAField Programmable Gate Array
IAEIntegral Absolute Error
ITAEIntegral Time Absolute Error
ISEIntegral Square Error
ITSEIntegral Time Square Error
MOSMetal-Oxide Semiconductor
OP-AMPOperational Amplifier
PI λ D μ Fractional-Order Proportional Integral Derivative
RCResistor Capacitor
S-KSanathanan-Koerner
VCIISecond-Generation Voltage Conveyor

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Figure 1. Typical functional block diagram of a fractional-order PI λ D μ  controller.
Figure 1. Typical functional block diagram of a fractional-order PI λ D μ  controller.
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Figure 2. Typical implementations of a PI λ D μ controller using (a) op-amps, (b) CCIIs, (c) CFOAs, and (d) VCIIs as active elements.
Figure 2. Typical implementations of a PI λ D μ controller using (a) op-amps, (b) CCIIs, (c) CFOAs, and (d) VCIIs as active elements.
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Figure 3. RC networks for approximating the behavior of the fractional-order capacitors, which are required for implementing the controllers in Figure 2. (a) Cauer type-I, (b) Cauer type-II, (c) Foster type-I, and (d) Foster type-II.
Figure 3. RC networks for approximating the behavior of the fractional-order capacitors, which are required for implementing the controllers in Figure 2. (a) Cauer type-I, (b) Cauer type-II, (c) Foster type-I, and (d) Foster type-II.
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Figure 4. Proposed implementations of a PI λ D μ controller using for (a) op-amps, (b) CCIIs, (c) CFOAs and (d) VCIIs as active elements.
Figure 4. Proposed implementations of a PI λ D μ controller using for (a) op-amps, (b) CCIIs, (c) CFOAs and (d) VCIIs as active elements.
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Figure 5. Magnitude and phase frequency responses of the impedance Z 1 ( s ) , approximated by (18).
Figure 5. Magnitude and phase frequency responses of the impedance Z 1 ( s ) , approximated by (18).
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Figure 6. Internal structure of the VCII- employed in simulations [26].
Figure 6. Internal structure of the VCII- employed in simulations [26].
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Figure 7. Simulated gain and phase responses of the Foster type-I network, realized using the values in Table 6, for approximating the impedance Z 1 ( s ) .
Figure 7. Simulated gain and phase responses of the Foster type-I network, realized using the values in Table 6, for approximating the impedance Z 1 ( s ) .
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Figure 8. Monte Carlo analysis results about the (a) magnitude, and (b) phase of the impedance Z 1 ( s ) , approximated by a Foster type-I network.
Figure 8. Monte Carlo analysis results about the (a) magnitude, and (b) phase of the impedance Z 1 ( s ) , approximated by a Foster type-I network.
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Figure 9. Simulated gain and phase responses of the proposed controller.
Figure 9. Simulated gain and phase responses of the proposed controller.
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Figure 10. Open-loop gain and phase responses of the system controller-plant.
Figure 10. Open-loop gain and phase responses of the system controller-plant.
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Figure 11. Step response of the system controller-plant.
Figure 11. Step response of the system controller-plant.
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Figure 12. Monte-Carlo analysis results of the (a) phase margin, and (b) gain crossover frequency of the control system (N = 500 runs).
Figure 12. Monte-Carlo analysis results of the (a) phase margin, and (b) gain crossover frequency of the control system (N = 500 runs).
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Figure 13. Output waveforms for a step input equal to 100 mV, obtained through corner analysis.
Figure 13. Output waveforms for a step input equal to 100 mV, obtained through corner analysis.
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Table 1. Passive and active component count for implementing the controllers in Figure 2, employing an nth–order approximation for emulating the behavior of the fractional-order capacitors.
Table 1. Passive and active component count for implementing the controllers in Figure 2, employing an nth–order approximation for emulating the behavior of the fractional-order capacitors.
TopologyNumber of Active ElementsNumber of ResistorsNumber of Capacitors
Figure 2a4 2 n + 10 2 n
Figure 2b4 (plus 3 buffers) 2 n + 10 2 n
Figure 2c4 2 n + 10 2 n
Figure 2d4 2 n + 11 2 n
Table 2. Passive and active component count for implementing the controllers in Figure 4a–d, employing an nth–order approximation for emulating the behavior of a fractional-order impedance.
Table 2. Passive and active component count for implementing the controllers in Figure 4a–d, employing an nth–order approximation for emulating the behavior of a fractional-order impedance.
TopologyNumber of Active ElementsNumber of ResistorsNumber of Capacitors
Figure 4a2 n + 4 n
Figure 4b1 (plus 1 buffer) n + 2 n
Figure 4c1 n + 2 n
Figure 4d1 n + 2 n
Table 3. Comparison of the theoretical and approximated open and closed-loop performances of the control system [21].
Table 3. Comparison of the theoretical and approximated open and closed-loop performances of the control system [21].
ParameterTheoreticalApproximation
Phase margin ( )70.3970.34
Gain crossover frequency (rad/s)6.346.34
Rise-time (ms)308.1236.4
Settling-time (ms)472.7355.4
Table 4. MOS transistors aspect ratios of the VCII- topology in Figure 6.
Table 4. MOS transistors aspect ratios of the VCII- topology in Figure 6.
TransistorAspect Ratio (μm /μm )
Mp1–Mp9200/2
Mn1–Mn420/2
Mn5–Mn620/0.4
Mn7–Mn112/2
Mn12–Mn134/2
Table 5. Passive elements of Cauer networks in Figure 3a,b, for approximating the impedance Z 1 ( s ) = R e x / C ( s ) .
Table 5. Passive elements of Cauer networks in Figure 3a,b, for approximating the impedance Z 1 ( s ) = R e x / C ( s ) .
ElementCauer Type-ICauer Type-II
R 0 15.8 Ω 12.1 k Ω
R 2 1 k Ω 931 Ω
R 4 1.96 k Ω 118 Ω
R 6 215 Ω 18.7 Ω
C 1 9.09 μ F9.76 μ F
C 3 15.8 μ F178 μ F
C 5 953 μ F196 μ F
Table 6. Passive elements of Foster networks in Figure 3c,d, for approximating the impedance Z 1 ( s ) = R e x / C ( s ) .
Table 6. Passive elements of Foster networks in Figure 3c,d, for approximating the impedance Z 1 ( s ) = R e x / C ( s ) .
ElementFoster Type-IFoster Type-II
R 0 15.8 Ω 12.1 k Ω
R 1 187 Ω 15.8 Ω
R 2 10.7 k Ω 60.4 k Ω
R 3 1.24 k Ω 511 k Ω
C 1 127 μ F9.09 μ F
C 2 10.2 μ F0.412 μ F
C 3 174 μ F0.392 μ F
Table 7. Comparison of the approximated and simulated open and closed-loop performances of the control system.
Table 7. Comparison of the approximated and simulated open and closed-loop performances of the control system.
ParameterApproximationSimulation
Phase margin ( )70.3471.14
Gain crossover frequency (rad/s)6.346.42
Rise-time (ms)236.4230.6
Settling-time (ms)355.4341.5
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MDPI and ACS Style

Nako, J.; Psychalinos, C.; Elwakil, A.S. Minimum Active Component Count Design of a PIλDμ Controller and Its Application in a Cardiac Pacemaker System. J. Low Power Electron. Appl. 2023, 13, 13. https://doi.org/10.3390/jlpea13010013

AMA Style

Nako J, Psychalinos C, Elwakil AS. Minimum Active Component Count Design of a PIλDμ Controller and Its Application in a Cardiac Pacemaker System. Journal of Low Power Electronics and Applications. 2023; 13(1):13. https://doi.org/10.3390/jlpea13010013

Chicago/Turabian Style

Nako, Julia, Costas Psychalinos, and Ahmed S. Elwakil. 2023. "Minimum Active Component Count Design of a PIλDμ Controller and Its Application in a Cardiac Pacemaker System" Journal of Low Power Electronics and Applications 13, no. 1: 13. https://doi.org/10.3390/jlpea13010013

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