Next Issue
Volume 13, June
Previous Issue
Volume 12, December
 
 

J. Low Power Electron. Appl., Volume 13, Issue 1 (March 2023) – 22 articles

Cover Story (view full-size image): RISC-V has recently gained attention for safety applications thanks to its extendable instruction set and its many open-source implementations that allow for exploring multiple techniques to achieve fault tolerance. This work is centered on the application of the DMR paradigm within an interleaved multi-threading (IMT) RISC-V architecture, gaining the low overhead advantages of the DMR technique, overcoming the cost of saving checkpoints and restoring the software state using Dynamic TMR (DTMR) protection, which implies the behavior of a TMR only in the case of error detection. This work also demonstrates the concept of Dynamic TMR and how it can be applied to an existing RISC-V IMT core, evaluating the proposed technique through an extensive fault-injection (FI) simulation campaign. View this paper
  • Issues are regarded as officially published after their release is announced to the table of contents alert mailing list.
  • You may sign up for e-mail alerts to receive table of contents of newly released issues.
  • PDF is the official format for papers published in both, html and pdf forms. To view the papers in pdf format, click on the "PDF Full-text" link, and use the free Adobe Reader to open them.
Order results
Result details
Select all
Export citation of selected articles as:
14 pages, 1879 KiB  
Article
Extreme Path Delay Estimation of Critical Paths in Within-Die Process Fluctuations Using Multi-Parameter Distributions
by Miikka Runolinna, Matthew Turnquist, Jukka Teittinen, Pauliina Ilmonen and Lauri Koskinen
J. Low Power Electron. Appl. 2023, 13(1), 22; https://doi.org/10.3390/jlpea13010022 - 20 Mar 2023
Cited by 2 | Viewed by 1568
Abstract
Two multi-parameter distributions, namely the Pearson type IV and metalog distributions, are discussed and suggested as alternatives to the normal distribution for modelling path delay data that determines the maximum clock frequency (FMAX) of a microprocessor or other digital circuit. These distributions outperform [...] Read more.
Two multi-parameter distributions, namely the Pearson type IV and metalog distributions, are discussed and suggested as alternatives to the normal distribution for modelling path delay data that determines the maximum clock frequency (FMAX) of a microprocessor or other digital circuit. These distributions outperform the normal distribution in goodness-of-fit statistics for simulated path delay data derived from a fabricated microcontroller, with the six-term metalog distribution offering the best fit. Furthermore, 99.7% confidence intervals are calculated for some extreme quantiles on each dataset using the previous distributions. Considering the six-term metalog distribution estimates as the golden standard, the relative errors in single paths vary between 4 and 14% for the normal distribution. Finally, the within-die (WID) variation maximum critical path delay distribution for multiple critical paths is derived under the assumption of independence between the paths. Its density function is then used to compute different maximum delays for varying numbers of critical paths, assuming each path has one of the previous distributions with the metalog estimates as the golden standard. For 100 paths, the relative errors are at most 14% for the normal distribution. With 1000 and 10,000 paths, the corresponding errors extend up to 16 and 19%, respectively. Full article
Show Figures

Figure 1

25 pages, 11174 KiB  
Article
DycSe: A Low-Power, Dynamic Reconfiguration Column Streaming-Based Convolution Engine for Resource-Aware Edge AI Accelerators
by Weison Lin, Yajun Zhu and Tughrul Arslan
J. Low Power Electron. Appl. 2023, 13(1), 21; https://doi.org/10.3390/jlpea13010021 - 16 Mar 2023
Cited by 4 | Viewed by 2051
Abstract
Edge AI accelerators are utilized to accelerate the computation in edge AI devices such as image recognition sensors on robotics, door lockers, drones, and remote sensing satellites. Instead of using a general-purpose processor (GPP) or graphic processing unit (GPU), an edge AI accelerator [...] Read more.
Edge AI accelerators are utilized to accelerate the computation in edge AI devices such as image recognition sensors on robotics, door lockers, drones, and remote sensing satellites. Instead of using a general-purpose processor (GPP) or graphic processing unit (GPU), an edge AI accelerator brings a customized design to meet the requirements of the edge environment. The requirements include real-time processing, low-power consumption, and resource-awareness, including resources on field programmable gate array (FPGA) or limited application-specific integrated circuit (ASIC) area. The system’s reliability (e.g., permanent fault tolerance) is essential if the devices target radiation fields such as space and nuclear power stations. This paper proposes a dynamic reconfigurable column streaming-based convolution engine (DycSe) with programmable adder modules for low-power and resource-aware edge AI accelerators to meet the requirements. The proposed DycSe design does not target the FPGA platform only. Instead, it is an intellectual property (IP) core design. The FPGA platform used in this paper is for prototyping the design evaluation. This paper uses the Vivado synthesis tool to evaluate the power consumption and resource usage of DycSe. Since the synthesis tool is limited to giving the final complete system result in the designing stage, we compare DycSe to a commercial edge AI accelerator for cross-reference with other state-of-the-art works. The commercial architecture shares the competitive performance within the low-power ultra-small (LPUS) edge AI scopes. The result shows that DycSe contains 3.56% less power consumption and slight resources (1%) overhead with reconfigurable flexibility. Full article
(This article belongs to the Special Issue Low-Power Computation at the Edge)
Show Figures

Figure 1

18 pages, 3533 KiB  
Article
Efficient Dual Output Regulating Rectifier and Adiabatic Charge Pump for Biomedical Applications Employing Wireless Power Transfer
by Noora Almarri, Peter Langlois, Dai Jiang and Andreas Demosthenous
J. Low Power Electron. Appl. 2023, 13(1), 20; https://doi.org/10.3390/jlpea13010020 - 04 Mar 2023
Viewed by 2181
Abstract
A power management unit (PMU) is an essential block for diversified multi-functional low-power Internet of Things (IoT) and biomedical electronics. This paper includes a theoretical analysis of a high current, single-stage ac-dc, reconfigurable, dual output, regulating rectifier consisting of pulse width modulation (PWM) [...] Read more.
A power management unit (PMU) is an essential block for diversified multi-functional low-power Internet of Things (IoT) and biomedical electronics. This paper includes a theoretical analysis of a high current, single-stage ac-dc, reconfigurable, dual output, regulating rectifier consisting of pulse width modulation (PWM) and pulse frequency modulation (PFM). The regulating rectifier provides two independently regulated supply voltages of 1.8 V and 3.3 V from an input ac voltage. The PFM control feedback consists of feedback-driven regulation to adjust the driving frequency of the power transistors through adaptive buffers in the active rectifier. The PWM/PFM mode control provides a feedback loop to adjust the conduction duration accurately and minimize power losses. The design also includes an adiabatic charge pump (CP) to provide a higher voltage level. The adiabatic CP consists of latch-up and power-saving topologies to enhance its power efficiency. Simulation results show that the dual regulating rectifier has 94.3% voltage conversion efficiency with an ac input magnitude of 3.5 Vp. The power conversion efficiency of the regulated 3.3 V output voltage is 82.3%. The adiabatic CP has an overall voltage conversion efficiency (VCE) of 92.9% with a total on-chip capacitance of 60 pF. The circuit was designed using 180 nm CMOS technology. Full article
(This article belongs to the Special Issue Energy-Harvesting and Self-Powered Devices)
Show Figures

Figure 1

21 pages, 2004 KiB  
Article
Radio-Frequency Energy Harvesting Using Rapid 3D Plastronics Protoyping Approach: A Case Study
by Xuan Viet Linh Nguyen, Tony Gerges, Pascal Bevilacqua, Jean-Marc Duchamp, Philippe Benech, Jacques Verdier, Philippe Lombard, Pangsui Usifu Linge, Fabien Mieyeville, Michel Cabrera and Bruno Allard
J. Low Power Electron. Appl. 2023, 13(1), 19; https://doi.org/10.3390/jlpea13010019 - 17 Feb 2023
Cited by 3 | Viewed by 2020
Abstract
Harvesting of ambient radio-frequency energy is largely covered in the literature. The RF energy harvester is considered most of the time as a standalone board. There is an interest to add the RF harvesting function on an already-designed object. Polymer objects are considered [...] Read more.
Harvesting of ambient radio-frequency energy is largely covered in the literature. The RF energy harvester is considered most of the time as a standalone board. There is an interest to add the RF harvesting function on an already-designed object. Polymer objects are considered here, manufactured through an additive process and the paper focuses on the rapid prototyping of the harvester using a plastronic approach. An array of four antennas is considered for circular polarization with high self-isolation. The RF circuit is obtained using an electroless copper metallization of the surface of a 3D substrate fabricated using stereolithography printing. The RF properties of the polymer resin are not optimal; thus, the interest of this work is to investigate the potential capabilities of such an implementation, particularly in terms of freedom of 3D design and ease of fabrication. The electromagnetic properties of the substrate are characterized over a band of 0.5–2.5 GHz applying the two-transmission-line method. A circular polarization antenna is experimented as a rapid prototyping vehicle and yields a gain of 1.26 dB. A lab-scale prototype of the rectifier and power management unit are experimented with discrete components. The cold start-up circuit accepts a minimum voltage of 180 mV. The main DC/DC converter operates under 1.4 V but is able to compensate losses for an input DC voltage as low as 100 mV (10 μW). The rectifier alone is capable of 3.5% efficiency at −30 dBm input RF power. The global system of circularly polarized antenna, rectifier, and voltage conversion features a global experimental efficiency of 14.7% at an input power of −13.5 dBm. The possible application of such results is discussed. Full article
(This article belongs to the Special Issue Energy-Harvesting and Self-Powered Devices)
Show Figures

Figure 1

23 pages, 7408 KiB  
Article
Self-Parameterized Chaotic Map for Low-Cost Robust Chaos
by Partha Sarathi Paul, Anurag Dhungel, Maisha Sadia, Md Razuan Hossain and Md Sakib Hasan
J. Low Power Electron. Appl. 2023, 13(1), 18; https://doi.org/10.3390/jlpea13010018 - 13 Feb 2023
Cited by 2 | Viewed by 2440
Abstract
This paper presents a general method, called “self-parameterization”, for designing one-dimensional (1-D) chaotic maps that provide wider chaotic regions compared to existing 1-D maps. A wide chaotic region is a desirable property, as it helps to provide robust performance by enlarging the design [...] Read more.
This paper presents a general method, called “self-parameterization”, for designing one-dimensional (1-D) chaotic maps that provide wider chaotic regions compared to existing 1-D maps. A wide chaotic region is a desirable property, as it helps to provide robust performance by enlarging the design space in many hardware-security applications, including reconfigurable logic and encryption. The proposed self-parameterization scheme uses only one existing chaotic map, referred to as the seed map, and a simple transformation block. The effective control parameter of the seed map is treated as an intermediate variable derived from the input and control parameter of the self-parameterized map, under some constraints, to achieve the desired functionality. The widening of the chaotic region after adding self-parameterization is first demonstrated on three ideal map functions: Logistic; Tent; and Sine. A digitized version of the scheme was developed and realized in a field-programmable gate array (FPGA) implementation. An analog version of the proposed scheme was developed with very low transistor-count analog topologies for hardware-constrained integrated circuit (IC) implementation. The chaotic performance of both digital and analog implementations was evaluated with bifurcation plots and four established chaotic entropy metrics: the Lyapunov Exponent; the Correlation Coefficient; the Correlation Dimension; and Approximate Entropy. An application of the proposed scheme was demonstrated in a random number generator design, and the statistical randomness of the generated sequence was verified with the NIST test. Full article
(This article belongs to the Special Issue Low-Power Computation at the Edge)
Show Figures

Figure 1

13 pages, 1158 KiB  
Article
Decoding Algorithms and HW Strategies to Mitigate Uncertainties in a PCM-Based Analog Encoder for Compressed Sensing
by Carmine Paolino, Alessio Antolini, Francesco Zavalloni, Andrea Lico, Eleonora Franchi Scarselli, Mauro Mangia, Alex Marchioni, Fabio Pareschi, Gianluca Setti, Riccardo Rovatti, Mattia Luigi Torres, Marcella Carissimi and Marco Pasotti
J. Low Power Electron. Appl. 2023, 13(1), 17; https://doi.org/10.3390/jlpea13010017 - 13 Feb 2023
Viewed by 1928
Abstract
Analog In-Memory computing (AIMC) is a novel paradigm looking for solutions to prevent the unnecessary transfer of data by distributing computation within memory elements. One such operation is matrix-vector multiplication (MVM), a workhorse of many fields ranging from linear regression to Deep Learning. [...] Read more.
Analog In-Memory computing (AIMC) is a novel paradigm looking for solutions to prevent the unnecessary transfer of data by distributing computation within memory elements. One such operation is matrix-vector multiplication (MVM), a workhorse of many fields ranging from linear regression to Deep Learning. The same concept can be readily applied to the encoding stage in Compressed Sensing (CS) systems, where an MVM operation maps input signals into compressed measurements. With a focus on an encoder built on top of a Phase-Change Memory (PCM) AIMC platform, the effects of device non-idealities, namely programming spread and drift over time, are observed in terms of the reconstruction quality obtained for synthetic signals, sparse in the Discrete Cosine Transform (DCT) domain. PCM devices are simulated using statistical models summarizing the properties experimentally observed in an AIMC prototype, designed in a 90 nm STMicroelectronics technology. Different families of decoders are tested, and tradeoffs in terms of encoding energy are analyzed. Furthermore, the benefits of a hardware drift compensation strategy are also observed, highlighting its necessity to prevent the need for a complete reprogramming of the entire analog array. The results show >30 dB average reconstruction quality for mid-range conductances and a suitably selected decoder right after programming. Additionally, the hardware drift compensation strategy enables robust performance even when different drift conditions are tested. Full article
Show Figures

Figure 1

15 pages, 7128 KiB  
Article
Exploring Topological Semi-Metals for Interconnects
by Satwik Kundu, Rupshali Roy, M. Saifur Rahman, Suryansh Upadhyay, Rasit Onur Topaloglu, Suzanne E. Mohney, Shengxi Huang and Swaroop Ghosh
J. Low Power Electron. Appl. 2023, 13(1), 16; https://doi.org/10.3390/jlpea13010016 - 09 Feb 2023
Cited by 1 | Viewed by 2604
Abstract
The size of transistors has drastically reduced over the years. Interconnects have likewise also been scaled down. Today, conventional copper (Cu)-based interconnects face a significant impediment to further scaling since their electrical conductivity decreases at smaller dimensions, which also worsens the signal delay [...] Read more.
The size of transistors has drastically reduced over the years. Interconnects have likewise also been scaled down. Today, conventional copper (Cu)-based interconnects face a significant impediment to further scaling since their electrical conductivity decreases at smaller dimensions, which also worsens the signal delay and energy consumption. As a result, alternative scalable materials such as semi-metals and 2D materials were being investigated as potential Cu replacements. In this paper, we experimentally showed that CoPt can provide better resistivity than Cu at thin dimensions and proposed hybrid poly-Si with a CoPt coating for local routing in standard cells for compactness. We evaluated the performance gain for DRAM/eDRAM, and area vs. performance trade-off for D-Flip-Flop (DFF) using hybrid poly-Si with a thin film of CoPt. We gained up to a 3-fold reduction in delay and a 15.6% reduction in cell area with the proposed hybrid interconnect. We also studied the system-level interconnect design using NbAs, a topological semi-metal with high electron mobility at the nanoscale, and demonstrated its advantages over Cu in terms of resistivity, propagation delay, and slew rate. Our simulations revealed that NbAs could reduce the propagation delay by up to 35.88%. We further evaluated the potential system-level performance gain for NbAs-based interconnects in cache memories and observed an instructions per cycle (IPC) improvement of up to 23.8%. Full article
(This article belongs to the Special Issue Low Power Memory/Memristor Devices and Systems vol.2)
Show Figures

Figure 1

17 pages, 6975 KiB  
Article
A 1.1 V 25 ppm/°C Relaxation Oscillator with 0.045%/V Line Sensitivity for Low Power Applications
by Yizhuo Liao and Pak Kwong Chan
J. Low Power Electron. Appl. 2023, 13(1), 15; https://doi.org/10.3390/jlpea13010015 - 07 Feb 2023
Cited by 3 | Viewed by 2026
Abstract
A fully-integrated CMOS relaxation oscillator, realized in 40 nm CMOS technology, is presented. The oscillator includes a stable two-transistor based voltage reference without an operational amplifier, a simple current reference employing the temperature-compensated composite resistor, and the approximated complementary to absolute temperature (CTAT) [...] Read more.
A fully-integrated CMOS relaxation oscillator, realized in 40 nm CMOS technology, is presented. The oscillator includes a stable two-transistor based voltage reference without an operational amplifier, a simple current reference employing the temperature-compensated composite resistor, and the approximated complementary to absolute temperature (CTAT) delay-based comparators compensate for the approximated proportional to absolute temperature (PTAT) delay arising from the leakage currents in the switches. This relaxation oscillator is designed to output a square wave with a frequency of 64 kHz in a duty cycle of 50% at a 1.1 V supply. The simulation results demonstrated that the circuit can generate a square wave, with stable frequency, against temperature and supply variation, while exhibiting low current consumption. For the temperature range from −20 °C to 80 °C at a 1.1 V supply, the oscillator’ output frequency achieved a temperature coefficient (T.C.) of 12.4 ppm/°C in a typical corner in one sample simulation. For a 200-sample Monte Carlo simulation, the obtained T.C. is 25 ppm/°C. Under typical corners and room temperatures, the simulated line sensitivity is 0.045%/V with the supply from 1.1 V to 1.6 V, and the dynamic current consumption is 552 nA. A better figure-of-merit (FoM), which equals 0.129%, is displayed when compared to the representative prior-art works. Full article
(This article belongs to the Special Issue Ultra-Low-Power ICs for the Internet of Things)
Show Figures

Figure 1

15 pages, 888 KiB  
Article
Wideband Cascaded and Stacked Receiver Front-Ends Employing an Improved Clock-Strategy Technique
by Arash Abbasi and Frederic Nabki
J. Low Power Electron. Appl. 2023, 13(1), 14; https://doi.org/10.3390/jlpea13010014 - 02 Feb 2023
Cited by 1 | Viewed by 1652
Abstract
A wideband cascaded receiver and a stacked receiver using an improved clock strategy are proposed to support the software-defined radio (SDR). The improved clock strategy reduces the number of mixer switches and the number of LO clock paths required to drive the mixer [...] Read more.
A wideband cascaded receiver and a stacked receiver using an improved clock strategy are proposed to support the software-defined radio (SDR). The improved clock strategy reduces the number of mixer switches and the number of LO clock paths required to drive the mixer switches. This reduces the dynamic power consumption. The cascaded receiver includes an inverter-based low-noise transconductance amplifier (LNTA) using a feed-forward technique to enhance the noise performance; a passive mixer; and an inverter-based transimpedance amplifier (TIA). The stacked receiver architecture is used to reduce the power consumption by sharing the current between the LNTA and the TIA from a single supply. It utilizes a wideband LNTA with a capacitor cross-coupled (CCC) common-gate (CG) topology, a passive mixer to convert the RF current to an IF current, an active inductor (AI) and a 1/f noise-cancellation (NC) technique to improve the noise performance, and a TIA to convert the IF current to an IF voltage at the output. Both cascaded and stacked receivers are simulated in 22 nm CMOS technology. The cascaded receiver achieves a conversion-gain from 26 dB to 36 dB, a double-sideband noise-figure (NFDSB) from 1.4 dB to 3.9 dB, S11<10 dB and an IIP3 from 7.5 dBm to 10.5 dBm, over the RF operating band from 0.4 GHz to 12 GHz. The stacked receiver achieves a conversion-gain from 34.5 dB to 36 dB, a NFDSB from 4.6 dB to 6.2 dB, S11<10 dB, and an IIP3 from 21 dBm to 17.5 dBm, over the RF operating band from 2.2 GHz to 3.2 GHz. The cascaded receiver consumes 11 m from a 1 V supply voltage, while the stacked receiver consumes 2.4 m from a 1.2 V supply voltage. Full article
(This article belongs to the Special Issue Ultra-Low-Power ICs for the Internet of Things)
Show Figures

Figure 1

16 pages, 1105 KiB  
Article
Minimum Active Component Count Design of a PIλDμ Controller and Its Application in a Cardiac Pacemaker System
by Julia Nako, Costas Psychalinos and Ahmed S. Elwakil
J. Low Power Electron. Appl. 2023, 13(1), 13; https://doi.org/10.3390/jlpea13010013 - 02 Feb 2023
Cited by 5 | Viewed by 2222
Abstract
A generalized structure for implementing fractional-order controllers is introduced in this paper. This is achieved thanks to the consideration of the controller transfer function as a ratio of integer and non-integer impedances. The non-integer order impedance is implemented using RC networks, such as [...] Read more.
A generalized structure for implementing fractional-order controllers is introduced in this paper. This is achieved thanks to the consideration of the controller transfer function as a ratio of integer and non-integer impedances. The non-integer order impedance is implemented using RC networks, such as the Foster and Cauer networks. The main offered benefit, with regards to the corresponding convectional implementations, is the reduced active and, also, passive component count. To demonstrate the versatility of the proposed concept, a controller suitable for implementing a cardiac pacemaker control system is designed. The evaluation of the performance of the system is performed through circuit simulation results, using a second-generation voltage conveyor as the active element. Full article
Show Figures

Figure 1

33 pages, 9795 KiB  
Article
Energy Autonomous Wireless Sensing Node Working at 5 Lux from a 4 cm2 Solar Cell
by Marcel Louis Meli, Sebastien Favre, Benjamin Maij, Stefan Stajic, Manuel Boebel, Philip John Poole, Martin Schellenberg and Charalampos S. Kouzinopoulos
J. Low Power Electron. Appl. 2023, 13(1), 12; https://doi.org/10.3390/jlpea13010012 - 01 Feb 2023
Cited by 3 | Viewed by 3208
Abstract
Harvesting energy for IoT nodes in places that are permanently poorly lit is important, as many such places exist in buildings and other locations. The need for energy-autonomous devices working in such environments has so far received little attention. This work reports the [...] Read more.
Harvesting energy for IoT nodes in places that are permanently poorly lit is important, as many such places exist in buildings and other locations. The need for energy-autonomous devices working in such environments has so far received little attention. This work reports the design and test results of an energy-autonomous sensor node powered solely by solar cells. The system can cold-start and run in low light conditions (in this case 20 lux and below, using white LEDs as light sources). Four solar cells of 1 cm2 each are used, yielding a total active surface of 4 cm2. The system includes a capacitive sensor that acts as a touch detector, a crystal-accurate real-time clock (RTC), and a Cortex-M3-compatible microcontroller integrating a Bluetooth Low Energy radio (BLE) and the necessary stack for communication. A capacitor of 100 μF is used as energy storage. A low-power comparator monitors the level of the energy storage and powers up the system. The combination of the RTC and touch sensor enables the MCU load to be powered up periodically or using an asynchronous user touch activity. First tests have shown that the system can perform the basic work of cold-starting, sensing, and transmitting frames at +0 dBm, at illuminances as low as 5 lux. Harvesting starts earlier, meaning that the potential for full function below 5 lux is present. The system has also been tested with other light sources. The comparator is a test chip developed for energy harvesting. Other elements are off-the-shelf components. The use of commercially available devices, the reduced number of parts, and the absence of complex storage elements enable a small node to be built in the future, for use in constantly or intermittently poorly lit places. Full article
(This article belongs to the Special Issue Energy-Harvesting and Self-Powered Devices)
Show Figures

Figure 1

11 pages, 2925 KiB  
Article
Study of Nitrogen-Doped Carbon Nanotubes for Creation of Piezoelectric Nanogenerator
by Marina V. Il’ina, Olga I. Soboleva, Soslan A. Khubezov, Vladimir A. Smirnov and Oleg I. Il’in
J. Low Power Electron. Appl. 2023, 13(1), 11; https://doi.org/10.3390/jlpea13010011 - 22 Jan 2023
Cited by 4 | Viewed by 2691
Abstract
The creation of sustainable power sources for wearable electronics and self-powered systems is a promising direction of modern electronics. At the moment, a search for functional materials with high values of piezoelectric coefficient and elasticity, as well as non-toxicity, is underway to generate [...] Read more.
The creation of sustainable power sources for wearable electronics and self-powered systems is a promising direction of modern electronics. At the moment, a search for functional materials with high values of piezoelectric coefficient and elasticity, as well as non-toxicity, is underway to generate such power sources. In this paper, nitrogen-doped carbon nanotubes (N-CNTs) are considered as a functional material for a piezoelectric nanogenerator capable of converting nanoscale deformations into electrical energy. The effect of defectiveness and of geometric and mechanical parameters of N-CNTs on the current generated during their deformation is studied. It was established that the piezoelectric response of N-CNTs increased nonlinearly with an increase in the Young’s modulus and the aspect ratio of the length to diameter of the nanotube and, on the contrary, decreased with an increase in defectiveness not caused by the incorporation of nitrogen atoms. The advantages of using N-CNT to create energy-efficient piezoelectric nanogenerators are shown. Full article
(This article belongs to the Special Issue Energy-Harvesting and Self-Powered Devices)
Show Figures

Figure 1

24 pages, 1884 KiB  
Article
A Power-Efficient Neuromorphic Digital Implementation of Neural–Glial Interactions
by Angeliki Bicaku, Maria Sapounaki, Athanasios Kakarountas and Sotiris K. Tasoulis
J. Low Power Electron. Appl. 2023, 13(1), 10; https://doi.org/10.3390/jlpea13010010 - 18 Jan 2023
Cited by 4 | Viewed by 2236
Abstract
Throughout the last decades, neuromorphic circuits have incited the interest of scientists, as they are potentially a powerful tool for the treatment of neurological diseases. To this end, it is essential to consider the biological principles of the CNS and develop the appropriate [...] Read more.
Throughout the last decades, neuromorphic circuits have incited the interest of scientists, as they are potentially a powerful tool for the treatment of neurological diseases. To this end, it is essential to consider the biological principles of the CNS and develop the appropriate area- and power-efficient circuits. Motivated by studies that outline the indispensable role of astrocytes in the dynamic regulation of synaptic transmission and their active contribution to neural information processing in the CNS, in this work we propose a digital implementation of neuron–astrocyte bidirectional interactions. In order to describe the neuronal dynamics and the astrocytes’ calcium dynamics, a modified version of the original Izhikevich neuron model was combined with a linear approximation of the Postnov functional neural–glial interaction model. For the implementation of the neural–glial computation core, only three pipeline stages and a 10.10 fixed point representation were utilized. Regarding the results obtained from the FPGA implementation and the comparisons to other works, the proposed neural–glial circuit reported significant savings in area requirements (from 22.53% up to 164.20%) along with considerable savings in total power consumption of 28.07% without sacrificing output computation accuracy. Finally, an RMSE analysis was conducted, confirming that this particular implementation produces more accurate results compared to previous studies. Full article
Show Figures

Figure 1

3 pages, 267 KiB  
Editorial
Acknowledgment to the Reviewers of Journal of Low Power Electronics and Applications in 2022
by JLPEA Editorial Office
J. Low Power Electron. Appl. 2023, 13(1), 9; https://doi.org/10.3390/jlpea13010009 - 16 Jan 2023
Viewed by 1347
Abstract
High-quality academic publishing is built on rigorous peer review [...] Full article
17 pages, 5889 KiB  
Article
Numerical Optimization of a Nonlinear Nonideal Piezoelectric Energy Harvester Using Deep Learning
by Andreas Hegendörfer, Paul Steinmann and Julia Mergheim
J. Low Power Electron. Appl. 2023, 13(1), 8; https://doi.org/10.3390/jlpea13010008 - 12 Jan 2023
Cited by 1 | Viewed by 2230
Abstract
This contribution addresses the numerical optimization of the harvested energy of a mechanically and electrically nonlinear and nonideal piezoelectric energy harvester (PEH) under triangular shock-like excitation, taking into account a nonlinear stress constraint. In the optimization problem, a bimorph electromechanical structure equipped with [...] Read more.
This contribution addresses the numerical optimization of the harvested energy of a mechanically and electrically nonlinear and nonideal piezoelectric energy harvester (PEH) under triangular shock-like excitation, taking into account a nonlinear stress constraint. In the optimization problem, a bimorph electromechanical structure equipped with the Greinacher circuit or the standard circuit is considered and different electrical and mechanical design variables are introduced. Using a very accurate coupled finite element-electronic circuit simulator method, deep neural network (DNN) training data are generated, allowing for a computationally efficient evaluation of the objective function. Subsequently, a genetic algorithm using the DNNs is applied to find the electrical and mechanical design variables that optimize the harvested energy. It is found that the maximum harvested energy is obtained at the maximum possible mechanical stresses and that the optimum storage capacitor for the Greinacher circuit is much smaller than that for the standard circuit, while the total harvested energy by both configurations is similar. Full article
(This article belongs to the Special Issue Energy-Harvesting and Self-Powered Devices)
Show Figures

Figure 1

18 pages, 4283 KiB  
Article
Electromigration-Aware Architecture for Modern Microprocessors
by Freddy Gabbay and Avi Mendelson
J. Low Power Electron. Appl. 2023, 13(1), 7; https://doi.org/10.3390/jlpea13010007 - 11 Jan 2023
Cited by 1 | Viewed by 2189
Abstract
Reliability is a fundamental requirement in microprocessors that guarantees correct execution over their lifetimes. The reliability-related design rules depend on the process technology and device operating conditions. To meet reliability requirements, advanced process nodes impose challenging design rules, which place a major burden [...] Read more.
Reliability is a fundamental requirement in microprocessors that guarantees correct execution over their lifetimes. The reliability-related design rules depend on the process technology and device operating conditions. To meet reliability requirements, advanced process nodes impose challenging design rules, which place a major burden on the VLSI implementation flow because they impose severe physical constraints. This paper focuses on electromigration (EM), one of the critical factors affecting semiconductor reliability. EM is the aging process of on-die wires in integrated circuits (ICs). Traditionally, EM issues have been handled at the physical design level, which enforces reliability rules using worst-case scenario analysis to detect and solve violations. In this paper, we offer solutions that exploit architectural characteristics to reduce EM impact. The use of architectural methods can simplify EM solutions, and such methods can be incorporated with standard physical-design-based solutions to enhance current methods. Our comprehensive physical simulation results show that, with minimal area, power, and performance overhead, the proposed solution can relax EM design efforts and significantly extend a microprocessor’s lifetime. Full article
Show Figures

Figure 1

24 pages, 36314 KiB  
Article
FPGA-Based Decision Support System for ECG Analysis
by Agostino Giorgio, Cataldo Guaragnella and Maria Rizzi
J. Low Power Electron. Appl. 2023, 13(1), 6; https://doi.org/10.3390/jlpea13010006 - 07 Jan 2023
Cited by 7 | Viewed by 3197
Abstract
The high mortality rate associated with cardiac abnormalities highlights the need of accurately detecting heart disorders in the early stage so to avoid severe health consequence for patients. Health trackers have become popular in the form of wearable devices. They are aimed to [...] Read more.
The high mortality rate associated with cardiac abnormalities highlights the need of accurately detecting heart disorders in the early stage so to avoid severe health consequence for patients. Health trackers have become popular in the form of wearable devices. They are aimed to perform cardiac monitoring outside of medical clinics during peoples’ daily lives. Our paper proposes a new diagnostic algorithm and its implementation adopting a FPGA-based design. The conceived system automatically detects the most common arrhythmias and is also able to evaluate QT-segment lengthening and pulmonary embolism risk often caused by myocarditis. Debug and simulations have been carried out firstly in Matlab environment and then in Quartus IDE by Intel. The hardware implementation of the embedded system and the test for the functional accuracy verification have been performed adopting the DE1_SoC development board by Terasic, which is equipped with the Cyclone V 5CSEMA5F31C6 FPGA by Intel. Properly modified real ECG signals corrupted by a mixture of muscle noise, electrode movement artifacts, and baseline wander are used as a test bench. A value of 99.20% accuracy is achieved by taking into account 0.02 mV for the root mean square value of noise voltage. The implemented low-power circuit is suitable as a wearable decision support device. Full article
Show Figures

Figure 1

21 pages, 1719 KiB  
Article
A Bottom-Up Methodology for the Fast Assessment of CNN Mappings on Energy-Efficient Accelerators
by Guillaume Devic, Gilles Sassatelli and Abdoulaye Gamatié
J. Low Power Electron. Appl. 2023, 13(1), 5; https://doi.org/10.3390/jlpea13010005 - 05 Jan 2023
Viewed by 2131
Abstract
The execution of machine learning (ML) algorithms on resource-constrained embedded systems is very challenging in edge computing. To address this issue, ML accelerators are among the most efficient solutions. They are the result of aggressive architecture customization. Finding energy-efficient mappings of ML workloads [...] Read more.
The execution of machine learning (ML) algorithms on resource-constrained embedded systems is very challenging in edge computing. To address this issue, ML accelerators are among the most efficient solutions. They are the result of aggressive architecture customization. Finding energy-efficient mappings of ML workloads on accelerators, however, is a very challenging task. In this paper, we propose a design methodology by combining different abstraction levels to quickly address the mapping of convolutional neural networks on ML accelerators. Starting from an open-source core adopting the RISC-V instruction set architecture, we define in RTL a more flexible and powerful multiply-and-accumulate (MAC) unit, compared to the native MAC unit. Our proposal contributes to improving the energy efficiency of the RISC-V cores of PULPino. To effectively evaluate its benefits at system level, while considering CNN execution, we build a corresponding analytical model in the Timeloop/Accelergy simulation and evaluation environment. This enables us to quickly explore CNN mappings on a typical RISC-V system-on-chip model, manufactured under the name of GAP8. The modeling flexibility offered by Timeloop makes it possible to easily evaluate our novel MAC unit in further CNN accelerator architectures such as Eyeriss and DianNao. Overall, the resulting bottom-up methodology assists designers in the efficient implementation of CNNs on ML accelerators by leveraging the accuracy and speed of the combined abstraction levels. Full article
(This article belongs to the Special Issue RISC-V Architectures and Systems: Hardware and Software Perspectives)
Show Figures

Figure 1

10 pages, 5491 KiB  
Article
Simple Technique to Improve Essentially the Performance of One-Stage Op-Amps in Deep Submicrometer CMOS Technologies
by Jaime Ramirez-Angulo, Alejandra Diaz-Armendariz, Jesus E. Molinar-Solis, Alejandro Diaz-Sanchez and Jesus Huerta-Chua
J. Low Power Electron. Appl. 2023, 13(1), 4; https://doi.org/10.3390/jlpea13010004 - 04 Jan 2023
Cited by 2 | Viewed by 2113
Abstract
A comparative study of one-stage-amp performance improvement based on simulations in 22 nm, 45 nm, 90 nm, and 180 nm in deep submicrometer CMOS technologies is discussed. Generic SPICE models were used to simulate the circuits. It is shown that in all cases [...] Read more.
A comparative study of one-stage-amp performance improvement based on simulations in 22 nm, 45 nm, 90 nm, and 180 nm in deep submicrometer CMOS technologies is discussed. Generic SPICE models were used to simulate the circuits. It is shown that in all cases a simple modification using resistive local common mode feedback increases open-loop gain and gain-bandwidth product, peak output currents, and slew rate by close to an order of magnitude. It is shown that this modification is especially appropriate for its utilization in current CMOS technologies since large factor improvements were not available in previous technologies. The OTAs with resistive local common mode feedback require simple phase lead compensation with a very small additional silicon area and keep supply requirements and static power dissipation unchanged. Full article
Show Figures

Figure 1

18 pages, 1200 KiB  
Article
A Fully-Differential CMOS Instrumentation Amplifier for Bioimpedance-Based IoT Medical Devices
by Israel Corbacho, Juan M. Carrillo, José L. Ausín, Miguel Á. Domínguez, Raquel Pérez-Aloe and J. Francisco Duque-Carrillo
J. Low Power Electron. Appl. 2023, 13(1), 3; https://doi.org/10.3390/jlpea13010003 - 30 Dec 2022
Cited by 3 | Viewed by 2514
Abstract
The implementation of a fully-differential (FD) instrumentation amplifier (IA), based on indirect current feedback (ICF) and aimed to electrical impedance measurements in an Internet of Things (IoT) biomedical scenario, is presented. The IA consists of two FD transconductors, to process the input signal [...] Read more.
The implementation of a fully-differential (FD) instrumentation amplifier (IA), based on indirect current feedback (ICF) and aimed to electrical impedance measurements in an Internet of Things (IoT) biomedical scenario, is presented. The IA consists of two FD transconductors, to process the input signal and feed back the output signal, a summing stage, used to add both contributions and generate the correcting current feedback signal, and a common-mode feedback network, which controls the DC level at the output nodes of the circuit. The transconductors are formed by a voltage-to-current conversion resistor and two voltage buffers, which are based on a super source follower cell in order to improve the overall response of the circuit. As a result, a compact single-stage structure, suitable for achieving a high bandwidth and a low power consumption, is obtained. The FD ICF IA has been designed and fabricated in 180 nm CMOS technology to operate with a 1.8-V supply and provide a nominal gain of 4 V/V. Experimental results show a voltage gain of 3.78 ± 0.06 V/V, a BW of 5.83 MHz, a CMRR at DC around 70 dB, a DC current consumption of 266.4 μA and a silicon area occupation of 0.0304 mm2. Full article
(This article belongs to the Special Issue Ultra-Low-Power ICs for the Internet of Things)
Show Figures

Figure 1

13 pages, 1845 KiB  
Article
Evaluation of Dynamic Triple Modular Redundancy in an Interleaved-Multi-Threading RISC-V Core
by Marcello Barbirotta, Abdallah Cheikh, Antonio Mastrandrea, Francesco Menichelli, Marco Ottavi and Mauro Olivieri
J. Low Power Electron. Appl. 2023, 13(1), 2; https://doi.org/10.3390/jlpea13010002 - 28 Dec 2022
Cited by 10 | Viewed by 2854
Abstract
Functional safety is a key requirement in several application domains in which microprocessors are an essential part. A number of redundancy techniques have been developed with the common purpose of protecting circuits against single event upset (SEU) faults. In microprocessors, functional redundancy may [...] Read more.
Functional safety is a key requirement in several application domains in which microprocessors are an essential part. A number of redundancy techniques have been developed with the common purpose of protecting circuits against single event upset (SEU) faults. In microprocessors, functional redundancy may be achieved through multi-core or simultaneous-multi-threading architectures, with techniques that are broadly classifiable as Double Modular Redundancy (DMR) and Triple Modular Redundancy (TMR), involving the duplication or triplication of architecture units, respectively. RISC-V plays an interesting role in this context for its inherent extendability and the availability of open-source microarchitecture designs. In this work, we present a novel way to exploit the advantages of both DMR and TMR techniques in an Interleaved-Multi-Threading (IMT) microprocessor architecture, leveraging its replicated threads for redundancy, and obtaining a system that can dynamically switch from DMR to TMR in the case of faults. We demonstrated the approach for a specific family of RISC-V cores, modifying the microarchitecture and proving its effectiveness with an extensive RTL fault-injection simulation campaign. Full article
(This article belongs to the Special Issue RISC-V Architectures and Systems: Hardware and Software Perspectives)
Show Figures

Figure 1

18 pages, 3345 KiB  
Article
CCALK: (When) CVA6 Cache Associativity Leaks the Key
by Valentin Martinoli, Elouan Tourneur, Yannick Teglia and Régis Leveugle
J. Low Power Electron. Appl. 2023, 13(1), 1; https://doi.org/10.3390/jlpea13010001 - 27 Dec 2022
Viewed by 2233
Abstract
In this work, we study an end-to-end implementation of a Prime + Probe covert channel on the CVA6 RISC-V processor implemented on a FPGA target and running a Linux OS. We develop the building blocks of the covert channel and provide a detailed [...] Read more.
In this work, we study an end-to-end implementation of a Prime + Probe covert channel on the CVA6 RISC-V processor implemented on a FPGA target and running a Linux OS. We develop the building blocks of the covert channel and provide a detailed view of its behavior and effectiveness. We propose a realistic scenario for extracting information of an AES-128 encryption algorithm implementation. Throughout this work, we discuss the challenges brought by the presence of a running OS while carrying out a micro architectural covert channel. This includes the effects of having other running processes, unwanted cache evictions and the OS’ timing behavior. We also propose an analysis of the relationship between the data cache’s characteristics and the developed covert channel’s capacity to extract information. According to the results of our experimentations, we present guidelines on how to build and configure a micro architectural covert channel resilient cache in a mono-core mono-thread scenario. Full article
(This article belongs to the Special Issue RISC-V Architectures and Systems: Hardware and Software Perspectives)
Show Figures

Figure 1

Previous Issue
Next Issue
Back to TopTop