# Surrogate Assisted Optimization for Low-Voltage Low-Power Circuit Design

^{1}

^{2}

^{3}

^{*}

## Abstract

**:**

## 1. Introduction

## 2. Metamodeling Technique: An Overview

_{j}(x) represents the j

^{th}regression function model, β

_{j}is the corresponding weighting coefficient, and Z(x) is a stochastic process. The latter has a mean value equal to zero, and the covariance between two sampling points, x

_{i}and x

_{j}, is expressed as in [25,26,27]:

^{2}is the variance coefficient of Z(x) and R(θ,x

_{i},x

_{j}) is the correlation function.

## 3. The Optimization Kernel

_{1},…, x

_{n})∈ X, X ⊂ ℜ

^{n}is the decision space for the variables, f (x

_{i}): ℜ

^{n}⎯→ℜ, is the objective function and h

_{k}(x) ≤ 0, k = 1…m is a set of constraints that limit the values of the variables.

#### 3.1. The Particle Swarm Optimization Algorithm

_{Pbest}is the best position, x

_{Gbest}is the global best position, w is the inertia weight of the particle, and c

_{1}and c

_{2}are the construction parameters.

#### 3.2. The JAYA Algorithm

_{j,best,i}is the value of the variable j for the best candidate and X

_{j, worst,i}is the value of the variable j for the worst candidate. Xʹ

_{j,k,i}is the update value of X

_{j,k,I}and [r

_{1,j,i}, r

_{2,j,i}] are the random numbers for the j

^{th}variable during the i

^{th}iteration and varies between [0, 1]. Term 1 in Equation (6) specifies the trend of the solution to move closer to the best solution, whereas Term 2 specifies the trend of the solution to avoid the worst solution. X’

_{j,k,i}is accepted if it gives a better function value. At the end of the iteration, all the accepted function values have been used as inputs to the next iteration.

## 4. The Proposed Approach and Application Examples

#### 4.1. The Proposed Approach

#### 4.2. Application 1: A Class AB CMOS CCII+

_{bias}) values: 15 µA, 20 µA, 26 µA, 30 µA and 45 µA. The voltage power supply was V

_{dd}/V

_{ss}= ± 1 V. Five models were constructed and validated. Table 1 gives the relative error of the model created for the different bias currents of the class AB CMOS CCII+, where the accuracy of the constructed models can be easily interpreted.

_{bias}= 26 µA. (In order to not overload the paper, a unique case is presented.)

#### 4.3. Application 2: A Differential-Based Class AB CMOS CCII

_{bias}) values: 100 nA, 250 nA, 1 µA and 10 µA. To this end, four models were constructed and validated. The same sizes for both databases were considered. The voltage power supply was V

_{dd}/V

_{ss}= ± 0.6 V.

#### 4.4. Application 3: An CMOS OTA-Based CCII+

_{bias2}) values: 500 nA, 1 µA, 10 µA and 30 µA, where I

_{bias1}= 3 µA. Four models were constructed and validated, as shown in Table 5. The voltage power supply was V

_{dd}/V

_{ss}= ±1V. The obtained optimization results corresponding to the application of the Kriging model as an evaluator within the Jaya/PSO sizing kernel are given in Table 6. A comparison with the results given in [9,49] is also provided.

## 5. Comparisons and Discussion

## 6. Conclusions

## Author Contributions

## Funding

## Conflicts of Interest

## References

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**Figure 5.**HSPICE simulations of Rx of Class AB CMOS CCII+: Kriging-PSO vs. Kriging-Jaya (I

_{bias}= 26 µA).

**Figure 6.**Boxplot of the 50 execution results for Kriging-PSO and Kriging-Jaya regarding Rx performances of the Class AB CMOS CCII+. I

_{bias}= (

**a**) 15 µA, (

**b**) 20 µA, (

**c**) 26 µA, (

**d**) 30 µA, (

**e**) 45 µA.

**Figure 8.**HSPICE simulation of Rx of the differential-based class AB CMOS CCII: Kriging-PSO vs. Kriging-Jaya (I

_{bias}= 10 µA).

**Figure 9.**Boxplot of the 50 execution results for Kriging-PSO and Kriging-Jaya regarding Rx performances of the differential-based class AB CMOS CCII. I

_{bias}= (

**a**) 100 nA, (

**b**) 250 nA, (

**c**) 1 µA, (

**d**) 10 µA.

**Figure 11.**HSPICE simulation of Rx of CMOS OTA based CCII+: Kriging-PSO vs. Kriging-JAYA (I

_{bias2}= 10 µA).

**Figure 12.**Boxplot of the 50 execution results for Kriging-PSO and Kriging-Jaya regarding Rx performances of CMOS OTA based CCII+. I

_{bias2}= (

**a**) 500 nA, (

**b**) 1 µA, (

**c**) 10 µA, (

**d**) 30 µA.

I_{biais} (µA) | Relative Error (%) |
---|---|

15 | 0.042 |

20 | 0.046 |

26 | 0.005 |

30 | 0.007 |

45 | 0.009 |

I_{biais} (µA) | Ln (µm) | Wn (µm) | Lp (µm) | Wp (µm) | Optimized Rx (Ω) | Simulated Rx (Ω) | Relative Error (%) | |
---|---|---|---|---|---|---|---|---|

Kriging-PSO | 15 | 0.746 | 318.810 | 0.644 | 499.340 | 1242.500 | 1240.800 | 0.137 |

20 | 0.751 | 324.456 | 0.641 | 498.337 | 962.780 | 960.070 | 0.282 | |

26 | 0.834 | 276.812 | 0.689 | 500.000 | 764.250 | 765.820 | 0.205 | |

30 | 0.746 | 318.629 | 0.644 | 499.351 | 673.974 | 673.470 | 0.074 | |

45 | 0.503 | 453.117 | 0.546 | 497.754 | 476.360 | 476.350 | 0.002 | |

Kriging-Jaya | 15 | 0.663 | 499.910 | 0.665 | 500.000 | 1211.400 | 1208.000 | 0.281 |

20 | 0.681 | 496.242 | 0.667 | 500.000 | 936.972 | 934.490 | 0.265 | |

26 | 0.713 | 498.740 | 0.665 | 500.000 | 743.120 | 741.480 | 0.221 | |

30 | 0.715 | 499.375 | 0.664 | 500.000 | 655.792 | 654.434 | 0.207 | |

45 | 0.714 | 500.000 | 0.664 | 500.000 | 463.960 | 462.938 | 0.220 |

I_{biais} (µA) | Relative Error (%) |
---|---|

0.10 | 0.829 |

0.25 | 0.386 |

1 | 0.092 |

10 | 0.007 |

I_{biais} (µA) | Ln (µm) | Wn (µm) | Lp (µm) | Wp (µm) | Optimized Rx (Ω) | Simulated Rx (Ω) | Relative Error (%) | |
---|---|---|---|---|---|---|---|---|

Kriging- PSO | 0.10 | 693.521 | 31.530 | 848.132 | 746.120 | 9.265 | 9.487 | 2.340 |

0.25 | 444.361 | 32.237 | 769.656 | 261.891 | 9.946 | 10.084 | 1.360 | |

1 | 283.484 | 30.710 | 832.148 | 124.233 | 9.037 | 8.953 | 0.930 | |

10 | 498.060 | 31.583 | 824.740 | 276.939 | 8.530 | 8.492 | 0.450 | |

Kriging- JAYA | 0.10 | 99.160 | 35.000 | 849.576 | 474.915 | 9.340 | 9.377 | 0.400 |

0.25 | 562.035 | 26.702 | 849.958 | 451.720 | 9.093 | 9.088 | 0.050 | |

1 | 648.526 | 33.385 | 849.958 | 49.618 | 8.662 | 8.750 | 1.000 | |

10 | 850.000 | 27.006 | 849.958 | 48.875 | 8.050 | 8.057 | 0.090 |

I_{biais2} (µA) | Relative Error (%) |
---|---|

0.5 | 0.365 |

1 | 0.366 |

10 | 0.507 |

30 | 0.378 |

I_{biais2} (µA) | Ln (µm) | Wn (µm) | Lp (µm) | Wp (µm) | Optimized Rx (Ω) | Simulated Rx (Ω) | Relative Error (%) | |
---|---|---|---|---|---|---|---|---|

Kriging- PSO | 0.5 | 385.211 | 13.468 | 377.879 | 401.654 | 15.000 | 15.007 | 0.047 |

1 | 333.942 | 11.767 | 360.872 | 365.650 | 7.817 | 7.802 | 0.191 | |

10 | 402.660 | 17.227 | 418.236 | 417.988 | 0.947 | 0.952 | 0.493 | |

30 | 437.826 | 11.018 | 403.388 | 371.282 | 0.367 | 0.369 | 0.515 | |

Kriging- JAYA | 0.5 | 356.367 | 11.297 | 440.913 | 404.515 | 14.802 | 14.830 | 0.189 |

1 | 347.074 | 11.384 | 441.399 | 422.708 | 7.681 | 7.698 | 0.220 | |

10 | 343.585 | 11.572 | 448.640 | 417.206 | 0.928 | 0.932 | 0.429 | |

30 | 356.406 | 11.419 | 443.569 | 411.998 | 0.362 | 0.364 | 0.549 |

I_{bias} | V_{dd}/V_{ss} | Kriging-PSO | Kriging-JAYA | [9] | [49] | |
---|---|---|---|---|---|---|

Application #1 | 26 µA | ± 1 V | 765.82 Ω | 741.48 Ω | 725.00 Ω | 990.00 Ω |

Application #2 | 10 µA | ± 0.6 V | 8.50 Ω | 8.06 Ω | 8.50 Ω | 12.00 Ω |

Application #3 | 10 µA | ± 1 V | 0.95 Ω | 0.93 Ω | 0.90 Ω | 1.30 Ω |

Computation Time (s) | -- | -- | 3.69 | 3.88 | 400.00 | -- |

JAYA vs. PSO | p-Value | T+ | T- | Winner |
---|---|---|---|---|

Application #1 | 7.5569 × 10^{−10} | 0 | 50 | Jaya |

Application #2 | 7.5569 × 10^{−10} | 0 | 50 | Jaya |

Application #3 | 7.5569 × 10^{−10} | 0 | 50 | Jaya |

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**MDPI and ACS Style**

Garbaya, A.; Kotti, M.; Fakhfakh, M.; Tlelo-Cuautle, E.
Surrogate Assisted Optimization for Low-Voltage Low-Power Circuit Design. *J. Low Power Electron. Appl.* **2020**, *10*, 20.
https://doi.org/10.3390/jlpea10020020

**AMA Style**

Garbaya A, Kotti M, Fakhfakh M, Tlelo-Cuautle E.
Surrogate Assisted Optimization for Low-Voltage Low-Power Circuit Design. *Journal of Low Power Electronics and Applications*. 2020; 10(2):20.
https://doi.org/10.3390/jlpea10020020

**Chicago/Turabian Style**

Garbaya, Amel, Mouna Kotti, Mourad Fakhfakh, and Esteban Tlelo-Cuautle.
2020. "Surrogate Assisted Optimization for Low-Voltage Low-Power Circuit Design" *Journal of Low Power Electronics and Applications* 10, no. 2: 20.
https://doi.org/10.3390/jlpea10020020