# The Impact of Ambient Temperature on Electrothermal Characteristics in Stacked Nanosheet Transistors with Multiple Lateral Stacks

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## Abstract

**:**

_{amb}) on the SHE in stacked nanosheet transistors is investigated. As the number of lateral stacks (N

_{stack}) increases, the nanoscale devices show more severe thermal crosstalk issues, and the current performance between n- and p-type nanoscale transistors exhibits different degradation trends. To compare the effect of different T

_{amb}ranges, the temperature coefficients of current per stack and threshold voltage are analyzed. As the N

_{stack}increases from 4 to 32, it is verified that the zero-temperature coefficient bias point (V

_{ZTC}) decreases significantly in p-type nanoscale devices when T

_{amb}is above room temperature. This can be explained by the enhanced thermal crosstalk. Then, the gate length-dependent electrothermal characteristics with different N

_{stack}s are investigated at various T

_{amb}s. To explore the origin of drain current variation, the temperature-dependent backscattering model is utilized to explain the variation. At last, the simulation results verify the impact of T

_{amb}on the SHE. The study provides an effective design guide for stacked nanosheet transistors when considering multiple stacks in circuit applications.

## 1. Introduction

_{2}, greatly hinder heat transport, leading to a severe self-heating effect (SHE) [4,5,6,7]. The thermal conductivity of Si active regions decreases significantly due to intensified phonon scattering. Then, the thermal conductivity of the source/drain (S/D) causes an additional decrease due to heavy doping and the SiGe alloy material adopted. In addition, the nanosheet channels are floated and isolated from the substrate, making it difficult to transport heat. Due to the gate stack structure, phonon-boundary scattering is intensified. These factors lead to SHE issues being prominent in NSFET. The SHE can cause degradation of electrical performance and bring about reliability issues, ultimately decreasing the device’s lifetime significantly [8,9,10,11,12]. Some researchers have conducted a series of investigations into SHE issues, including compact models, optimization technologies, and self-heating mechanisms [13,14,15,16,17,18,19]. In addition, the multiple lateral stacks are fabricated in NSFETs for high performance. The self-heating will be exacerbated due to the rising current in the lateral stack structure [7]. This is one aspect of thermal issues.

_{amb}), where the T

_{amb}includes those from inside the chip and the surrounding environment. The high T

_{amb}can change the temperature-sensitivity threshold voltage (V

_{th}) and introduce variability in the on-state current. At the same time, the T

_{amb}plays a crucial role in thermal properties, such as thermal conductivity, lattice temperature rise, and thermal resistance (R

_{th}) [20,21,22,23,24,25]. Some researchers have analyzed the electrothermal characteristics of FinFETs with multiple fins under the impact of T

_{amb}[20,23,26]. However, few studies focus on the research of T

_{amb}on NSFET with different numbers of lateral stacks (N

_{stack}). In addition, there are few works on the geometry effect in NSFETs with different N

_{stack}s. Therefore, we performed a symmetrical investigation on the electrothermal performance of NSFETs with different N

_{stack}s under the T

_{amb}impact. Furthermore, the geometry effect with different N

_{stack}s is also studied.

_{amb}-dependent SHE in NSFETs with different N

_{stack}s is symmetrically measured and analyzed. The rest of the article is divided into three parts. Section 2 discusses the fabrication of NMOS and PMOS in detail. In Section 3, the current variation with different N

_{stack}s is explored. Then, the geometry effect with different gate lengths is further analyzed based on the backscattering model. In addition, the simulations are conducted for verification. Finally, the conclusion is given in Section 4.

## 2. Device Fabrication

_{ch}= 3). In this step, the reduced pressure chemical vapor deposition was used to grow the periodical GeSi/Si multilayer with 16 nm Ge

_{0.3}Si

_{0.7}and 10 nm Si. Then, the fin array was carried out using spacer image transfer (SIT) technology, which was formed using a SiN

_{x}hard mask. For high-performance desire, the stacked nanosheets were fabricated with multiple lateral stacks in this step, as shown in Figure 1b. The number of parallel nanorails of lateral stacks is defined as N

_{stack}. The N

_{stack}is 2, 4, 8, 16, and 32. Next, the shallow trench isolation (STI) was formed to decrease the leakage current between the devices. Meanwhile, the rapid annealing process was performed to make the film compact. Then, a dummy gate was fabricated with amorphous Si to protect the nanosheets. After the deposition of amorphous Si, the chemical mechanical planarization (CMP) was used to perform the planarization process. The dummy gate image was formed using deposition and etch of Si

_{3}N

_{4}hard mask. The inner spacer formation was a key process that was deposited using SiN

_{x}and etched using reactive ion etching (RIE). After this, the in-situ doping process with highly doped doses and the activation process were carried out to form S/D. The zero-level interlayer dielectric (ILD0) with SiN

_{x}is used to avoid the over-etch phenomenon. After the dummy gate removal, GeSi was selectively removed using the wet-etched technique. After forming the thin gate oxide layer, the HfO

_{2}was deposited and the nanosheet was surrounded by different metal stacks. The atom-layer-deposition technology (ALD) was used to deposit the multilayer HK/MG films, and the CMP was performed to achieve gate separation. Finally, the tungsten contact and the BEOL process were fabricated to complete the NSFETs.

_{NS}) is about 30 nm, and the nanosheet thickness (T

_{NS}) is about 10 nm. The gate length (L

_{G}) is 30, 40, 60, and 500 nm. Then, energy-dispersive spectroscopy (EDS) is used to exhibit the distribution of elements in NSFETs, as shown in Figure 3. It shows that Ge has been completely removed, and the nanosheets are separated from each other. Each nanosheet is surrounded by Hf and oxide elements. This indicates that the nanosheets can be well controlled using bias voltages. At the same time, it can be seen that Al, Ti, N, and Ta elements are deposited surrounding the nanosheets, and the W element has been wrapped to the Si nanosheets.

## 3. Results and Discussion

#### 3.1. Electrothermal Performance of Different Numbers of Stacks under the Impact of Ambient Temperature

_{amb}), the T

_{amb}-dependent SHE in NSFETs is measured using the Agilent B1500 semiconductor parameter analyzer (Agilent Technologies, Santa Clara, CA, USA). The T

_{amb}varies from −50 °C to 125 °C in a 25 °C step.

_{DS}) as the T

_{amb}increases for NMOS and PMOS. The threshold voltages (V

_{th}s) are 300 mV and −300 mV at T

_{amb}= 25 °C of room temperature (T

_{rt}) for NMOS and PMOS, respectively. The V

_{th}is extracted using the constant current method. As the T

_{amb}increases, the |V

_{th}| decreases because the carrier concentration is positively correlated with the T

_{amb}. In Figure 4a, the I

_{DS}of NMOS shows an increasing trend. Meanwhile, the I

_{DS}of PMOS also shows an increasing trend at a lower |V

_{GS}|. However, it exhibits a reverse temperature dependence at a larger |V

_{GS}|, as shown in Figure 4b. This is because the effect of the V

_{th}reduction exceeds that of the mobility degradation in NMOS. However, the effect of the |V

_{th}| reduction is inferior to that of the mobility degradation at a larger |V

_{GS}| in PMOS. Moreover, the I

_{DS}of PMOS is higher than that of NMOS at a larger |V

_{GS}|. The current degradation indicates that the higher current is more severely impacted by T

_{amb}. In addition, it is found that the zero-temperature coefficient bias point (V

_{ZTC}) occurs in PMOS, where the V

_{ZTC}represents the bias voltage point that the I

_{DS}is independent of the T

_{amb}[29]. In addition, there are two V

_{ZTC}under T

_{amb}= −50~25 °C range and T

_{amb}= 25~125 °C range.

_{amb}-dependent relation, Figure 5 shows that the I

_{DS}variations with different N

_{stack}s under the impact of T

_{amb}are extracted relative to the I

_{DS}at T

_{amb}= −50 °C, and the gate overdrive voltage (V

_{ov}= V

_{GS}− V

_{th}) is 0.43 V and −0.43 V for NMOS and PMOS, respectively. The I

_{DS}degradation of NMOS is lower than that of PMOS. At high T

_{amb}, The NMOS with N

_{stack}= 4 shows the largest I

_{DS}degradation, and other multiple stacks have minor differences. The devices with N

_{stack}= 2 have the lowest I

_{DS}degradation at high T

_{amb}in Figure 5a. PMOS shows a different trend when N

_{stack}increases, as shown in Figure 5b. The PMOS with N

_{stack}= 2 shows the largest I

_{DS}degradation, and other multiple stacks have minor differences. The PMOS with N

_{stack}= 32 shows the lowest I

_{DS}degradation. The I

_{DS}variation in NMOS with N

_{stack}= 4 and PMOS with N

_{stack}= 2 may be induced by random structure irregularities.

_{DS}variation, the temperature coefficients of I

_{DS}per stack (β) are extracted, as shown in Figure 6. Figure 6a shows that β in NMOS decreases in the negative direction under T

_{amb}above T

_{rt}when N

_{stack}is from 4 to 32. This is induced by the coupling mechanism with the impact of the SHE and T

_{amb}. As the N

_{stack}increases, the thermal crosstalk is enhanced in stacked nanosheets, where the thermal crosstalk is part of the SHE. The SHE can intensify phonon-electron scattering, and then counteract the partial effect of T

_{amb}, resulting in reduced I

_{DS}degradation. In Section 3.3, the simulation results will further verify the speculation. The β in NMOS with N

_{stack}= 2 is the lowest [Figure 6a]. This can be caused by difficult heat transport due to the smaller contact area between nanosheets and the S/D region, leading to severe thermal crosstalk. Meanwhile, the β under T

_{amb}below 0 °C is basically larger than that under T

_{amb}above T

_{rt}. This is because the impact of thermal crosstalk is weakened by enhanced heat transport ability.

_{amb}because the current density (J

_{DS}) in PMOS is larger than that in NMOS. The PMOS with N

_{stack}= 2 exhibits the largest β. This reverse behavior is due to the highest J

_{DS}in PMOS with N

_{stack}= 2 compared to NMOS. In addition, the difference of β when N

_{stack}= 4~32 is small. This is because the difference in J

_{DS}of PMOS is small, and thus the difference in thermal crosstalk is relatively insignificant.

_{th}(η) is extracted, as shown in Figure 7. The η in NMOS under T

_{amb}above T

_{rt}rapidly decreases in the negative direction with N

_{stack}first, and then the velocity of decrease gradually slows down [Figure 7a]. The η of NMOS with N

_{stack}= 16 is the lowest. This is because the thermal crosstalk becomes severe; therefore, the impact of T

_{amb}is mitigated. However, it increases when the N

_{stack}grows to 32. This can be explained by the heat transport ability that the contact area between nanosheets and S/D regions gradually increases with N

_{stack}, and then the enhanced thermal crosstalk effect is weakened. Therefore, the η with N

_{stack}= 32 increases. The η in NMOS under T

_{amb}below 0 °C rapidly decreases first, and then increases with N

_{stack}= 16. The η in PMOS exhibits a similar trend compared with that in NMOS [Figure 7b]. However, the η value is larger.

_{DS}variation and the η based on the temperature-dependent backscattering model is also further analyzed. In the temperature-dependent backscattering model [30,31], the I

_{DS}formula is defined using (1), and the linear relation of I

_{DS}and T

_{amb}is given using (2). Finally, the analytic expression for α concerning temperature is given using (3):

_{inj}is the inverse layer density near the source region; ν

_{th}is the thermal injection velocity at the thermal source; λ

_{0}is the mean-free path; l

_{0}is the critical distance when the carriers travel over a KT layer from the thermal source, where K and T are Boltzmann constant and temperature, respectively; and V

_{th0}is the threshold voltage at referenced temperature −50 °C. The α includes the backscattering coefficient term and the voltage-dependence term. In Figure 7, the η in PMOS is higher than that in NMOS significantly, and thus the second term of (3) becomes larger. This leads to a greater degradation of the I

_{DS}in PMOS compared to NMOS when T

_{amb}increases, as shown in Figure 5.

_{ZTC}of PMOS is extracted in Figure 8. It is shown that the V

_{ZTC}of PMOS decreases in the negative direction under T

_{amb}above T

_{rt}when N

_{stack}grows from 4 to 32. The result can be explained by the coupling mechanism with the impact of the SHE and T

_{amb}. As the N

_{stack}increases, the current variation comes to balance at lower |V

_{GS}| due to the effect of V

_{th}and mobility. However, the V

_{ZTC}under T

_{amb}below T

_{rt}is 0.1 V higher than that under higher T

_{amb}in the negative direction. This is because the SHE plays a lesser role in the case of T

_{amb}below T

_{rt}. Therefore, the effect of V

_{th}and mobility compensate at a higher V

_{GS}for the lower T

_{amb}. The investigation of V

_{ZTC}is useful to explore the working voltage in real applications.

#### 3.2. Electrothermal Performance of Different Gate Lengths with Different N_{stack}s under the Impact of T_{amb}

_{stack}s, as shown in Figure 9. As L

_{G}increases, the degradation of I

_{DS}becomes severe. This can be explained by the temperature-dependent backscattering model.

_{G}increases, the channel potential decreases, and then l

_{0}increases. Thus, the first term of (3) declines. This is an inverse result with the I

_{DS}degradation [Figure 9a]. Furthermore, the η is extracted, as shown in Figure 9b. The η increases in the negative direction as the L

_{G}increases at V

_{DS}= 0.9 V. Therefore, the I

_{DS}degradation is the result of both terms. At the same time, when the N

_{stack}increases at V

_{DS}= 0.9 V, the devices with L

_{G}= 30, 40 nm show that the η decreases in the negative direction first, then, increases, similar to the trend of devices with L

_{G}= 500 nm. Remarkably, when V

_{DS}= 0.9 V, the slope of η with N

_{stack}located in the 8 and 16 range is negative first, and then positive when the L

_{G}increases from 30 nm to 500 nm.

_{DS}degradation in short gate length devices at V

_{DS}= 0.9 V is higher than that at V

_{DS}= 0.1 V. The difference gradually becomes larger with T

_{amb}, and the device with L

_{G}= 30 nm has the largest difference. Figure 9b shows that the η increases in the negative direction as the V

_{DS}increases, and thus the second term of (3) becomes larger. Then, the λ

_{0}/l

_{0}also increases with larger V

_{DS}, and the first term of (3) becomes larger. Finally, the I

_{DS}degradation is higher with larger V

_{DS}.

#### 3.3. Simulation Verification

_{amb}is verified using the simulation method. To clarify the SHE clearly, the 16 nm gate length devices are simulated. The simulated devices are 3 nm node NSFETs, referring to [1]. The electrothermal parameters are set according to [32], where the L

_{G}, W

_{NS}, and T

_{NS}are set to 16, 20, and 6 nm, respectively. The nanosheets adopt three layers of vertically stacked structure. All simulations are performed using Sentaurus TCAD tools [33]. The SHE is calculated with the thermodynamic model (TD model). Figure 10a shows that the I

_{DS}with the SHE is lower than that without the SHE at larger V

_{GS}. At V

_{GS}= V

_{DS}= 0.7 V, the on-state I

_{DS}(I

_{ON}) degradation with the SHE is lower than that without the SHE as T

_{amb}increases, as shown in Figure 10b. The results indicate that the SHE weakened the impact of T

_{amb}. As the N

_{stack}increases, the η declines in the negative direction as shown in Figure 11. At the same time, the β decreases with N

_{stack}. This further verifies that the coupling heat counteracts the partial effect of T

_{amb}.

_{th}) and the maximum lattice temperature rise (∆T

_{max}) with respect to T

_{amb}are extracted. The R

_{th}is defined using (4), where total heat includes Joule heat, Peltier heat, Tompson heat, and recombination heat [34].

_{th}= ∆T

_{max}/total heat (K/μW)

_{max}and R

_{th}in the devices with N

_{stack}= 1 under T

_{amb}= 300 K are 149 K and 2.59 K/μW, respectively, as shown in Figure 12. In Figure 12a, the ∆T

_{max}decreases with T

_{amb}. However, the lattice temperature gradually increases. This explains why I

_{DS}with the SHE is lower at larger V

_{GS}[Figure 10a]. At the same time, the ∆T

_{max}increases when N

_{stack}is from 1 to 2 first, and then has a minor variation when N

_{stack}is from 2 to 4. This can be explained by the R

_{th}variation with N

_{stack}. In Figure 12b, the R

_{th}per stack decreases with T

_{amb}. This is because the ∆T

_{max}reduction ratio exceeds the I

_{ON}degradation. Then, the R

_{th}per stack increases when N

_{stack}is from 1 to 2, and then the rising speed increases when N

_{stack}is from 2 to 4. This is induced by the coupling effect. The rising R

_{th}causes an increase in lattice temperature, leading to a decrease in current density, eventually, the ∆T

_{max}variation is low when N

_{stack}is from 2 to 4 compared to that when N

_{stack}is from 1 to 2. In addition, when the T

_{amb}increases, the R

_{th}decreases significantly in the devices with N

_{stack}= 4 compared to that with N

_{stack}= 1 and 2. This is because the coupling heat is more severe in the devices with N

_{stack}= 4. These results verify that the SHE counteracts the partial effect of T

_{amb}.

## 4. Conclusions

_{amb}on the SHE in NSFET with different N

_{stack}s is investigated. The results show that the NMOS with N

_{stack}= 2 has the lowest I

_{DS}degradation, and the I

_{DS}degradation of PMOS with N

_{stack}= 32 is lower than that with N

_{stack}= 2. The results show that the I

_{DS}degradation is lowest in the NMOS with N

_{stack}= 2 and the PMOS with N

_{stack}= 32 when the T

_{amb}is at a high level. Due to the coupling mechanism with the impact of the SHE and T

_{amb}, the η exhibits a decrease trend first, and then an increase trend with N

_{stack}when the T

_{amb}is higher than T

_{rt}. Remarkably, the V

_{ZTC}of PMOS decreases with N

_{stack}> 4 in the negative direction when T

_{amb}is higher than T

_{rt}. Based on the backscattering theory, the I

_{DS}degradation ratio decreases when the L

_{G}becomes shorter. Meanwhile, the I

_{DS}degradation decreases at V

_{DS}= 0.1 V compared to that at V

_{DS}= 0.9 V in short gate length devices. Finally, the simulations verify that the SHE counteracts the partial effect of T

_{amb}. The work explores the electrothermal characteristics when NSFETs with different N

_{stack}s work under the impact of T

_{amb}and provides design guidelines for real applications.

## Author Contributions

## Funding

## Data Availability Statement

## Acknowledgments

## Conflicts of Interest

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**Figure 1.**(

**a**) Process flow of GAA NSFETs adopting the gate last process. (

**b**) Schematic of the NSFET with multiple lateral stacks along the nanosheet width direction.

**Figure 3.**The EDS images of NSFETs in this work. The top figures illustrate W, Si, and O elements. The middle figures illustrate Hf, Ti, and N elements. The bottom figures illustrate Al, Ta, and Ge elements. Ge has been removed completely.

**Figure 4.**Experimental temperature dependence of transfer characteristics at L

_{G}= 500 nm, N

_{stack}= 2, (

**a**) V

_{DS}= 0.9 V for NMOS and (

**b**) V

_{DS}= −0.9 V for PMOS. It shows two V

_{ZTC}under T

_{amb}= −50~25 °C range and T

_{amb}= 25~125 °C range.

**Figure 5.**(

**a**) I

_{DS}variations of NMOS with different N

_{stack}s under the impact of T

_{amb}relative to the I

_{DS}at T

_{amb}= −50 °C, (

**b**) I

_{DS}variations of PMOS with different N

_{stack}s under the impact of T

_{amb}relative to the I

_{DS}at T

_{amb}= −50 °C.

**Figure 6.**L

_{G}= 500 nm, (

**a**) V

_{DS}= 0.9 V, V

_{ov}= 0.59 V, the temperature coefficients of I

_{DS}per stack in NMOS, (

**b**) V

_{DS}= −0.9 V, V

_{ov}= −0.59 V, the temperature coefficients of I

_{DS}per stack in PMOS under different T

_{amb}ranges.

**Figure 7.**L

_{G}= 500 nm, the temperature coefficients of V

_{th}(η) with different N

_{stack}s in (

**a**) NMOS and (

**b**) PMOS under different T

_{amb}ranges.

**Figure 8.**L

_{G}= 500 nm, the V

_{ZTC}of PMOS with different N

_{stack}under T

_{amb}= −50–25 °C range and T

_{amb}= 25–125 °C range.

**Figure 9.**(

**a**) I

_{DS}variations with different gate lengths under the impact of T

_{amb}relative to the I

_{DS}at T

_{amb}= −50 °C. (

**b**) The temperature coefficients of V

_{th}with different gate lengths when the N

_{stack}increases.

**Figure 10.**(

**a**) The transfer characteristics of NSFET (N

_{stack}= 1) with/without the SHE as the T

_{amb}increases from 300 K to 400 K, (

**b**) I

_{DS}variations relative to the I

_{DS}at T

_{amb}= 300 K with/without the SHE when V

_{GS}= V

_{DS}= 0.7 V.

**Figure 11.**The temperature coefficients of V

_{th}and the temperature coefficients of I

_{DS}per stack with different N

_{stack}s.

**Figure 12.**When V

_{GS}= V

_{DS}= 0.7 V, (

**a**) ∆T

_{max}and (

**b**) R

_{th}variations relative to the devices with N

_{stack}= 1 under T

_{amb}= 300 K.

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## Share and Cite

**MDPI and ACS Style**

Zhao, P.; Cao, L.; Wang, G.; Wu, Z.; Yin, H.
The Impact of Ambient Temperature on Electrothermal Characteristics in Stacked Nanosheet Transistors with Multiple Lateral Stacks. *Nanomaterials* **2023**, *13*, 2971.
https://doi.org/10.3390/nano13222971

**AMA Style**

Zhao P, Cao L, Wang G, Wu Z, Yin H.
The Impact of Ambient Temperature on Electrothermal Characteristics in Stacked Nanosheet Transistors with Multiple Lateral Stacks. *Nanomaterials*. 2023; 13(22):2971.
https://doi.org/10.3390/nano13222971

**Chicago/Turabian Style**

Zhao, Peng, Lei Cao, Guilei Wang, Zhenhua Wu, and Huaxiang Yin.
2023. "The Impact of Ambient Temperature on Electrothermal Characteristics in Stacked Nanosheet Transistors with Multiple Lateral Stacks" *Nanomaterials* 13, no. 22: 2971.
https://doi.org/10.3390/nano13222971