# Design of Trench MIS Field Plate Structure for Edge Termination of GaN Vertical PN Diode

^{*}

## Abstract

**:**

## 1. Introduction

## 2. Device Structure

^{+}contact layer were set to be 1 × 10

^{19}cm

^{−3}and 2 µm, respectively. It is important to note that the thickness of the bottom contact layer does not significantly affect the breakdown voltage unless it is extremely thin.

^{+}layer had a doping concentration of 1 × 10

^{18}cm

^{−3}and a thickness of 0.4 µm. It is known that a typical highly doped p-type GaN layer has an electrical doping concentration of low 10

^{18}cm

^{−3}due to the incomplete activation issue [32,33,34,35,36]. Therefore, the thickness of the top P

^{+}layer must be carefully chosen to avoid punch-through at the breakdown condition. The doping concentration and thickness of the low-doped N

^{−}drift layer were 2.8 × 10

^{16}cm

^{−3}and 6.7 µm, respectively, to achieve the target breakdown voltage of 1 kV.

## 3. Boundary Conditions of Trench MIS FP

#### 3.1. Punch-Through under MIS FP

#### 3.2. Avalanche Breakdown at the Surface under FP Edge

#### 3.3. Dielectric Breakdown of MIS Region

## 4. Analytic Model

#### 4.1. Design Approach for Optimum Trench MIS FP

^{−}GaN drift region, ${V}_{s}$ is the surface potential of the trenched surface under MIS FP, and ${V}_{bi}$ is the built-in potential of the PN diode. The above relationship can be rewritten as:

#### 4.2. Interface Charge Effects

^{2}] and ${W}_{it}$ is the depletion width induced by the interface charges at the MIS interface. For example, when positive interface charges exist, the depletion width under the MIS interface decreases by ${W}_{D.MIS}-{W}_{it}$. As a result, the surface potential at the trenched MIS region decreases, and it can be expressed as:

^{11}, and 1 × 10

^{12}cm

^{−2}. Figure 6b shows the ratio between the dielectric layer thickness and trench depth, where the maximum limitation (${t}_{di}$/${t}_{td}$ = 1) is indicated as a boundary condition.

#### 4.3. Maximum Allowed Electric Fields in GaN Surface and Dielectric Layer

^{12}cm

^{−2}and the minimum dielectric thickness was determined using Equation (13). Figure 8a shows a comparison between TCAD and the calculated maximum electric field at the trenched GaN surface below the MIS FP edge versus ${t}_{td}$ where ${t}_{di}$ was the minimum dielectric layer thickness needed for ${t}_{td}$, obtained using Equation (13). The difference between TCAD and the calculation was not significant. The boundary condition for the critical electric field of GaN must be considered to determine the safe margin of ${t}_{td}$. In this study, the maximum allowed electric field for GaN was set to be 4 MV/cm as an example.

_{x}dielectric layer. In conclusion, the trench depth (${t}_{td}$) must be larger than approximately 1.1 µm based on Figure 8a,b, taking into account the maximum allowed electric field strengths for GaN and SiN

_{x}.

## 5. Design of GaN PN Diode with a Trench MIS FP Structure

## 6. Conclusions

## Author Contributions

## Funding

## Data Availability Statement

## Conflicts of Interest

## References

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**Figure 1.**(

**a**) Cross−sectional schematic of a vertical GaN PN diode with a trench MIS FP and (

**b**) structural variables of trench MIS FP; ${t}_{td}$ is the trench depth from the PN junction, ${t}_{di}$ is the dielectric layer thickness, and ${L}_{\mathit{fp}}$ is the lateral extension of FP.

**Figure 2.**Depletion profiles (

**a**) without and (

**b**) with the punch-through phenomenon and their potential distributions (

**c**) corresponding to (

**a**) and (

**d**) corresponding to (

**b**).

**Figure 3.**Example of electric field distribution in which the highest electric field occurs at the trenched GaN surface under the MIS FP edge.

**Figure 5.**Cross-section view of the vertical GaN PN diode with the positive interface charge between SiNx.

**Figure 6.**(

**a**) Minimum required dielectric layer thickness versus trench depth and (

**b**) ratio between minimum dielectric layer thickness and trench depth where the green line is the maximum limitation of the ratio.

**Figure 8.**Comparison between TCAD simulation and analytic model; (

**a**) maximum electric field in the dielectric layer under MIS FP. (

**b**) Maximum electric field at the trenched GaN surface below the MIS FP edge. The dashed lines are the safety margin of GaN and dielectric material.

**Figure 9.**(

**a**) Structures and electric field distributions of an ideal 1D vertical PN diode and a vertical PN diode with a proposed trench MIS FP, and (

**b**) breakdown characteristics obtained using the proposed trench MIS FP in comparison with an ideal 1D diode structure. The electric field distributions were simulated at a reverse bias voltage of 1080 V.

Structures | P^{+} GaN | N^{−} GaN | N^{+} GaN |
---|---|---|---|

Thickness (µm) | 0.4 | 6.7 | 2 |

Doping concentration (cm^{−3}) | 1 × 10^{18} | 2.8 × 10^{16} | 1 × 10^{19} |

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**MDPI and ACS Style**

Lee, S.-H.; Cha, H.-Y.
Design of Trench MIS Field Plate Structure for Edge Termination of GaN Vertical PN Diode. *Micromachines* **2023**, *14*, 2005.
https://doi.org/10.3390/mi14112005

**AMA Style**

Lee S-H, Cha H-Y.
Design of Trench MIS Field Plate Structure for Edge Termination of GaN Vertical PN Diode. *Micromachines*. 2023; 14(11):2005.
https://doi.org/10.3390/mi14112005

**Chicago/Turabian Style**

Lee, Sung-Hoon, and Ho-Young Cha.
2023. "Design of Trench MIS Field Plate Structure for Edge Termination of GaN Vertical PN Diode" *Micromachines* 14, no. 11: 2005.
https://doi.org/10.3390/mi14112005