# Efficient Surrogate Modeling and Design Optimization of Compact Integrated On-Chip Inductors Based on Multi-Fidelity EM Simulation Models

## Abstract

**:**

## 1. Introduction

## 2. Integrated On-Chip Inductors: Design Challenges and Simulation Models

#### 2.1. Integrated On-Chip Inductors: Typical Structures and Applications

#### 2.2. Computational Models of Integrated Inductors

**em**, this can be accomplished through the grid, meshing, and metal model settings [26]. Sonnet

**em**incorporates a surface meshing technique so that only the circuit metallization is sub-sectioned to the accuracy of the uniform fixed grid. In that regard, individual subsections cannot be smaller than the underlying grid itself, yet their exact size and placement are controlled by choosing from one of three meshing options. Fine meshing provides the highest accuracy but also demands the largest memory and processing time. The second option produces mesh on the edges of the structure and generates coarse subsections in the remaining parts of the circuit, which results in a good compromise between the speed and accuracy of EM analysis. The last option yields the least accurate results as the entire circuit is divided into large subsections, without distinguishing critical parts of the structure (e.g., edges). Finally, metal model settings enable modeling of thick metals by adding additional shunted metal layers to the original polygon, which allows for proper consideration of the coupling effects between closely separated conductors (e.g., interwinding capacitance).

**em**by using a fine grid, fine meshing and thick metal model for upper-layer winding. It should be reiterated that design optimization based exclusively on such a model is often prohibitive. To alleviate this problem, EM models of lower fidelity are obtained by compromising model accuracy with respect to its grid, meshing, and type of metal model. However, the influence of lesser model settings on its processing time and accuracy is not obvious and requires investigation. The latter was accomplished here by analyzing simulation results of a family of variable-fidelity EM models representing all available combinations of accuracy settings. The assessment of model speed and accuracy was conducted based on the simulation time as well as inductance and quality factor approximation errors (calculated using the relevant quantities of the high-fidelity model). The selected results of variable-fidelity EM model comparison are presented in Figure 3. The inspection of Figure 3 reveals the independent metal model, grid, and meshing effects for different EM model settings.

#### 2.3. Design Challenges

## 3. Efficient Surrogate Modeling and Design Optimization

#### 3.1. Design Case

**x**= [x

_{1}x

_{2}x

_{3}]

^{T}, include track width, track-to-track distance, and inner radius, respectively.

#### 3.2. Surrogate Modeling Using Response Surface Approximation and Space Mapping

**R**

_{f}, implemented in Sonnet

**em**by using a 0.5 × 0.5 grid (in microns), thick metal model and fine meshing (cf. Section 2.2), takes approximately 64 min to return single-frequency simulation data. On the other hand, the coarse-discretization EM model (denoted as

**R**

_{cd}) requires only 6 s to provide single-frequency results, being implemented on a coarser 2 × 2 grid (in microns), and using the thin metal model as well as coarse meshing.

_{B}= {

**x**

^{1},

**x**

^{2}, …,

**x**

^{N}} denote a base set, such that the responses

**R**

_{cd}(

**x**

^{j}) are known for j = 1, 2, …, N. Let

**R**

_{cd}(

**x**) = [R

_{cd}

_{.1}(

**x**) … R

_{cd.m}(

**x**)]

^{T}, where vector components correspond to complex admittance evaluated at m frequency points.

_{p}(

**x**) = µ + ε(

**x**), with µ denoting the mean of the response at base points, and ε being the error with zero expected value and a correlation structure depending on a generalized distance between the base points [31]. A Gaussian correlation function of the following form is used

_{k}are unknown hyper-parameters used to fit the model; x

_{k}

^{i}and x

_{k}

^{j}are the kth components of the base points

**x**

^{i}and

**x**

^{j}.

**R**

_{c}is defined as

**1**denotes an N-vector of ones,

**f**

_{j}= [R

_{cd.j}(

**x**

^{1}) … R

_{cd.j}(

**x**

^{N})]

^{T}, while

**r**= [R(

**x**,

**x**

^{1}) … R(

**x**,

**x**

^{N})] is the correlation vector between the point

**x**and base points, whereas

**R**= [R(

**x**

^{i},

**x**

^{j})]

_{i}

_{,j = 1,…,N}, is the correlation matrix between the base points. The mean ${\overline{\mu}}_{j}$ is given by

_{k}are found by maximizing $-[N\mathrm{ln}({\overline{\sigma}}^{2})+\mathrm{ln}|R|]/2$ , where |R| and the variance ${\overline{\sigma}}_{j}^{2}={({\mathit{f}}_{j}-1{\overline{\mu}}_{j})}^{T}{\mathit{R}}^{-1}({\mathit{f}}_{j}-1{\overline{\mu}}_{j})/N$ are functions of θ

_{k}[31].

**R**

_{cd}. Thus, it requires refinement to become a reliable surrogate

**R**

_{s}, i.e., an accurate representation of the high-fidelity model

**R**

_{f}. In the present work, this is accomplished by a combination of the input, frequency, and multiplicative output space mapping of the form

**R**

_{c}(

**x**;f

_{1}+ f

_{2}Ω) is the frequency scaled coarse model [32], where Ω is the frequency sweep, whereas

**F**= [f

_{1}f

_{2}]

^{T}are the scaling parameters of the affine transformation Ω ← f

_{1}+ f

_{2}Ω. The SM parameters are found by minimizing the expression ∑

_{k}

_{= 1,…,NSM}||

**R**

_{f}(

**x**

^{k.SM}) −

**A**⋅

**R**

_{f}(

**B**⋅

**x**

^{k.SM}+

**c**; f

_{1}+ f

_{2}Ω)|| w.r.t. the matrices

**A**,

**B**, and the vectors

**c**and

**F**. The base set X

_{B}

_{.SM}= {

**x**

^{1.SM},

**x**

^{2.SM}, …,

**x**

^{NSM.SM}} is allocated using star distribution (2n + 1 samples with n being the number of design parameters) [32].

**R**

_{cd}is not critical here and other types of approximation models could be implemented instead (e.g., artificial neural networks [33], support vector machines [34], rational functions [35], etc.). Most importantly, regardless of the data-driven modeling approach used here to create the coarse model

**R**

_{c}, it becomes a reliable surrogate

**R**

_{s}only after applying space mapping corrections as shown in (5).

#### 3.3. Numerical Results

**l**= [2 1 56]

^{T}μm, and

**u**= [16 7 140]

^{T}μm. In the first step, the kriging model is set up using 480

**R**

_{cd}samples allocated on a uniform rectangular 8 × 4 × 15 grid. The space-mapping-corrected version of the low-fidelity kriging model

**R**

_{c}is created as in (5) using 7 star-distributed

**R**

_{f}samples.

**R**

_{cd}simulation samples used for setting up the kriging model comprise the complex admittance Y

_{11}in the frequency range from 0.1 GHz to 10 GHz, which can be subsequently recalculated to obtain the actual figures of interest, i.e., inductance L and the quality factor Q [36].

**R**

_{s}and

**R**

_{f}are depicted in Figure 6. The relative RMS error acquired for 50 random test designs—for both the kriging model and the SM surrogate—is reported in Table 1. It can be observed that space mapping plays an extremely important role in improving the accuracy of the original kriging model. Additionally, the overall model accuracy is very good, especially considering its low setup cost (cf. Table 2). Note that each model evaluation typically requires six frequency points using adaptive band synthesis [26].

#### 3.4. Inductor Design Optimization Application Example

_{target}as well as maximizes the quality factor Q, both at a defined operating frequency f

_{0}. In addition, the peak frequency f

_{Q}

_{max}(the frequency corresponding to the maximum quality factor) should be moved to f

_{0}as close as possible, whereas the inductor layout area should be controlled by explicit constraints. It is also imperative that the final results are at the level of the high-fidelity model. With this in mind, the design problem can be formulated as

**R**

_{f}(

**x**) denotes the response vector of a high-fidelity EM model,

**x**is a vector of designable parameters, A(

**x**) is the circuit layout area, and A

_{max}is a user-defined maximum acceptable layout area. The objective function is defined according to the above specification as follows

_{target}and f

_{Q}

_{max}to f

_{0}. The penalty coefficients β

_{1}and β

_{2}are chosen so that the corresponding functions assume observable values (when compared to Q(

**x**)) for relative violations larger than a few percent. For the given example, penalty coefficients are set to 1000, however, this specific value is not critical. In addition to the above, the penalty functions are continuous and differentiable with respect to the given performance figures, which is a major advantage from the optimization standpoint.

**R**

_{f}. For the sake of computational efficiency, an iterative SBO formulation can be utilized. In more detail, to account for the non-zero error of the surrogate model, the additive output space mapping algorithm [30] is applied to perform inductor optimization as given below:

_{0}= 4.2 GHz, while obtaining L

_{target}= 4 nH at f

_{0}. In addition, the process (8) is constrained by A

_{max}= 28,000 μm

^{2}. The lower and upper bounds of the feasible design space

**lb**,

**ub**, the initial design

**x**

^{(}^{0)}(set in the center of the domain) as well as the final design

**x*** are summarized in Table 3.

**x**

^{(0)}relatively differs from L

_{target}by about 35%, which is the reason for executing the optimization procedure. The final design

**x*** was obtained in two iterations of (8), which means that only two high-fidelity EM simulations of the considered coil were conducted. The final inductor performance is shown in Figure 7. Table 4 provides detailed data on the structure of interest at the optimized design. One should note that the optimization process was restricted to the simulation grid of the high-fidelity EM model (i.e., 0.5 μm × 0.5 μm), which obviously limits the resolution of the design and does not allow for more precise satisfaction of the specifications or the quality factor improvement.

## 4. Multi-Fidelity Design Optimization of Compact On-Chip Inductors

#### 4.1. Design Case

#### 4.2. Multi-Fidelity Optimization Algorithm

**R**

_{c.j}}, j = 1, …, K, where

**R**

_{c.j}

_{+1}is finer than

**R**

_{c.j}, which translates into better accuracy, but also a longer processing time. As opposed to lumped-element equivalent circuits that are currently widely used for design optimization of planar inductors, variable-fidelity EM models offer relatively good prediction and generalization capabilities [38]. In this work, all {

**R**

_{c.j}} models are implemented and evaluated using Sonnet (see Section 2.2 for details on the definition of a low-fidelity EM model).

**x**

^{(0)}, the coarse-discretization EM model of the lowest fidelity,

**R**

_{c.}

_{1}, is optimized to arrive at

**x**

^{(1)}, which represents the first approximation of the high-fidelity model optimum

**x**

_{f}*. Having obtained

**x**

^{(1)}, it is subsequently used as the starting point for optimization of another model in the line to produce an even more accurate approximation of

**x**

_{f}*. This is repeated in a sequence until the optimum

**x**

^{(K)}of the finest among coarse-discretization EM models,

**R**

_{c.K}, is found. Normally, only a few

**R**

_{c}models are needed for fast convergence of the algorithm under discussion. In this work, the process can be effectively accomplished with K = 2. Additionally, a pattern search algorithm [39] is used here to optimize all coarse-discretization EM models. Having obtained the optimized design x

^{(K)}of the finest coarse-discretization model

**R**

_{c.K}, it is evaluated at perturbed designs around

**x**

^{(K)}, i.e., at

**x**

_{k}

^{(K)}= [x

_{1}

^{(K)}… x

_{k}

^{(K)}+ sign(k)·d

_{k}… x

_{n}

^{(K)}]

^{T}, k = −n, −n+1, …, n − 1, n. Notation

**R**

^{(k)}=

**R**

_{c.K}(

**x**

_{k}

^{(K)}) is used here. These data are applied to refine the finest approximate design without directly optimizing

**R**

_{f}. The latter is omitted by setting up an approximation model based on

**R**

^{(k)}, and optimizing it in the neighborhood of

**x**

^{(K)}defined as [

**x**

^{(K)}−

**d**,

**x**

^{(K)}+

**d**], where

**d**= [d

_{1}d

_{2}… d

_{n}]

^{T}. The approximation is performed using a reduced quadratic model q(

**x**) = [q

_{1}q

_{2}… q

_{m}]

^{T}, defined as [40]

_{j.r}can be found analytically [37] by solving a system of linear regression problems of the form q

_{j}(

**x**

_{k}

^{(K)}) =

**R**

_{c.K}(

**x**

_{k}

^{(K)}) for k = −n, …, 0, …, n. In the final step, the refined design is found as:

**q**(

**x**

^{(K)}) =

**R**

_{f}(

**x**

^{(K)}) −

**R**

_{c.K}(

**x**

^{(K)}) accounts for misalignment between

**R**

_{c.K}and

**R**

_{f}[37]. The optional frequency scaling of

**q**is also possible to account for frequency shift between

**R**

_{c.K}and

**R**

_{f}[41]. If necessary, step (10) can be repeated starting from a refined design, i.e.,

**x*** = argmin{

**x**

^{(K)}−

**d**≤

**x**≤

**x**

^{(K)}+

**d**: U(

**q**(

**x**) + Δ

**q**(

**x***) (constraint placed on A(

**x**) is omitted here for the sake of clarity). Note that each iteration requires only one evaluation of the high-fidelity EM model

**R**

_{f}.

#### 4.3. Numerical Results

**R**

_{f}was set up as described in Section 3.2. In addition, two coarse-discretization EM models—

**R**

_{c}

_{1}and

**R**

_{c}

_{2}—were defined by using 2 μm × 2 μm and 1 μm × 1 μm grids, respectively, as well as the thin metal model and coarse meshing. Their respective simulation times are 60 s and 150 s.

_{0}= 3.25 GHz while reaching L

_{target}= 3.49 nH at the same frequency. An additional objective is to keep the inductor’s layout area below or equal to A

_{max}= 13,000 μm

^{2}. The bounds of the search space, as well as the starting point for the optimization process

**x**

^{(0)}, are collected in Table 5. The initial design exhibits an inductance of 4.55 nH at the operating frequency, which is relatively 30% off from the target value of 3.49 nH.

**x*** reaches the specified inductance at the operating frequency and the quality factor of 14.1 at f

_{0}. This result was obtained at the total cost of six evaluations of

**R**

_{f}(including three iterations of the refinement procedure (10), cf. Table 6 for a detailed cost breakdown). The cost-efficiency of the presented method can be highlighted when compared against alternative design routines that include: (i) direct derivative-free optimization of the

**R**

_{f}model using a pattern search algorithm [39], (ii) exhaustive enumeration, (iii) customized enumeration and (iv) implicit space mapping with geometric programming [19]. The results obtained by the presented method as well as alternative approaches (i–iv) listed above are compared in Table 7. The first alternative approach considered in the comparison yields the same final design as the one obtained by the method presented in Section 4,

**x***

_{(i)}=

**x***. However, this solution is identified at the cost of 42 evaluations of the high-fidelity model

**R**

_{f}, which demonstrates a 7-fold speedup of the presented method when compared to a standard EM-driven optimization routine of [39]. In exhaustive enumeration, sampling of the domain using 2 μm, 1 μm, and 0.5 μm step sizes for every design dimension translates into 1376, 8925, and 63,713 EM model simulations, which is clearly intractable in a reasonable time frame, yet guarantees finding the actual discreet optimum. In the customized enumeration of (iii), developed for comparison purposes, the process begins with selecting a pool of candidate solutions from the complete set of designs obtained by sampling the search space with a medium step of 1 μm; the candidate solutions are chosen based on their footprint area subject to a user-defined constraint of ≤ Amax and ≥ γ%·Amax (here, γ = 99) and are subsequently simulated using

**R**

_{c}

_{2}coarse-discretization EM model. The candidate pool is further narrowed down by selecting those designs whose inductance satisfies L

_{target}± δ

_{L}

_{target}, where deviation δ

_{Ltarget}is picked by the user to account for EM model inaccuracy (here, δ

_{Ltarget}= 15%). Finally, the pool of candidate solutions is expanded iteratively by producing new designs in the vicinity of the base solutions by changing every single parameter by ±0.5 μm, with designs that violate A

_{max}constraint or lower/upper bounds being discarded from the pool. The EM-verification of the first-iteration candidate pool requires 18

**R**

_{f}simulations, whereas the next one involves additional 59

**R**

_{f}simulations. This corresponds to the cost of finding the first-iteration optimum

**x**

^{(1)}

_{(iii)}and the second-iteration optimum

**x**

^{(2)}

_{(iii)}, respectively. The last method included here as a benchmark is an implicit space mapping (ISM) algorithm with an approximate circuit-model-based geometric programming objective function formulation of [19]. The ISM approach produces a satisfactory design

**x***

_{(iv)}at the cost of eight EM simulations, which is the second most efficient way of reaching a comparable design solution included in method comparison (cf. Table 7).

## 5. Discussion and Conclusions

## Funding

## Conflicts of Interest

## References

- Leroux, P.; Steyaert, M. High-performance 5.2 GHz LNA with on-chip inductor to provide ESD protection. Electron. Lett.
**2001**, 37, 467–469. [Google Scholar] [CrossRef] - Lin, K.-C.; Chiou, H.-K.; Wu, P.-C.; Chen, W.-H.; Ko, C.-L.; Juang, Y.-Z. 2.4-GHz Complementary Metal Oxide Semiconductor Power Amplifier Using High-Quality Factor Wafer-Level Bondwire Spiral Inductor. IEEE Trans. Compon. Packag. Manuf. Technol.
**2013**, 3, 1286–1292. [Google Scholar] [CrossRef] - Chen, C.-H.; Chiang, P.-Y.; Jou, C.F. A Low Voltage Mixer with Improved Noise Figure. IEEE Microw. Wirel. Compon. Lett.
**2009**, 19, 92–94. [Google Scholar] [CrossRef] - Grau, G.; Langmann, U.; Winkler, W.; Knoll, D.; Osten, J.; Pressel, K. A Current-Folded Up-Conversion Mixer and VCO with Center-Tapped Inductor in a SiGe-HBT Technology for 5-GHz Wireless LAN Applications. IEEE J. Solid-State Circuits
**2000**, 35, 1345–1352. [Google Scholar] [CrossRef] - Aguilera, J.; Berenguer, R. Design and Test of Integrated Inductors for RF Applications; Kluwer Academic Publishers: New York, NY, USA, 2004. [Google Scholar]
- Lopez-Villegas, J.; Samitier, J.; Cane, C.; Losantos, P.; Bausells, J. Improvement of the Quality Factor of RF Integrated Inductors by Layout Optimization. IEEE Trans. Microw. Theory Tech.
**2000**, 48, 76–83. [Google Scholar] [CrossRef] [Green Version] - Yue, C.P.; Wong, S.S. On-chip spiral inductors with patterned ground shields for Si-based RF IC’s. IEEE J. Solid-State Circuits
**1998**, 33, 743–752. [Google Scholar] [CrossRef] - Wojnowski, M.; Issakov, V.; Knoblinger, G.; Pressel, K.; Sommer, G.; Weigel, R. High-Q Inductors Embedded in the Fan-Out Area of an Ewlb. IEEE Trans. Compon. Packag. Manuf. Technol.
**2012**, 2, 1280–1292. [Google Scholar] [CrossRef] - Cao, Y.; Groves, R.A.; Huang, X.; Zamdmer, N.D.; Plouchart, J.-O.; Wachnik, R.A.; King, T.-J.; Hu, C. Frequency-Independent Equivalent-Circuit Model for On-Chip Spiral Inductor. IEEE J. Solid-State Circuits
**2003**, 38, 419–426. [Google Scholar] [CrossRef] - Arcioni, P.; Castello, R.; Perregrini, L.; Sacchi, E.; Svelto, F. An Innovative Modelization of Loss Mechanism in Silicon Integrated Inductors. IEEE Trans. Circuits Syst.–II Analog. Digit. Signal Process.
**1999**, 46, 1453–1460. [Google Scholar] [CrossRef] - Fakhfakh, M.; Tlelo-Cuautle, E.; Siarry, P. Computational Intelligence in Analog and Mixed-Signal (AMS) and Radio-Frequency (RF) Circuit Design; Springer: Berlin/Heidelberg, Germany, 2015. [Google Scholar]
- Niknejad, A.M.; Meyer, R.G. Analysis, Design, and Optimization of Spiral Inductors and Transformers for Si RF IC’s. IEEE J. Solid-State Circuits
**1998**, 33, 1470–1481. [Google Scholar] [CrossRef] [Green Version] - Aguilera, J.; de Nó, J.; García-Alonso, A.; Oehler, F.; Hein, H.; Sauerer, J. A guide for on-chip inductor design in a conventional CMOS process for RF applications. Appl. Microw. Wirel.
**2001**, 13, 56–65. [Google Scholar] - Koutsoyannopoulos, Y.K.; Papananos, Y. Systematic Analysis and Modeling of Integrated Inductors and Transformers in RF IC Design. IEEE Trans. Circuits Syst.–II Analog. Digit. Signal Process.
**2000**, 47, 699–713. [Google Scholar] [CrossRef] [Green Version] - Hershenson, M.; Mohan, S.S.; Boyd, S.P.; Lee, T.H. Optimization of Inductor Circuits via Geometric Programming. In Proceedings of the 36th Design Automation Conference, New Orleans, LA, USA, 21–25 June 1999; pp. 994–998. [Google Scholar]
- Zhan, Y.; Sapatnekar, S.S. Optimization of Integrated Spiral Inductors Using Sequential Quadratic Programming. In Proceedings of the Design, Automation and Test in Europe Conference and Exhibition, Paris, France, 16–20 February 2004; pp. 622–627. [Google Scholar]
- Nieuwoudt, A.; Massoud, Y. Multi-level approach for integrated spiral inductor optimization. In Proceedings of the 42th Design Automation Conference, San Diego, CA, USA, 13–17 June 2005; pp. 648–651. [Google Scholar]
- Koziel, S.; Leifsson, L. Surrogate-Based Modeling and Optimization: Applications in Engineering; Springer: Berlin/Heidelberg, Germany, 2013. [Google Scholar]
- Yu, W.; Bandler, J.W. Optimization of spiral inductor on silicon using space mapping. In Proceedings of the 2006 IEEE MTT-S International Microwave Symposium Digest, San Francisco, CA, USA, 11–16 June 2006; IEEE: New York, NY, USA, 2006; pp. 1085–1088. [Google Scholar]
- Bandler, J.W.; Cheng, Q.S.; Nikolova, N.K.; Ismail, M.A. Implicit space mapping optimization exploiting preassigned parameters. IEEE Trans. Microw. Theory Tech.
**2004**, 52, 378–385. [Google Scholar] [CrossRef] - Koziel, S.; Cheng, Q.S.; Bandler, J.W. Space mapping. IEEE Microw. Mag.
**2008**, 9, 46–57. [Google Scholar] [CrossRef] - Kurgan, P.; Koziel, S.; Bandler, J.W. Low-cost EM-driven surrogate modeling and optimization of planar inductors. In Proceedings of the 2015 IEEE MTT-S International Microwave Symposium, Phoenix, AZ, USA, 17–22 May 2015; IEEE: New York, NY, USA, 2015; pp. 1–3. [Google Scholar]
- Caverly, R. CMOS RFIC Design Principles; Artech House: Norwood, MA, USA, 2007. [Google Scholar]
- Hella, M.M.; Ismail, M. RF CMOS Power Amplifiers: Theory, Design and Implementation; Kluwer Academic Publishers: New York, NY, USA, 2002. [Google Scholar]
- Koziel, S.; Yang, X.S.; S, X.; Zhang, Q.J. Simulation-Driven Design Optimization and Modeling for Microwave Engineering; College Press: Imperial, UK, 2012. [Google Scholar]
- Sonnet Em, Version 14.54; Sonnet Software: North Syracuse, NY, USA, 2013.
- Bunch, R.L.; Sanderson, D.I.; Raman, S. Quality Factor and Inductance in Differential IC Implementations. IEEE Microw. Mag.
**2002**, 3, 82–92. [Google Scholar] [CrossRef] - Murphy, O.H.; McCarthy, K.G.; Delabie, C.J.P.; Murphy, A.C.; Murphy, P.J. Design of multiple-metal stacked inductors incorporating an extended physical model. IEEE Trans. Microw. Theory Tech.
**2005**, 53, 2063–2072. [Google Scholar] [CrossRef] - Haobijam, G.; Paily, R. Efficient optimization of integrated spiral inductor with bounding of layout design parameters. Analog. Integr. Circuits Signal Process.
**2007**, 51, 131–140. [Google Scholar] [CrossRef] - Koziel, S.; Bandler, J.W.; Madsen, K. Towards a rigorous formulation of the space mapping technique for engineering design. IEEE Int. Symp. Circuits Syst.
**2005**, 1, 5605–5608. [Google Scholar] - Queipo, N.V.; Haftka, R.T.; Shyy, W.; Goel, T.; Vaidynathan, R.; Tucker, P.K. Surrogate based analysis and optimization. Prog. Aerosp. Sci.
**2005**, 41, 1–28. [Google Scholar] [CrossRef] [Green Version] - Cheng, Q.S.; Koziel, S.; Bandler, J.W. Simplified space mapping approach to enhancement of microwave device models. Int. J. RF Microw. Comput.-Aided Eng.
**2006**, 16, 518–535. [Google Scholar] [CrossRef] - Liu, T.; Zhang, W.; Yu, Z. Modeling of spiral inductors using artificial neural network. In Proceedings of the IEEE International Joint Conference on Neural Networks, Montreal, QC, Canada, 31 July–4 August 2005; pp. 2353–2358. [Google Scholar]
- Wang, Y.; Franzon, P.D. RFIC IP redesign and reuse through surrogate based machine learning method. In Proceedings of the 2018 IEEE MTT-S International Conference on Numerical Electromagnetic and Multiphysics Modeling and Optimization, Reykjavik, Iceland, 8–10 August 2018; pp. 1–4. [Google Scholar]
- Wang, H.; Sun, L.; Liu, J.; Zou, H.; Yu, Z.; Gao, J. Transfer function analysis and broadband scalable model for on-chip spiral inductors. IEEE Trans. Microw. Theory Techn.
**2011**, 59, 1696–1708. [Google Scholar] [CrossRef] - Sanderson, D.I.; Rautio, J.C.; Groves, R.A.; Raman, S. Accurate modeling of monolithic inductors using conformal meshing for reduced computation. IEEE Microw. Mag.
**2003**, 4, 87–96. [Google Scholar] [CrossRef] - Koziel, S.; Ogurtsov, S. Robust multi-fidelity simulation-driven design optimization of microwave structures. In Proceedings of the 2010 IEEE MTT-S International Microwave Symposium Digest, Anaheim, CA, USA, 23–28 May 2010; pp. 201–204. [Google Scholar]
- Koziel, S.; Bandler, J.W.; Madsen, K. Quality assessment of coarse models and surrogates for space mapping optimization. Optim. Eng.
**2008**, 9, 375–391. [Google Scholar] [CrossRef] - Koziel, S. Computationally efficient multi-fidelity multi-grid design optimization of microwave structures. Appl. Comput. Electromagn. Soc. J.
**2010**, 25, 578–586. [Google Scholar] - Koziel, S.; Ogurtsov, S. Microwave design optimization using local response surface approximations and variable-fidelity electromagnetic models. Int. J. RF Microw. Comput.-Aided Eng.
**2013**, 23, 349–356. [Google Scholar] [CrossRef] - Bandler, J.W.; Cheng, Q.S.; Dakroury, S.A.; Mohamed, A.S.; Bakr, M.H.; Madsen, K.; Sondergaard, J. Space mapping: The state of the art. IEEE Trans. Microw. Theory Tech.
**2004**, 52, 337–361. [Google Scholar] [CrossRef] - Deb, K. Multi-Objective Optimization Using Evolutionary Algorithms; Wiley: New York, NY, USA, 2001. [Google Scholar]
- Koziel, S.; Kurgan, P. Expedited EM-driven generation of Pareto-optimal trade-off curves for variable-turn on-chip inductors. IET Microw. Antennas Propag.
**2018**, 12, 1205–1210. [Google Scholar] [CrossRef] - Koziel, S.; Kurgan, P. Rapid multi-objective design of integrated on-chip inductors by means of Pareto front exploration and design extrapolation. J. Electromagn. Waves Appl.
**2019**, 33, 1416–1426. [Google Scholar] [CrossRef] - Hermannsson, E.; Leifsson, L.; Koziel, S.; Kurgan, P.; Bekasiewicz, A. Trawl-door shape optimization with 3D CFD models and local surrogates. In Proceedings of the 4th International Conference on Simulation and Modeling Methodologies, Technologies and Applications, Vienna, Austria, 28–30 August 2014. [Google Scholar]

**Figure 1.**Typical on-chip inductors: (

**a**) rectangular coil in single-ended configuration, (

**b**) octagonal coil of differential type, and (

**c**) circular coil in unbalanced configuration. Windings, undercrossing, and vias are represented in the picture by dark gray, light gray, and black colors, respectively.

**Figure 2.**Examples of EM models of graduated complexity of a rectangular 4-turn, 1-layer coil. From left to right: coarse model without edge meshing, routed on a 2 × 2 grid; coarse model with edge meshing on a 1 × 1 grid, and fine model created on a 0.5 × 0.5 grid. Grid dimensions are in microns.

**Figure 3.**Comparative analysis of variable-fidelity EM models of a rectangular 4-turn upper-layer inductor realized in a differential configuration (cf. Figure 2). Key model performance parameters are: inductance approximation error (δ

_{L}), quality factor approximation error (δ

_{Q})—both calculated for the peak frequency—and simulation time. Figures (

**a**–

**c**) showcase simulation results for EM models with grid fixed to 1 × 1 (in microns) and different mesh settings: coarse (no edge) mesh (○), coarse mesh (△), and fine mesh (Δ). Figures (

**d**–

**f**) present simulation data obtained for models with a fixed thin metal model. Models with different mesh settings are marked identically as for Figures (

**a**–

**c**). Figures (

**g**–

**i**) compare EM models whose metal is approximated by a thin model. Different curves denote different grid settings: 2 × 2 (○), 1 × 1 (Δ), and 0.5 × 0.5 (□)–all dimensions in microns.

**Figure 5.**The 65-nm CMOS technology stack used in this work. Inductor windings are routed using M7 metal layer, whereas layer M6 is used for undercrossing (M7 and M6 are connected with vias).

**Figure 6.**Frequency characteristics of the on-chip inductor at the selected test points: surrogate model

**R**

_{s}(○) and high-fidelity EM model

**R**

_{f}(-).

**Figure 7.**Responses of the compact integrated on-chip inductor at the initial (dashed, ---) and final (solid, -) design solutions. The horizontal and vertical red lines denote the target inductance and the operating frequency f

_{0}, respectively.

**Figure 8.**Frequency characteristics of the on-chip inductors designed by different methods: this work (black), 1st iteration of customized enumeration (green), 2nd iteration of customized enumeration (blue), ISM (violet). Horizontal and vertical solid red lines denote the target inductance and the operating frequency, respectively.

Model | Relative RMS Error [%] | |
---|---|---|

Inductance L | Quality Factor Q | |

R_{c}^{1} | 17.0 | 15.3 |

R_{s}^{2} | 10.5 | 6.8 |

^{1}Coarse model developed using kriging interpolation based on coarse-mesh simulation data.

^{2}Surrogate model developed by correcting

**R**

_{c}using space mapping technology.

Modeling Stage | Number of Model Evaluations | Computational Cost | |
---|---|---|---|

Absolute [h] | Relative to R_{f} | ||

Kriging Coarse Model | 480 × R_{cd} | 4.8 | 0.75 |

Space Mapping Corrections | 7 × R_{f} | 44.8 | 7 |

Total cost | n/a | 49.6 | 7.75 |

x_{1} [μm] | x_{2} [μm] | x_{3} [μm] | |

Lower bounds: lb | 2 | 1 | 56 |

Upper bounds: ub | 16 | 7 | 140 |

Initial design: x^{(0)} | 9.0 | 4.0 | 98.0 |

Final design: x* | 7.5 | 3.5 | 86.0 |

Design Specifications | L, Q, and Maximum-Q Frequency at the Final Design | |||
---|---|---|---|---|

L_{target} | f_{0} | L | Q | f_{Q}_{max} |

4 nH | 4.2 GHz | 4 nH | 14.5 | 3.85 GHz |

x_{1} [μm] | x_{2} [μm] | x_{3} [μm] | |

Lower bounds: lb | 2 | 1 | 56 |

Upper bounds: ub | 16 | 7 | 140 |

Initial design: x^{(0)} | 9.0 | 4.0 | 98.0 |

Algorithm Step | Number of Model Evaluations | Computational Cost | |

Absolute [min] | Relative toR_{f} | ||

Optimization of R_{c}_{.1} | 20 × R_{c.}_{1} | 20 | 0.31 |

Optimization of R_{c}_{.2} | 22 × R_{c.}_{2} | 55 | 0.86 |

Setup of model q^{1} | 3 × 7 × R_{c.}_{2} | 53 | 0.83 |

Evaluation of R_{f} | 4 × R_{f} | 256 | 4 |

Total cost | n/a | 384 | 6 |

^{1}

**q**was set up three times (one for each refinement iteration).

Method | Final Design | L @ f_{0} | Q @ f_{0} | f_{Qmax} | Layout Area | CPU Cost(Relative to R_{f}) |

This work | x* = [3.5 1 79.5]^{T} | 3.49 nH | 14.1 | 3.0 GHz | 12,882 μm^{2} | 6 |

Pattern search algorithm | x*_{(i)} = [3.5 1 79.5]^{T} | 3.49 nH | 14.1 | 3.0 GHz | 12,882 μm^{2} | 42 |

Customized Enumeration ^{1} | x^{(1)}_{(iii)} = [3 1.5 78]^{T} | 3.32 nH | 13.3 | 3.2 GHz | 12,321 μm^{2} | 18.78 |

x^{(2)}_{(iii)} = [2 2 80]^{T} | 3.48 nH | 12.9 | 3.37 GHz | 11,664 μm^{2} | 77.78 | |

ISM with GP | x*_{(iv)} = [2 3 79.5]^{T} | 3.44 nH | 12.8 | 3.44 GHz | 12,882 μm^{2} | 8 |

^{1}Exhaustive enumeration of (ii) was not executed due to excessive CPU cost; for the same reason, customized enumeration was terminated after the second iteration.

Ref. | Number of Turns | Specifications | Inductor Performance and Area | ||||

L_{target} | f_{0} | A_{max} | L @ f_{0} | Q @ f_{0} | Layout Area | ||

[43] | 3 ^{1} | 3.49 nH | 3.25 GHz | – | 3.49 nH | 16.6 | 37,488 μm^{2} |

[44] | 3.5 ^{2} | 3.50 nH | 3.25 GHz | – | 3.50 nH | 16.3 | 30,002 μm^{2} |

[43] | 4 ^{1} | 3.49 nH | 3.25 GHz | – | 3.50 nH | 15.7 | 27,001 μm^{2} |

This work | 4 ^{1} | 3.49 nH | 3.25 GHz | 13,000 μm^{2} | 3.49 nH | 14.1 | 12,882 μm^{2} |

[43] | 5 ^{1} | 3.49 nH | 3.25 GHz | – | 3.50 nH | 12.5 | 6989 μm^{2} |

^{1}1-layer rectangular spiral inductor in a differential configuration.

^{2}1-layer rectangular spiral inductor in a single-ended configuration.

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## Share and Cite

**MDPI and ACS Style**

Kurgan, P.
Efficient Surrogate Modeling and Design Optimization of Compact Integrated On-Chip Inductors Based on Multi-Fidelity EM Simulation Models. *Micromachines* **2021**, *12*, 1341.
https://doi.org/10.3390/mi12111341

**AMA Style**

Kurgan P.
Efficient Surrogate Modeling and Design Optimization of Compact Integrated On-Chip Inductors Based on Multi-Fidelity EM Simulation Models. *Micromachines*. 2021; 12(11):1341.
https://doi.org/10.3390/mi12111341

**Chicago/Turabian Style**

Kurgan, Piotr.
2021. "Efficient Surrogate Modeling and Design Optimization of Compact Integrated On-Chip Inductors Based on Multi-Fidelity EM Simulation Models" *Micromachines* 12, no. 11: 1341.
https://doi.org/10.3390/mi12111341