To evaluate the reasonableness of the parameter settings with MATLAB/Simulink 2020b software, an in-group equalization circuit simulation model with two batteries was developed, and the key parameter settings are listed in Table 3
. The model includes a battery module, an SOC estimation module, a double-layer switch selection module, a BCEQ, and a VFPID control module. The S-Function function, Fuzzy module, PID controller, and PWM output module consist of the VFPID unit. The S-Function function module approximates the
of the module’s power packs, as well as the variance among adjacent power packs
, and the PWM output module regulates the switch
on and off in the BCEQ.
4.1. Equilibrium Topology Validation
To verify the performance of the theoretical topology, circuit models were built for the bidirectional Cuk circuit equalization circuit according to the literature in [27
] (Pattern 1), the composite equalization architecture based on the Cuk circuit literature in [28
] (Pattern 2), the equalization converter with a coupled inductor based on the literature in [29
] (Pattern 3), and the BCEQ proposed in this paper (Pattern 4); their equalization results in the three phases of resting, charging, and discharging were tested, as shown in Figure 10
and Figure 11
The initial SOC settings for each cell at quiescence are 75%, 73%, 72%, 70%, 68%, and 67%. As can be seen in Figure 10
, the four circuits take 1269 s, 972 s, 1158 s, and 843 s to reach the equilibrium state, while the architecture proposed in this work takes the shortest times of 33.6%, 13.3% and 27.2%, respectively. Pattern 1 has the longest equalization path because it can only transmit energy between nearby cells, which results in the slowest equalization and increased energy loss. Both pattern 1 and pattern 2 have inductive structures with high circuit sizes, which increases power losses due to cell resistance values. Pattern 3 uses coupled inductors to share a single core, which reduces circuit energy losses, but its structure can only transmit energy between nearby cells, and in addition, the equalization results are not preferred. The proposed topology 4 uses coupled inductors to reduce energy losses, and it incorporates switching tubes to allow energy transmission between any number of individual cells, which significantly shortens the equalization path and equalizes
, and after the relative equilibrium was reached within the pattern in about 200s, the intermodule equilibrium was started. It is worth noting that the pattern in this paper performs intramodule equalization as well as intermodule cell equalization, which further improves the equalization speed compared with the hierarchical Pattern 2, and therefore has the highest efficiency, as well as the extreme SOC difference values of 0.24%, 0.13%, 0.17%, and 0.09% for each cell in the four patterns after equalization, respectively. Regarding patterns 1, 2, and 3, the pattern suggested in this paper reduces the energy loss by 4.3%, 3.9%, and 4.2%, respectively.
During charging, the original SOC values for each cell are set to 58%, 57%, 56%, 55%, 54%, and 53%, and as seen in Figure 11
, the four circuits take 1258 s, 961 s, 1141 s, and 821 s to reach the equilibrium state, respectively, and the architecture provided in this work reduces the time by 34.7%, 14.6%, and 28%, respectively. After equilibrium, the values of the battery SOC polarization for the four patterns are 0.21%, 0.15%, 0.19%, and 0.11%, respectively, and the proposed pattern reduces the energy loss by 4.0%, 3.8%, and 3.9%, respectively.
The initial SOCs of each cell in the discharged state are set to 62%, 61%, 60%, 59%, 58%, and 57%, and it can be seen from Figure 12
that the four circuits take 1271 s, 989 s, 1159 s, and 849 s to reach the equilibrium state, and the architecture provided in this work reduces the equilibrium time by approximately 33.2%, 14.2%, and 26.7%. After equilibrium, the extreme SOC difference values for each cell are 0.23%, 0.14%, 0.21%, and 0.10%, respectively, and the pattern given in this study reduces the energy loss by 3.8%, 3.5%, and 3.7%, respectively. In conclusion, the structure proposed in this paper is ideal in all three states. For a more visual presentation, the experimental data of the four patterns after equilibrium are listed in Table 4
, Table 5
and Table 6
, which show that the proposed framework can effectively solve the problem of inconsistency in the power group. Figure 13
depicts the comparison findings for each mode after equalization.
To evaluate the topologies proposed in this paper more comprehensively, we also investigated the construction costs of the four topologies concerning the market price of electronic components in 2022, assuming the same price for the production cost of other measurement instruments, such as voltage and temperature, and taking a cell pack with 32 cells forming four modules as an example; the comparison results are shown in Table 7
. Compared with other topologies, the structure proposed in this study reduces more than half of the capacitor and inductor components, despite the higher number of switches, and its overall cost is in the acceptable range. The price of the large-scale battery pack in the actual vehicle, with the increased use of capacitors and inductors, will be more expensive than the one with the addition of cheaper switches, which better reflects the cost advantage of the structure in this paper. In addition, the circuit works by controlling only the on and off of the switch
in the BCEQ, which reduces the hardware resource requirements and also saves costs to a certain extent. When the amount of cells inside the unit gets higher, only the switch needs to be added, and the complexity of the circuit remains the same. Figure 14
shows a comparison chart of all pattern information, and it is clear that the method proposed in this paper has an advantage in terms of equalization time, circuit size, construction cost, and control difficulty.
4.2. Equalization Control Strategy Verification
The VFPID introduces the concept of the variable theoretical domain based on FPID so that the input and output theoretical domains are adjusted in real-time with the change in the scaling factor, thus achieving adaptive change and better control accuracy for nonlinear and large lag systems. An in-module charge/discharge equalization simulation experiment is performed in this section, using VFPID and FPID to validate the superior performance of the method proposed in this paper. Charge and discharge with constant current and set the equalization current to 5A. Set the initial values of battery SOC to values with large differences for more visual observation, and set the initial SOC of each battery to 78%, 75%, 72%, 70%, 68%, and 64% in the static experiment for more visual observation. Such as in Figure 15
, the three cells with the most charge were discharged at the beginning, while the cells with less charge were not. The equalization time of VFPID is about 935 s, while the equalization time of FPID is about 1289 s. The equalization speed is increased by 27.5%, and the extreme difference values of SOC of each cell after equalization are 0.33% and 0.12%, respectively. During charging, the original SOC values for each cell are set to 53%, 51%, 48%, 45%, 43%, and 41%. Such as in Figure 16
, the equalization time of VFPID is about 927 s, while the equalization time of FPID is about 1274 s, which is 27.2% faster. The SOC extremes of each cell after equalization are 0.28% and 0.11%, respectively. During discharging, the original SOC values for each cell are set to 85%, 83%, 80%, 78%, 75%, and 73%. Such as in Figure 17
, the VFPID equalization time is approximately 942 s, while the equalization time of FPID is about 1298 s, and the equalization speed is improved by 27.4%; the SOC pole values of each battery after equalization are 0.24% and 0.09%, respectively. Table 8
illustrates the SOC values of the cells after the equalization is completed by the two algorithms. Figure 18
shows the comparison of the SOC results of the equalized cells.
4.3. Verification of the Equalization Scheme under Dynamic DST Conditions
In the actual use of the vehicle, there is usually complex dynamic multiplier charging and discharging. Therefore, this section verifies the discharge of the four circuits in Section 4.1
under dynamic DST conditions, with the SOCs of each cell initially set to 62%, 61%, 60%, 59%, 58%, and 57%; Figure 19
shows the working discharge current during dynamic multiplier discharge with a discharge time of 3000 s, and Figure 20
demonstrates the equalization procedure. At the times of 1906 s, 1467 s, 1788 s, and 1318 s correspondingly, compared with other equilibration schemes, this study provides faster equilibration, saving time by 30.8%, 10.2%, and 26.3%, respectively, and the SOC pole difference values of each pattern cell after equilibrium are 0.35%, 0.27%, 0.31%, and 0.18%, respectively; the energy utilization percentages rose by 4.9%, 4.3%, and 4.5%, respectively, and the findings of the equalization tests are given in Table 9
. Therefore, the equalization method proposed in the literature is equally applicable under dynamic conditions and can solve the problem of inconsistency of the cells and ensure the safe operation of the power pack.