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Review

Ultimate Scaling of High-κ Gate Dielectrics: Higher-κ or Interfacial Layer Scavenging?

by
Takashi Ando
IBM Thomas J. Watson Research Center, Yorktown Heights, New York, NY 10598, USA
Materials 2012, 5(3), 478-500; https://doi.org/10.3390/ma5030478
Original submission received: 29 January 2012 / Revised: 11 February 2012 / Accepted: 6 March 2012 / Published: 14 March 2012
(This article belongs to the Special Issue High-k Materials and Devices)
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Abstract

:
Current status and challenges of aggressive equivalent-oxide-thickness (EOT) scaling of high-κ gate dielectrics via higher-κ (>20) materials and interfacial layer (IL) scavenging techniques are reviewed. La-based higher-κ materials show aggressive EOT scaling (0.5–0.8 nm), but with effective workfunction (EWF) values suitable only for n-type field-effect-transistor (FET). Further exploration for p-type FET-compatible higher-κ materials is needed. Meanwhile, IL scavenging is a promising approach to extend Hf-based high-κ dielectrics to future nodes. Remote IL scavenging techniques enable EOT scaling below 0.5 nm. Mobility-EOT trends in the literature suggest that short-channel performance improvement is attainable with aggressive EOT scaling via IL scavenging or La-silicate formation. However, extreme IL scaling (e.g., zero-IL) is accompanied by loss of EWF control and with severe penalty in reliability. Therefore, highly precise IL thickness control in an ultra-thin IL regime (<0.5 nm) will be the key technology to satisfy both performance and reliability requirements for future CMOS devices.

Graphical Abstract

1. Introduction

The rapid progress of complementary metal-oxide-semiconductor (CMOS) integrated circuit technology has been accomplished by a calculated reduction of the dimensions of the unit device in the circuit—a practice termed “scaling [1]”. Continued device scaling for future technology nodes requires reduction in equivalent oxide thickness (EOT) of gate dielectrics. Extendibility of the conventional SiO(N)/polycrystalline silicon (poly-Si) gate structure is challenged due to exponential increase in gate leakage currents [2]. As alternatives to SiO(N) gate dielectrics, much work has been done on the research of high permittivity (high-κ) materials [3]. After a decade-long search for the appropriate high-κ materials, the semiconductor industry has converged on Hf-based oxides, such as HfO2 or HfSixOy, for the first generation CMOS products featuring high-κ gate dielectrics and metal gate electrodes (HKMG) [4,5]. The EOT for the first generation HKMG device is approximately 1.0 nm [4]. Continued Lg scaling for the 32 nm and beyond with a planer structure requires sub-nm EOT to suppress short-channel effects. Fully depleted device structures, such as FinFET or extremely thin SOI (ETSOI), improve short-channel control and thus relax the requirements for EOT scaling. However, the insertion point of such device architectures is expected to be the 22 nm and beyond and sub-nm EOT may be still required at those advanced technology nodes.
A typical HKMG stack structure contains a silicon oxide based interfacial layer (IL), a high-k dielectric, followed by a metal gate electrode. This system is equivalent to two capacitors connected in series. Thus, the total EOT of the HKMG stack can be expressed as follows.
E O T = E O T I L + E O T H K
where EOTIL and EOTHK are contributions from the IL and high-κ layer, respectively. An apparent way to scale EOTHK is to reduce the physical thickness of the high-κ layer, however, there is little room in this direction. It has been reported that a thick HfO2 layer causes significant degradations in carrier mobility and charge trapping both with gate-first [6] and gate-last [7] processes. Therefore, the first generation HKMG devices already employ the thinnest possible high-κ layer. This leaves us with three possible EOT scaling approaches: (1) Introduce a new high-κ material with k-value greater than that of HfO2; (2) Increase the k-value of IL; (3) Reduce the physical thickness of IL. In this paper, we review current status and challenges for each approach and discuss the EOT scaling strategy for future CMOS devices.

2. Higher-κ Materials

HfO2 is one of the most widely used high-κ materials, showing a k-value of approximately 20. Replacing HfO2 with materials having k-values greater than 20 (higher-κ) is a long term scaling solution. In pursuit of higher-k materials, the tradeoff between k-value and band gap needs to be taken into account. It is generally known that band gap values have a roughly inverse dependence on k-values (Eg~k−0.65) [8]. Therefore, materials with too high k-values typically result in excessive direct tunneling currents and most work showing promising EOT-leakage current density (Jg) characteristics has been achieved with k-value ranging from 20 to 30. Various groups have reported k-value increase in this range by stabilizing the higher-k phase (tetragonal or cubic) of HfO2 via doping of elements such as zirconium [9], yttrium [10], and silicon [11]. This is a practical means to attain a modest k-value increase, however, controllability of crystallinity in an ultra thin HfO2 thickness regime (<2 nm) has yet to be demonstrated. Other groups have suggested La-based higher-k materials such as La-Al-O or La-Lu-O [12]. These materials have recently demonstrated a lot of promise to outperform Hf-based high-κ on a device level [13,14,15,16].
A less disruptive way to increase the average k-value of the gate stack is to boost the k-value of the IL in conjunction with Hf-based oxides. A La2O3 cap on a Hf-based high-κ layer has been widely used to adjust the threshold voltage (Vt) of n-type field-effect-transistors (nFET) [17]. Some portion of the La elements diffuse through the high-κ layer and form La-silicate IL after high temperature anneals [18]. This is an effective way to increase the k-value of SiO2-based IL. Figure 1(a,b) shows the Z-contrast image and Electron Energy-Loss Spectroscopy (EELS) profiles, respectively, obtained by Cs-corrected Scanning Transmission Electron Microscopy (STEM) for the SiO2/HfO2/La2O3/TiN/poly-Si stack after a 1,000 °C anneal (after [19]). As seen in Figure 1(b), formation of La-silicate in the IL can be precisely controlled by carefully optimizing the La2O3 layer thickness and the thermal budget, resulting in EOT of 0.58 nm. It was also reported that a single layer of La-silicate gate dielectric scales EOT to a similar value (0.62 nm) [20]. As a potential new alternative, it was recently shown that a thin epitaxial strontium oxide (SrO) interfacial layer prior to HfO2 deposition results in EOT of 0.50 nm [21] and 0.60 nm [22] for gate-last and gate-first integrations, respectively.
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Figure 1. (a) Z-contrast image and (b) corresponding Electron Energy-Loss Spectroscopy (EELS) profiles (La, Ti, and Si) of the SiO2/HfO2/La2O3/TiN/poly-Si stack after a 1,000 °C anneal (after [19]).
Figure 1. (a) Z-contrast image and (b) corresponding Electron Energy-Loss Spectroscopy (EELS) profiles (La, Ti, and Si) of the SiO2/HfO2/La2O3/TiN/poly-Si stack after a 1,000 °C anneal (after [19]).
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Table 1 summarizes recently reported IL k-boost and higher-κ data. EOT values less than 0.80 nm have been achieved with both approaches, however, the aggressive scaling is accompanied with effective workfunction (EWF) shift toward the Si conduction band minimum (CBM) in most cases. This trend is attributable to formation of electric dipoles at the SiO2/high-κ interface originating from lanthanide (e.g., La, Lu) or alkaline earth (e.g., Sr) metals [23,24,25]. Formation of such dipoles makes application of these materials to p-type field-effect-transistors (pFET) extremely difficult. Development of CMOS-compatible higher-κ materials is one of the biggest challenges to overcome. Unlike other lanthanide-based higher-κ materials, La-Al-O showed controllability of the EWF from the Si CBM to near the Si mid-gap with TiN electrodes by changing the La/(La+Al) atomic ratio [16,26,27]. This unique capability of La-Al-O may allow CMOS integration when combined with appropriate workfunction setting metals using gate-last process [28].
Table
Table 1. Summary of silicon oxide based interfacial layer (IL) k-boost and higher-k data in literature. Equivalent oxide thickness (EOT), effective workfunction (EWF).
Table 1. Summary of silicon oxide based interfacial layer (IL) k-boost and higher-k data in literature. Equivalent oxide thickness (EOT), effective workfunction (EWF).
Materialsk-valueEOT (nm)EWF with TiN electrode
La-silicate IL/(HfO2) [19,20]-0.58–0.62~Si CBM
SrO IL/HfO2 [20,21]-0.50–0.60~Si CBM
Y doped HfO2 [10]27--
Si doped HfO2 [11]27--
La-Lu-O [13]230.58~Si CBM
Y-La-Si-O [14]-0.77~Si CBM
La2O3 [16]-0.62~Si CBM
La-Al-O [15,16]23–250.31–0.74Si CBM~Si mid-gap

3. Interfacial Layer Scavenging Approach

As reviewed in Section 2, higher-κ materials are not mature enough to replace Hf-based oxide especially in terms of pFET EWF control although there has been great progress in EOT scaling in recent years (see Table 1). Considering the maturity of Hf-based high-κ gate dielectrics, scaling SiO2-based IL in conjunction with Hf-based oxides may be more practical in meeting the requirements for the 22 nm node and beyond. Several techniques going in this direction have been reported, such as IL scaling via scavenging reaction [19,29,30,31,32,33,34,35,36,37], cycle-by-cycle atomic layer deposition (ALD) and annealing of HfO2 [38], and advanced post deposition anneal for epitaxial HfO2 growth [39]. In this section, we mainly review the IL scavenging process since most device level learning is available in the literature with this approach.

3.1. Materials and Process Considerations

IL scaling via scavenging reaction has become a mainstream approach in recent years to realize EOT 0.5 nm and less. Several variations have been reported since Kim et al. found this phenomenon using a Ti overlayer on HfO2 or ZrO2 gate dielectrics [29]. Table 2 summarizes the key materials and process parameters for various IL scavenging processes in the literature. We have reviewed these IL scavenging processes from the following perspectives: (1) IL growth condition, (2) Choice of scavenging element, (3) Location of scavenging element, (4) Choice of high-κ material, (5) Maximum process temperature.

3.1.1. IL Growth Condition

Ragnarsson et al. reported that EOT scaling via IL scavenging strongly depends on the growth condition of the initial IL [36]. In this work, room temperature chemical oxide ILs showed more EOT scaling compared to in-situ steam generation (ISSG) oxide ILs at 760–900 °C and thermal oxide ILs at 1,100 °C. It has been reported that IL scavenging reaction proceeds via decomposition of SiO2 and subsequent re-incorporation of Si atoms into the channel [29,34]. Since this is a reverse reaction of IL growth, a uniform SiO2 layer with low formation energy may be preferred as a starting IL to facilitate the scavenging reaction at later stages of process flow.
Table
Table 2. Summary of IL scavenging processes in the literature.
Table 2. Summary of IL scavenging processes in the literature.
Scavenging elementHigh-κ materialsMax temperature (°C)EOT (nm)
Ti [29]HfO2 or ZrO23001.70
Ti [31]HfO25000.69
Hf [31]HfO25000.60
Hf [32]HfO210200.59
TiN [36]HfO210350.60
TiN [36]HfO2/La-cap10350.46
Doped TiN [19]HfO210000.54
Doped TiN [19]HfO2/La-cap10000.42
Doped TiN [37]HfO26000.49

3.1.2. Choice of Scavenging Element

Scavenging element is one of the most important factors for IL scavenging reaction, which affects the choice of other process parameters, such as location of scavenging element or maximum temperature in the subsequent processes. We found that the Gibbs free energy change at 1,000 K (ΔG01000) of the following reaction serves as a guiding principle for the choice of scavenging element [19].
S i + 2 y M x O y → 2 x y M + S i O 2
where M is the scavenging element in the gate stack. When M with a positive ΔG01000 value is doped in the gate stack, there is an energy gain for forming a metal oxide (MxOy) rather than maintaining SiO2, which is the driving force for the IL scavenging reaction. In the actual scavenging reaction, oxygen transport from SiO2 to M requires some energy. However, the experimental data suggest that oxygen diffusion through HfO2 or ZrO2 is quite rapid at elevated temperatures and this is not the rate-limiting step for the IL scavenging reaction [29,34]. The EOT trend for metal-inserted poly-Si stack (MIPS) [40] with SiO2/HfO2 dual-layer gate dielectrics in the literature is summarized in Figure 2 as a function of ΔG01000 per oxygen atom (ΔG01000/O) for the scavenging element. Here, the scavenging element is defined as the metal with the most positive ΔG01000/O value (after [41]), existing in either gate dielectrics or workfunction-setting metal layers. For this comparison, data from the early days of gate-first development are also included (Poly-Si gate in [42]; W, TaN, TiN gates in [43]) to understand the IL scavenging process in a historical context.
As seen in Figure 2, EOT and ΔG01000/O values show a very strong correlation. Poly-Si data point [42] serves as a reference since the ΔG01000/O value is zero and neither IL regrowth nor scavenging is expected. Most thermally stable metals studied in the early phase of MGHK development (e.g., W, TaN in [43]) have negative ΔG01000/O values, resulting in IL regrowth during high temperature activation anneals. On the other hand, TiN has a slightly positive ΔG01000/O value, providing slight EOT scaling compared to Poly-Si in most cases (e.g., thick TiN in [36,43]). The near zero ΔG01000/O value may be the main reason why TiN has been widely accepted as a baseline metal electrode throughout the industry. The neutral nature of TiN typically results in neither IL regrowth nor scavenging. However, it is possible to trigger IL scavenging by carefully optimizing the TiN thickness and employing an in-situ cap due to the slightly negative ΔG01000/O value (e.g., thin TiN in [36]). In this case, a high thermal budget (>1,000 °C) is required since the driving force of the reaction is not very strong. In order to facilitate the reaction at lower temperatures, scavenging elements with much more positive ΔG01000/O values are needed. Such elements, however, come with a severe penalty in thermal stability due to high reactivity with high-κ layers. In fact, early IL scavenging works employ pure transition metals with high ΔG01000/O values at relatively low temperatures (300–500 °C [29,31]). Thus, direct capping of very strong scavenging metals may not be compatible with the state-of-the-art CMOS integration requiring higher process temperatures. To overcome this trade-off, we proposed doping of scavenging metals with high ΔG01000/O values into a thermally stable TiN electrode [19,34]. This technique enables highly controllable IL scavenging for both gate-first (maximum process temperature: 1,000 °C) [19] and gate-last (maximum process temperature: 600 °C) [37] integrations.
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Figure 2. EOT of SiO2/HfO2 metal-inserted poly-Si stack (MIPS) structure as a function of ΔG01000 per oxygen atom for scavenging element. TiN electrodes doped with various metals are compared with literature data (after [19,32,36,42,43]). The ΔG01000 values are after [41].
Figure 2. EOT of SiO2/HfO2 metal-inserted poly-Si stack (MIPS) structure as a function of ΔG01000 per oxygen atom for scavenging element. TiN electrodes doped with various metals are compared with literature data (after [19,32,36,42,43]). The ΔG01000 values are after [41].
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As reviewed in this sub-section, the choice of appropriate scavenging metals, considering the thermal budget in downstream processes, is the key aspect of IL scavenging technique. We found that the ΔG01000/O value for Equation (2) consistently explains the historical EOT trend and serves as a guiding principle for the material choice.

3.1.3. Location of Scavenging Element

In this sub-section, we have categorized various IL scavenging techniques into direct-scavenging and remote-scavenging based on the locations of the scavenging elements in the gate stacks. Figure 3 illustrates the difference between the two categories. Direct-scavenging schemes incorporate the scavenging elements within the high-κ layers, whereas the remote-scavenging schemes isolate the scavenging elements from the high-κ layers. Early IL scavenging works fall into the direct-scavenging category since the scavenging metals are incorporated within the high-κ layers either by direct capping [29,30] or by deposition of off-stoichiometric HfO2 [32]. Then, we reported IL scavenging using a TaN-alloy electrode [33]. This technique is still considered direct-scavenging since the scavenging metals diffuse out from the TaN-alloy during a high temperature anneal and end up in the HfO2 layer. The advantage of direct-scavenging is that it does not require such a strong driving force of the reaction (see ΔG01000/O discussion in the previous sub-section). Therefore, a relatively weak scavenging metal such as Ti can cause aggressive EOT scaling [29,31]. The downsides of this approach include the following: (1) Effective workfunction change either by inherently low vacuum workfunction of scavenging metals or by formation of fixed charges and/or interface dipoles [29,31]; (2) Excessive carrier mobility degradation and leakage current increase [19]. One elegant way to perform direct-scavenging is to use Hf as a scavenging metal such that it becomes a part of the HfO2 gate dielectric after absorbing oxygen from the IL [30,32]. The degradation in device characteristics due to direct-scavenging can be mitigated to some extent in this way. We proposed the concept of remote-scavenging to completely overcome the aforementioned issues. By doping scavenging elements into a thermally stable TiN electrode with a certain distance from the high-κ/TiN interface, it is possible to cause IL scavenging reaction without out-diffusion of the scavenging elements into the high-κ layer. Such a process enables EOT scaling without extrinsic degradation in carrier mobility and leakage current and with no change in EWF [19]. Another way to carry out remote-scavenging is to employ a thin TiN electrode (~2 nm) with an in-situ Si cap to avoid oxidation from the ambient [35]. These remote-scavenging techniques demonstrated highly controllable EOT scaling and compatibility with advanced CMOS processing. Figure 4 shows cross-sectional transmission electron microscopy (TEM) images of the HKMG stacks for remote-scavenging with (a) medium scavenging metal dose, (b) high scavenging metal dose (after [19]), and (c) direct scavenging with TaN-alloy (after [33]), respectively. As shown in Figure 4(a,b), the final IL thickness is controllable by changing the scavenging metal dose. It is possible to completely eliminate the initial IL by both remote-scavenging and direct-scavenging (see Figure 4(b,c)).
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Figure 3. Schematics of direct- and remote- scavenging techniques in the literature.
Figure 3. Schematics of direct- and remote- scavenging techniques in the literature.
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Figure 4. Cross-sectional transmission electron microscopy (TEM) images of the high-κ gate dielectrics and metal gate electrodes (HKMG) stacks for remote-scavenging with (a) medium scavenging metal dose; (b) high scavenging metal dose (after [19]); and (c) direct scavenging with TaN-alloy (after [33]).
Figure 4. Cross-sectional transmission electron microscopy (TEM) images of the high-κ gate dielectrics and metal gate electrodes (HKMG) stacks for remote-scavenging with (a) medium scavenging metal dose; (b) high scavenging metal dose (after [19]); and (c) direct scavenging with TaN-alloy (after [33]).
Materials 05 00478 g004

3.1.4. Choice of High-κ Material

As shown in Table 2, most IL scavenging works used HfO2 or ZrO2 as gate dielectrics. In order to understand the role of high-κ layer on IL scavenging, we employed doped TiN electrodes on various compositions of HfSixOy layers with the Si/(Hf + Si) ratio ranging from 0.00 (HfO2) to 0.44 and fabricated metal-oxide-semiconductor (MOS) capacitors using gate-first process with a 1,000 °C activation anneal. Reference samples with pure TiN electrodes were also prepared. Figure 5(a) shows EOT reduction by remote IL scavenging (i.e., EOT difference between the doped TiN and the pure TiN) as a function of the Si/(Hf + Si) ratio of HfSixOy. The doping amount of the scavenging metal was chosen such that the initial IL (approximately 0.5 nm) is completely removed for HfO2. As the Si/(Hf + Si) ratio is increased, the EOT reduction is similar to that for HfO2 up to Si/(Hf + Si) ratio of 0.20 and then it starts to decrease. This trend indicates that ionic bonds (Hf-O) play a key role in remote-scavenging and the effect is hampered as the ratio of covalent bonds (Si-O) is increased. HfO2 and ZrO2 are very effective mediators of remote-scavenging from this perspective.

3.1.5. Maximum Process Temperature

The discussion in Section 3.1.4 leads us to speculate that oxygen vacancies in ionic metal oxides contribute to remote-scavenging. We investigated the temperature dependence of remote-scavenging using HfO2 gate dielectrics in order to shed more light on the kinetics of the reaction. The maximum process temperature after the deposition of doped TiN electrodes was varied from 400 °C to 1,000 °C. As shown in Figure 5(b), most of the EOT scaling effect from the doped TiN already took place at 600 °C and little further change occurred with the 1,000 °C process (after [34]). In the case of pure TiN, a slight EOT increase was brought about by the 1,000 °C process. In contrast, the doped TiN served two purposes. One is the substantial EOT scaling via IL scavenging at the temperature between 400 and 600 °C. The other is the suppression of IL regrowth at the higher temperature. The former reaction coincides with the reported temperature at which oxygen vacancies in a HfO2 layer become mobile and reach a steady state for oxygen transport [44]. We speculate that the IL scavenging reaction proceeds in a remote way as the oxygen vacancies in the HfO2 layer act as mediators for oxygen transport from the IL to the TiN electrode. Thermal activation of the mobile oxygen vacancies in the HfO2 at 400–600 °C may be the threshold temperature for this reaction, provided that the driving force of the reaction (ΔG01000/O) is large enough [34,37]. This reaction model is schematically illustrated in Figure 5(c). When the driving force of the reaction is small (e.g., TiN), oxygen scavenging itself becomes the rate-limiting step and much higher thermal budget (1,000 °C or higher) is required [36]. Thus, the required thermal budget for remote-scavenging strongly depends on the choice of scavenging element.
As reviewed in this Section, (1) IL growth condition; (2) Choice of scavenging element; (3) Location of scavenging element; (4) Choice of high-κ material; (5) Maximum process temperature, are the key considerations for IL scavenging. Careful materials and process design suited for the overall integration scheme (e.g., gate-first or gate-last) is indispensable for the implementation of IL scavenging in state-of-the-art CMOS devices.
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Figure 5. (a) EOT reduction via remote-scavenging from doped TiN electrodes as a function of Si/(Hf+Si) ratio in HfSixOy gate dielectrics. The EOT reduction is calculated from the difference between the doped TiN and the pure TiN; (b) EOT as a function of maximum process temperature for doped TiN and pure TiN using HfO2 gate dielectrics (after [34]); (c) Schematics of remote scavenging reaction. M, V0, and O0 represent the scavenging element, the oxygen vacancy in HfO2, and the oxygen atom in the lattice position of HfO2, respectively.
Figure 5. (a) EOT reduction via remote-scavenging from doped TiN electrodes as a function of Si/(Hf+Si) ratio in HfSixOy gate dielectrics. The EOT reduction is calculated from the difference between the doped TiN and the pure TiN; (b) EOT as a function of maximum process temperature for doped TiN and pure TiN using HfO2 gate dielectrics (after [34]); (c) Schematics of remote scavenging reaction. M, V0, and O0 represent the scavenging element, the oxygen vacancy in HfO2, and the oxygen atom in the lattice position of HfO2, respectively.
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3.2. EOT Scaling and Gate Leakage Current

The polarity of gate leakage current through SiO2/HfO2 dual-layer gate dielectrics depends on the gate bias polarity and substrate doping type. For typical SiO2/HfO2 stacks, electron injection from the Si conduction band is the dominant tunneling current component under positive gate bias (n-type substrate in accumulation), whereas hole injection from the Si valence band is the majority current under negative gate bias (p-type substrate in accumulation) [45,46]. Therefore, we compared the EOT-Jg characteristics of IL scavenging both for n-type and p-type MOS capacitors in accumulation. For this comparison, only direct-scavenging using Hf [30,32] and remote-scavenging [19,34,36,37] are included to rule out the extrinsic degradation in Jg as discussed in Section 3.1.3. In addition, these IL scavenging data are compared with zero-IL HfO2 stacks obtained by other methods (cycle-by-cycle ALD and annealing of HfO2 [38] and advanced post deposition anneal for epitaxial HfO2 growth [39]). Multiple data points from the same reference are obtained by changing the IL thickness with a fixed HfO2 thickness. Figure 6(a,b) show the EOT-Jg characteristics in literature for n-type MOS capacitors and p-type MOS capacitors, respectively. The slopes for ideal SiO2 scaling (10× increase in Jg per 0.2 nm scaling) are included in both plots as a guide. It should be noted that the experimental slopes for IL scavenging follow the ideal SiO2 scaling in a wide EOT range on both bias conditions irrespective of the maximum process temperatures (500–600 °C in [30,37], 1,000–1,035 °C in [19,32,36]). This suggests that optimized IL scavenging techniques can avoid extrinsic Jg degradation for both nFET and pFET either with gate-first or gate-last integration. As shown in Figure 6(a), La-caps help in reducing Jg with little EOT penalty. Thus, the most aggressive EOT scaling (0.42 nm) was obtained by IL scavenging in conjunction with La-caps [34]. Comparison between IL scavenging techniques and other methods [38,39] is shown in Figure 6(b). In all cases, EOT scaling down to 0.50 nm was achieved using pure HfO2, indicating that the ultimate scaling point (zero-IL) does not depend on the method. However, IL scavenging techniques do offer an advantage over other methods in adjusting the IL thickness anywhere between the as-grown thickness and zero on the ideal SiO2 scaling trend in EOT-Jg characteristics [19,32,36,37]. Such controllability of IL thickness is extremely important when we consider EWF control and device reliability in conjunction with aggressive EOT scaling as we review in Section 3.3 and Section 3.4.
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Figure 6. (a) EOT-Jg characteristics for n-type metal-oxide-semiconductor (MOS) capacitors with (SiO2)/HfO2/(La-cap) gate dielectrics in literature. Jg is defined at Vg = flatband voltage (Vfb) + 1 V for [34,37] and at Vg = 1 V for [36]; (b) EOT-Jg characteristics for p-type MOS capacitors with (SiO2)/HfO2 gate dielectrics in literature. Jg is defined at Vg = Vfb − 1 V for [19,30,32,38,39]. The slopes for ideal SiO2 scaling are shown in broken lines with the magnitude in Jg reduction from SiO2/Poly-Si stacks in both plots. The maximum process temperatures are indicated in the legends.
Figure 6. (a) EOT-Jg characteristics for n-type metal-oxide-semiconductor (MOS) capacitors with (SiO2)/HfO2/(La-cap) gate dielectrics in literature. Jg is defined at Vg = flatband voltage (Vfb) + 1 V for [34,37] and at Vg = 1 V for [36]; (b) EOT-Jg characteristics for p-type MOS capacitors with (SiO2)/HfO2 gate dielectrics in literature. Jg is defined at Vg = Vfb − 1 V for [19,30,32,38,39]. The slopes for ideal SiO2 scaling are shown in broken lines with the magnitude in Jg reduction from SiO2/Poly-Si stacks in both plots. The maximum process temperatures are indicated in the legends.
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3.3. Effective Work Function Control

As discussed in Section 3.1.3, remote-scavenging process per se does not change the EWF of the gate stack, which makes this technique applicable to both nFET and pFET if the EWF is independently tuned by other knobs. In the case of gate-first process, La and Al cap layers on Hf-based high-κ gate dielectrics are widely practiced to control the EWF for nFET and pFET, respectively [17,40]. The origin of the EWF change has been identified to be the electric dipoles located at the SiO2/high-κ interface, however, the exact mechanism of the interface dipole formation is still controversial [25,27,47,48].
When the La-(Al-) cap and remote-scavenging techniques are simultaneously employed, we need to consider the kinetics of both reactions. It was reported that the La-(Al-) cap requires at least 800 °C to diffuse through the HfO2 and reach the SiO2 IL [18,25]. After the La (Al) atoms reach the SiO2 IL, thermal budget as low as 300 °C is enough to activate the La- (Al-) induced dipoles [27]. Therefore, the diffusion of La (Al) atoms is the limiting factor for the interface dipole formation. On the other hand, the remote scavenging reaction can happen in a much lower temperature range (400–600 °C) if a sufficiently strong scavenging element is used as discussed in Section 3.1.5. Figure 7 shows the process flow for the MOS capacitors using La-(Al-) caps in conjunction with remote IL scavenging. Due to the difference of kinetics between the remote-scavenging and the interface dipole formation, the chronological order of the reactions is as follows: (1) The remote-scavenging happens during the Poly-Si deposition typically at 500–600 °C; (2) La (Al) atoms diffuse through the HfO2 layer during the activation anneal typically at 1,000 °C or higher; (3) La-(Al-) induced dipole layers form at the bottom IL, as schematically illustrated in Figure 7. The corresponding EOT-Vfb data are shown in Figure 8 (after [19]). The IL thickness was varied by changing the scavenging metal (M) dose. As seen in Figure 8, Vfb tuning by La-(Al-) caps and EOT scaling by remote-scavenging are compatible and can be independently controlled. Thus, the chronological order of the reactions enabled IL scavenging without disruption of the interface dipole formation. However, the EWF controllability by the La-(Al) caps is lost when the SiO2 IL is completely scavenged [49]. In addition, it was reported that complete elimination of IL from a SiO2/HfO2 stack causes disappearance of the interface dipoles originating from Si-O-Hf bonds, resulting in disruptive shifts of Vfb [50]. Therefore, leaving an ultra-thin SiO2 IL after scavenging may be the key to avoid a disruptive change of EWF and to allow tuning by interface dipoles for CMOS integration using gate-first process.
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Figure 7. Process flow for MOS capacitors using La-(Al-) caps in conjunction with remote IL scavenging. The change in the gate dielectrics at the key steps is illustrated in the schematics. The corresponding electrical data are shown in Figure 8.
Figure 7. Process flow for MOS capacitors using La-(Al-) caps in conjunction with remote IL scavenging. The change in the gate dielectrics at the key steps is illustrated in the schematics. The corresponding electrical data are shown in Figure 8.
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Figure 8. EOT-Vfb plot for MOS capacitors prepared with process flow in Figure 7. The Vfb values were tuned toward a negative (positive) direction using La-(Al-) caps. The EOT values were controlled by changing the amount of scavenging metal (M) dose in the TiN electrodes.
Figure 8. EOT-Vfb plot for MOS capacitors prepared with process flow in Figure 7. The Vfb values were tuned toward a negative (positive) direction using La-(Al-) caps. The EOT values were controlled by changing the amount of scavenging metal (M) dose in the TiN electrodes.
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In the case of gate-last process, EWF tuning for nFET and pFET is typically achieved by employing dual metal gates with appropriate work functions [4,51]. Since gate-last process does not rely on interface dipole for EWF adjustment, IL scavenging should not play a direct role on EWF setting. However, it was recently reported that the EWFs of gate-last pFET stacks start to roll-off when EOT is scaled below 0.8 nm [52,53]. Similar EWF roll-off behaviors were initially reported for gate-first process at a much thicker EOT regime (~3 nm) [54,55], motivating many people to move to gate-last process to realize low threshold voltage pFETs. We found that the same phenomenon takes place for gate-last process as the SiO2 IL thickness scales below 0.4 nm [37]. Based on our direct tunneling current analysis of SiO2/HfO2 dual-layer stacks using the transfer-matrix-approach [46,56], it is suggested that the band offsets for the SiO2 and HfO2 layers are reduced in the submonolayer IL regime, which may be related to the existence of a suboxide transition region at the Si/SiO2 interface (~0.3 nm) [57]. Such degradation in film quality may facilitate oxygen vacancy generation in the HfO2 layer [54,58] and/or the SiO2 IL [55], resulting in the unfavorable EWF shift for pFET. Thus, leaving an ultra-thin and robust SiO2 IL after scavenging is indispensable for EWF control of gate-last process as well.

3.4. Implications for Reliability and Carrier Mobility

Other device parameters requiring close attention with aggressive EOT scaling are reliability and carrier mobility. We investigated impacts of remote IL scavenging on reliability using constant voltage stress (CVS) and voltage ramp stress (VRS) [59,60]. SiO2/HfO2 dual-layer stacks with varying IL thicknesses were prepared in both gate-first and gate-last processes for this analysis. The change in the device lifetimes, including positive bias temperature instability (PBTI), negative bias temperature instability (NBTI), and time dependent dielectric breakdown (TDDB), are estimated and summarized in Figure 9 (after [61]). Note that the estimated lifetime trends for IL scaling are similar for gate-first and gate-last processes, indicating that these trends arise from the fundamental materials properties of the SiO2/HfO2 dual-layer stacks and do not depend much on the fabrication method [61]. As shown in Figure 9, the BTI lifetimes are predicted to decrease by 50–100× for every 0.1 nm of IL scaling. Drastic lifetime reductions also occur for TDDB. Therefore, calculated IL scaling, considering reliability requirements, is needed for future CMOS nodes.
The implication of IL scaling for carrier mobility is another important factor for device performance. Although a great deal of progress has been made across the community, electron mobility values for HKMG stacks typically fall below the trend for conventional SiO(N)/Poly-Si stacks. The degradation is attributed to intrinsic properties of high-κ, such as soft optical phonons [62], fixed charges [63,64,65], surface roughness [19,64], and interface dipoles [66]. Figure 10 (a) illustrates impacts of a SiO2/HfO2/TiN stack on electron mobilities at different effective fields (Eeff). In the case of ideal thermal oxide gate dielectrics, the electron mobility is limited by Coulomb scattering from the substrate impurities (low Eeff), phonon scattering from the Si substrate (middle Eeff), and surface roughness scattering from the Si/SiO2 interface (high Eeff) [67]. It has been reported by many researchers that introduction of high-κ dielectrics brings about additional degradation in each Eeff regime. In the low Eeff regime, fixed charges in the high-κ layer or interface dipoles localized at the IL/high-κ interface cause remote Coulomb scattering (RCS) [63,64,65,66]. In the middle Eeff regime, Fischetti et al. predicted that soft optical phonons in high-κ layers can couple with carrier electrons, resulting in remote phonon scattering (RPS) [62]. In the high Eeff regime, either the fluctuation of permittivity of high-κ layers or the surface roughness at the IL/high-κ interface can cause remote surface roughness scattering (r-SRS) [19,64]. All of these additional scattering mechanisms are predicted to show strong dependences on the IL thickness. Therefore we studied the impacts of remote IL scavenging and La-(Al-) induced IL modification on electron mobility.
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Figure 9. (a) Relative change of positive bias temperature instability (PBTI) and negative bias temperature instability (NBTI) lifetime with gate oxide thickness change via IL scavenging; (b) Relative change of time dependent dielectric breakdown (TDDB) lifetime for nFET and pFET with gate oxide thickness change via IL scavenging (after [61]).
Figure 9. (a) Relative change of positive bias temperature instability (PBTI) and negative bias temperature instability (NBTI) lifetime with gate oxide thickness change via IL scavenging; (b) Relative change of time dependent dielectric breakdown (TDDB) lifetime for nFET and pFET with gate oxide thickness change via IL scavenging (after [61]).
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Figure 10. (a) Impacts of SiO2/HfO2/TiN stack on electron mobilities at different Eeff. The red curve is obtained from a typical SiO2/HfO2/TiN stack prepared with gate-first process; (b) Electron mobility limited by RPS and RCS (μRPS + RCS) at 300 K as a function of estimated IL thickness at Ninv of 3 × 1012 cm−2 (after [34]). The data for remote IL scavenging and La-(Al-) induced dipoles are included. The simulated dependence from the RPS theory [62] with ion impurity correction is also shown.
Figure 10. (a) Impacts of SiO2/HfO2/TiN stack on electron mobilities at different Eeff. The red curve is obtained from a typical SiO2/HfO2/TiN stack prepared with gate-first process; (b) Electron mobility limited by RPS and RCS (μRPS + RCS) at 300 K as a function of estimated IL thickness at Ninv of 3 × 1012 cm−2 (after [34]). The data for remote IL scavenging and La-(Al-) induced dipoles are included. The simulated dependence from the RPS theory [62] with ion impurity correction is also shown.
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We performed low temperature mobility measurements and decoupled the SRS component from the RPS and RCS components [19,34]. The RPS- and RCS-limited mobility (μRPS+RCS) at inversion carrier density (Ninv) 3 × 1012 cm−2 as a function of estimated IL thickness is shown in Figure 10(b) (after [34]). Simulated IL dependence from the RPS theory [62] is shown in blue line. The experimental data for remote IL scavenging delineate a straight tradeoff line, which is slightly steeper and shifted downwards from the prediction based on the RPS theory. The deviation is attributable to the additional RCS from the fixed charges [65] and/or interface dipoles [66] at the SiO2/HfO2 interface. It is interesting to note that the trend line for the La-induced dipole is identical to that of the intrinsic IL scaling, indicating no additional RCS. In contrast, the Al-induced dipole brought about additional RCS at a fixed IL thickness. This difference may originate from the silicate forming nature of La [68], resulting in long-range and low density electric dipoles [27]. Thus, La-silicate IL is a promising EOT scaling knob (see Section 2) with no additional mobility degradation, although it is only suitable for nFET due to the EWF shift toward the Si CBM (see Table 1).
On the other hand, the mobility degradation in the high Eeff regime is solely limited by SRS [19,34]. Li and Ma predicted that roughness at the remote interface from the channel can degrade the carrier mobility depending on the oxide thickness (TIL) and the average deviation of TIL(ΔTIL) [69]. We speculate that r-SRS from the SiO2/HfO2 interface is the origin of the mobility degradation, resulting in a strong IL-thickness dependence of high field electron mobility. Figure 11 shows high field electron mobility as a function of EOT from literature data including remote IL scavenging [19,36], direct IL scavenging using Hf [32], La-silicate IL with HfO2 [19,33], and single-layer La-silicate [20]. It should be noted that all data fall on the same line with a slope of approximately 20 cm2/Vs per 0.1 nm scaling, showing the universality of our IL thickness dependent mobility model in the ultra-thin EOT regime [19,34]. Moreover, negligible impact of La-induced dipoles on mobility is evidenced by the convergence of the IL scavenging trend and the La-silicate trend.
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Figure 11. High field electron mobility as a function of EOT from literature data including remote IL scavenging [19,36], direct IL scavenging using Hf [32], La-silicate IL with HfO2 [19,33], and single-layer La-silicate [20]. The mobility values are taken at Ninv = 1 × 1013 cm−2 in [36] and at Eeff = 1 MV/cm in all other work. Simulated contour lines providing the same Ion at Lmin 16, 22, and 30 nm are shown for comparison (after [75]).
Figure 11. High field electron mobility as a function of EOT from literature data including remote IL scavenging [19,36], direct IL scavenging using Hf [32], La-silicate IL with HfO2 [19,33], and single-layer La-silicate [20]. The mobility values are taken at Ninv = 1 × 1013 cm−2 in [36] and at Eeff = 1 MV/cm in all other work. Simulated contour lines providing the same Ion at Lmin 16, 22, and 30 nm are shown for comparison (after [75]).
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3.5. EOT Scaling Strategy

Understanding of correlation between low-field mobility (μ) and high-field carrier velocity (v), which is more directly related to drive current, becomes more and more important in the state-of-the-art CMOS devices. The correlation depends on the gate length (Lg) [70]. In long-channel MOSFETs, μ is the sole factor in determining v. As velocity saturation phenomenon begins to occur in short-channel MOSFETs, μ dependence of v becomes weaker [71]. As the Lg shrinks further, the carrier transport eventually reaches a full-ballistic regime where μ loses its meaning and v is determined solely by injection velocity [72]. Modern MOSFETs, however, are considered to operate in a quasi-ballistic transport regime [73] where μ still plays an important role via backscattering ratio for carriers injected from source to channel [74]. Therefore, a higher μ is still preferred at a given EOT for the near-term CMOS scaling until full-ballistic operation is realized.
Ideally, gate dielectric scaling should be achieved without carrier mobility degradation. As reviewed in Section 3.4., this is fundamentally not possible if we employ IL scaling. The alternative is to maintain sufficiently thick IL and to introduce a higher-κ material. The mobility-EOT trade off may be mitigated in this way, however, materials reaching the maturity of Hf-based high-κ have not been identified yet as reviewed in Section 2. Therefore, EOT scaling with some compromise of carrier mobility is the only available scaling approach. In this regard, Tatsumura et al. predicted a mobility-EOT relationship providing the same drive current (Ion) at a given Lmin (Lg defined by off-state leakage current) by considering both mobility degradation and short-channel effects suppression from EOT scaling [75]. The comparison between the experimental data in the literature and the extracted contour lines from [75] is shown in Figure 11. The mobility-EOT slope for IL scavenging and La-silicate IL (~20 cm2/Vs per 0.1 nm) is shallower than the breakeven relationship for Lmin ≤ 30 nm (~40 cm2/Vs per 0.1 nm). This indicates that it is indeed possible to improve the short-channel device performance by employing IL scaling in conjunction with aggressive Lg scaling in future nodes albeit with some electron mobility degradation. The key to realize performance improvement going in this direction is to follow the ideal IL scaling trend by optimizing the IL scavenging process and/or by employing a silicate IL which does not cause additional carrier scattering (e.g., La-silicate).
Although, IL scaling can provide performance improvement, extreme IL scaling (e.g., zero-IL) ends up with loss of EWF control both in gate-first and gate-last processes (see Section 3.3) and with severe penalty in reliability (see Section 3.4). Therefore, a highly controllable IL scavenging technique which can adjust the IL thickness to the optimum point where both performance and reliability requirements are satisfied is required. Such IL thickness control has been demonstrated for remote IL scavenging by changing the scavenging metal dose in the TiN electrodes [19,34,37] or by adjusting the TiN thickness with the in-situ Si cap [35,36]. These are encouraging techniques to extend Hf-based high-κ dielectrics toward the end of the CMOS roadmap.

4. Conclusions

EOT scaling into the sub-nm regime has been accomplished by various approaches. La-based higher-κ materials and La-silicate IL with HfO2 showed aggressive EOT values (0.5–0.8 nm), but with large EWF shifts toward the Si CBM, limiting their application to nFET. Further exploration for pFET-compatible higher-κ materials is needed. Meanwhile, IL scavenging is a promising approach to extend Hf-based high-κ dielectrics to future nodes. Remote-scavenging techniques enable EOT scaling below 0.5 nm. The key considerations for IL scavenging are (1) IL growth condition; (2) Choice of scavenging element; (3) Location of scavenging element; (4) Choice of high-κ material and (5) Maximum process temperature. Careful materials and process choice based on these considerations is indispensable. Mobility-EOT trends in the literature suggest that short-channel performance improvement is attainable with aggressive EOT scaling via IL scavenging or La-silicate formation. However, extreme IL scaling is accompanied with loss of EWF control and with severe penalty in reliability. Therefore, highly precise IL thickness control in an ultra-thin IL regime (<0.5 nm) will be the key technology to satisfy both performance and reliability requirements for future CMOS devices.

Acknowledgments

The author acknowledges useful discussions with M.M. Frank, E.A. Cartier, C. Choi (now at Hanyang University), J. Rozen, N.D. Sathaye, K.V.R.M. Murali and V. Narayanan of IBM and K. Choi and A. Kerber of GLOBALFOUNDRIES. This work was performed by the Research Alliance Teams at various IBM Research and Development facilities.

References

  1. Dennard, R.H.; Gaensslen, F.H.; Yu, H.-N.; Rideout, V.L.; Bassou, E.; LeBlanc, A.R. Design of ion-implanted MOSFET’s with very small physical dimensions. IEEE J. Solid-State Circuits 1974, 9, 256–268. [Google Scholar] [CrossRef]
  2. Buchanan, D.A. Scaling the gate dielectric: Materials, integration, and reliability. IBM J. Res. Develop. 1999, 43, 245–264. [Google Scholar] [CrossRef]
  3. Wilk, G.D.; Wallace, R.M.; Anthony, J.M. High-κ gate dielectrics: Current status and materials properties considerations. J. Appl. Phys. 2001, 89, 5243–5275. [Google Scholar] [CrossRef]
  4. Mistry, K.; Allen, C.; Auth, C.; Beattie, B.; Bergstrom, D.; Bost, M.; Buehler, M.; Cappelani, A.; Chau, R.; Choi, C.H.; et al. A 45 nm logic technology with High-κ + metal gate transistors, strained silicon, 9 Cu interconnect layers, 193 nm dry patterning, and 100% Pb-free packaging. In Proceedings of IEEE International Electron Devices Meeting, Washington, DC, USA, 10–12 December 2007; pp. 247–250.
  5. Greene, B.; Liang, Q.; Amarnath, K.; Wang, Y.; Schaeffer, J.; Cai, M.; Liang, Y.; Saroop, S.; Cheng, J.; Rotondaro, A.; et al. High performance 32 nm SOI CMOS with high-κ/metal gate and 0.149 μm² SRAM and ultra low-κ back end with eleven levels of copper. In Proceedings of VLSI Technology Symposium, Kyoto, Japan, 15–18 June 2009; pp. 140–141.
  6. Kirsch, P.D.; Quevedo-Lopez, M.A.; Krishnan, S.A.; Lee, B.H.; Pant, G.; Kim, M.J.; Wallace, R.M.; Gnade, B.E. Mobility and charge trapping comparison for crystalline and amorphous HfON and HfSiON gate dielectrics. Appl. Phys. Lett. 2006, 89, 242909:1–242909:3. [Google Scholar] [CrossRef]
  7. Ando, T.; Hirano, T.; Tai, K.; Yamaguchi, S.; Yoshida, S.; Iwamoto, H.; Kadomura, S.; Watanabe, H. Low threshold voltage and high mobility nMOSFET Using Hf-Si/HfO2 gate stack fabricated by gate-last process. Jpn. J. Appl. Phys. 2010, 49, 016502:1–016502:6. [Google Scholar]
  8. Robertson, J. Maximizing performance for higher K gate dielectrics. J. Appl. Phys. 2008, 104, 124111–124117. [Google Scholar] [CrossRef]
  9. Hegde, R.I.; Triyoso, D.H.; Tobin, P.J.; Kalpat, S.; Ramon, M.E.; Tseng, H.H.; Schaeffer, J.K.; Luckowski, E.; Taylor, W.J.; Capasso, C.C.; et al. Microstructure modified HfO2 using Zr addition with TaxCy gate for improved device performance and reliability. In Proceedings of IEEE International Electron Devices Meeting, Washington, DC, USA, 4–7 December 2005; pp. 35–38.
  10. Kita, K.; Kyuno, K.; Toriumi, A. Permittivity increase of yttrium-doped HfO2 through structural phase transformation. Appl. Phys. Lett. 2005, 86, 102906:1–102906:3. [Google Scholar] [CrossRef]
  11. Tomida, K.; Kita, K.; Toriumi, A. Dielectric constant enhancement due to Si incorporation into HfO2. Appl. Phys. Lett. 2006, 89, 142902:1–142902:3. [Google Scholar]
  12. Schlom, D.G.; Haenni, J.H. A thermodynamic approach to selecting alternative gate dielectrics. MRS Bull. 2002, 27, 198–204. [Google Scholar] [CrossRef]
  13. Edge, L.F.; Vo, T.; Paruchuri, V.K.; Iijima, R.; Bruley, J.; Jordan-Sweet, J.; Linder, B.P.; Kellock, A.J.; Tsunoda, T.; Shinde, S.R. Materials and electrical characterization of physical vapor deposited LaxLu1−xO3 thin films on 300 mm silicon. Appl. Phys. Lett. 2011, 98, 122905:1–122905:3. [Google Scholar] [CrossRef]
  14. Dubourdieu, C.; Cartier, E.; Bruley, J.; Hopstaken, M.; Frank, M.M.; Narayanan, V. High temperature (1,000 °C) compatible Y-La-Si-O silicate gate dielectric in direct contact with Si with 7.7 Å equivalent oxide thickness. Appl. Phys. Lett. 2011, 98, 252901:1–252901:3. [Google Scholar] [CrossRef]
  15. Suzuki, M.; Tomita, M.; Yamaguchi, T.; Fukushima, N. Ultra-thin (EOT = 3 Å) and low leakage dielectrics of La-alminate directly on Si substrate fabricated by high temperature deposition. In Proceedings of IEEE International Electron Devices Meeting, Washington, DC, USA, 5 December 2005; pp. 433–436.
  16. Arimura, H.; Brown, S.L.; Callegari, A.; Kellock, A.; Bruley, J.; Copel, M.; Watanabe, H.; Narayanan, V.; Ando, T. Maximized benefit of La-Al-O higher-k gate dielectrics by optimizing the La/Al atomic ratio. IEEE Electron Device Lett. 2011, 32, 288–290. [Google Scholar] [CrossRef]
  17. Narayanan, V.; Paruchuri, V.K.; Bojarczuk, N.A.; Linder, B.P.; Doris, B.; Kim, Y.H.; Zafar, S.; Stathis, J.; Brown, S.; Arnold, J.; et al. Band-edge high-performance high-κ/metal gate n-MOSFETs using cap layers containing group IIA and IIIB elements with gate-first processing for 45 nm and beyond. In Proceedings of VLSI Technology Symposium, Honololu, HA, USA, 13–17 June 2006; pp. 224–225.
  18. Copel, M.; Guha, S.; Bojarczuk, N.; Cartier, E.; Narayanan, V.; Paruchuri, V. Interaction of La2O3 capping layers with HfO2 gate dielectrics. Appl. Phys. Lett. 2009, 95, 212903:1–212903:3. [Google Scholar] [CrossRef]
  19. Ando, T.; Frank, M.M.; Choi, K.; Choi, C.; Bruley, J.; Hopstaken, M.; Copel, M.; Cartier, E.; Kerber, A.; Callegari, A.; Lacey, D.; Brown, S.; Yang, Q.; Narayanan, V. Understanding mobility mechanisms in extremely scaled HfO2 (EOT 0.42 nm) using remote interfacial layer scavenging technique and Vt-tuning dipoles with gate-first process. In Proceedings of IEEE International Electron Devices Meeting, Washington, DC, USA, 7–9 December 2009; pp. 423–426.
  20. Kawanago, T.; Lee, Y.; Kakushima, K.; Ahmet, P.; Tsutsui, K.; Nishiyama, A.; Sugii, N.; Natori, K.; Hattori, T.; Iwai, H. EOT of 0.62 nm and high electron mobility in La-silicate/Si structure based nMOSFETs achieved by utilizing metal-inserted poly-Si stacks and annealing at high temperature. IEEE Trans. Electron Devices 2012, 59, 269–276. [Google Scholar] [CrossRef]
  21. Marchiori, C.; Frank, M.M.; Bruley, J.; Narayanan, V.; Fompeyrine, J. Epitaxial SrO interfacial layers for HfO2–Si gate stack scaling. Appl. Phys. Lett. 2011, 98, 052908-1–052908-3. [Google Scholar] [CrossRef]
  22. Frank, M.M.; Marchiori, C.; Bruley, J.; Fompeyrine, J.; Narayanan, V. Epitaxial strontium oxide layers on silicon for gate-first and gate-last TiN/HfO2 gate stack scaling. Microelectron. Eng. 2011, 88, 1312–1316. [Google Scholar] [CrossRef]
  23. Yamamoto, Y.; Kita, K.; Kyuno, K.; Toriumi, A. Study of La-induced flat band voltage shift in metal/HfLaOx/SiO2/Si capacitors. Jpn. J. Appl. Phys. 2007, 46, 7251–7255. [Google Scholar] [CrossRef]
  24. Iwamoto, K.; Kamimuta, Y.; Ogawa, A.; Watanabe, Y.; Migata, S.; Nabatame, T.; Toriumi, A. Experimental evidence for the flatband voltage shift of high-κ metal-oxide-semiconductor devices due to the dipole formation at the high-k/SiO2 interface. Appl. Phys. Lett. 2008, 92, 132907:1–132907:3. [Google Scholar] [CrossRef]
  25. Jagannathan, H.; Narayanan, V.; Brown, S. Engineering high dielectric constant materials for band-edge CMOS applications. ECS Trans. 2008, 16, 19–26. [Google Scholar]
  26. Suzuki, M.; Koyama, M.; Kinoshita, A. Effect of composition in ternary La-Al-O films on flat-band voltage for application to dual high-k Gate dielectric technology. Jpn. J. Appl. Phys. 2009, 48, 05DA03:1–05DA03:4. [Google Scholar]
  27. Arimura, H.; Haight, R.; Brown, S.L.; Kellock, A.; Callegari, A.; Copel, M.; Watanabe, H.; Narayanan, V.; Ando, T. Temperature-dependent La- and Al-induced dipole behavior monitored by femtosecond pump/probe photoelectron spectroscopy. Appl. Phys. Lett. 2010, 96, 132902:1–132902:3. [Google Scholar] [CrossRef]
  28. Rozen, J.; Ando, T.; Brown, S.L.; Bruley, J.; Cartier, E.; Kellock, A.J.; Narayanan, V. Work function control and equivalent oxide thickness scaling below 9 Å in a LaAlO-silicate interfacial layer/HfO2 stack compatible with gate last processing. In Presented at the 2011 IEEE Semiconductor Interface Specialists Conference, Arlington, VA, USA, 6–8 December 2011.
  29. Kim, H.; McIntyre, P.C.; Chui, C.O.; Saraswat, K.C.; Stemmer, S. Engineering chemically abrupt high-k metal oxide/silicon interfaces using an oxygen-gettering metal overlayer. J. Appl. Phys. 2004, 96, 3467–3472. [Google Scholar] [CrossRef]
  30. Choi, C.; Kang, C.Y.; Rhee, S.J.; Abkar, M.S.; Krishna, S.A.; Zhang, M.; Kim, H.; Lee, T.; Zhu, F.; Ok, I.; Koveshnikov, S.; Lee, J.C. Fabrication of TaN-gated ultra-thin MOSFETs(EOT < 1.0 nm) with HfO2 using a novel oxygen scavenging process for sub 65 nm application. In Proceedings of VLSI Technology Symposium, Kyoto, Japan, 14–18 June 2005; pp. 208–209.
  31. Choi, C.; Lee, J.C. Scaling equivalent oxide thickness with flat band voltage (VFB) modulation using in situ Ti and Hf interposed in a metal/high-k gate stack. J. Appl. Phys. 2010, 108, 064107:1–064107:4. [Google Scholar]
  32. Huang, J.; Heh, D.; Sivasubramani, P.; Kirsch, P.D.; Bersuker, G.; Gilmer, D.C.; Quevedo-Lopez, M.A.; Hussain, M.M.; Majhi, P.; Lysaght, P.; et al. Gate first high-k/metal gate stacks with zero SiOx interface achieving EOT = 0.59 nm for 16 nm application. In Proceedings of VLSI Technology Symposium, Kyoto, Japan, 15–18 June 2009; pp. 34–35.
  33. Choi, K.; Jagannathan, H.; Choi, C.; Edge, L.; Ando, T.; Frank, M.; Jamison, P.; Wang, M.; Cartier, E.; Zafar, S.; et al. Extremely scaled gate-first high-k/metal gate stack with EOT of 0.55 nm using novel interfacial layer scavenging techniques for 22 nm technology node and beyond. In Proceedings of VLSI Technology Symposium, Kyoto, Japan, 15–18 June 2009; pp. 138–139.
  34. Ando, T.; Copel, M.; Bruley, J.; Frank, M.M.; Watanabe, H.; Narayanan, V. Physical origins of mobility degradation in extremely scaled SiO2/HfO2 gate stacks with la and al induced dipoles. Appl. Phys. Lett. 2010, 96, 132904:1–132904:3. [Google Scholar]
  35. Ragnarsson, L.Å.; Li, Z.; Tseng, J.; Schram, T.; Rohr, E.; Cho, M.J.; Kauerauf, T.; Conard, T.; Okuno, Y.; Parvais, B.; et al. Ultra low-EOT (5 Å) gate-first and gate-last high performance CMOS achieved by gate-electrode optimization. In Proceedings of IEEE International Electron Devices Meeting, Baltimore, MA, USA, 7–9 December 2009; pp. 663–666.
  36. Ragnarsson, L.Å.; Chiarella, T.; Togo, M.; Schram, T.; Absil, P; Hoffmann, T. Ultrathin EOT high-κ/metal gate devices for future technologies: Challenges, achievements and perspectives. Microelectron. Eng. 2011, 88, 1317–1322. [Google Scholar] [CrossRef]
  37. Ando, T.; Cartier, E.; Bruley, J.; Choi, K.; Narayanan, V. Origin of effective work function roll-off behavior for replacement gate process studied by low-temperature interfacial layer scavenging technique. In Presented at the 2011 IEEE Semiconductor Interface Specialists Conference, Arlington, VA, USA, 6–8 December 2011.
  38. Takahashi, M.; Ogawa, A.; Hirano, A.; Kamimuta, Y.; Watanabe, Y.; Iwamoto, K.; Migita, S.; Yasuda, N.; Ota, H.; Nabatame, T.; Toriumi, A. Gate-first processed FUSI/HfO2/HfSiOX/Si MOSFETs with EOT = 0.5 nm—Interfacial layer formation by cycle-by-cycle deposition and annealing. In Proceedings of IEEE International Electron Devices Meeting, Washington, DC, USA, 10–12 December 2007; pp. 523–526.
  39. Migita, S.; Morita, Y.; Mizubayashi, W.; Ota, H. Preparation of epitaxial HfO2 film (EOT = 0.5 nm) on Si substrate using atomic-layer deposition of amorphous film and rapid thermal crystallization (RTC) in an abrupt temperature gradient. In Proceedings of IEEE International Electron Devices Meeting, San Francisco, CA, USA, 6–8 December 2010; pp. 269–272.
  40. Jung, H.S.; Lee, J.H.; Han, S.K.; Kim, Y.S.; Lim, H.J.; Kim, M.J.; Doh, S.J.; Yu, M.Y.; Lee, N.I.; Lee, H.L.; et al. A highly manufacturable mips (metal inserted poly-Si stack) technology with novel threshold voltage control. In Proceedings of VLSI Technology Symposium, Kyoto, Japan, 14–18 June 2005; pp. 232–233.
  41. Hubbard, K.J.; Schlom, D.G. Thermodynamic stability of binary oxides in contact with silicon. J. Mater. Res. 1996, 11, 2757–2776. [Google Scholar] [CrossRef]
  42. Gusev, E.P.; Buchanan, D.A.; Cartier, E.; Kumar, A.; DiMaria, D.; Guha, S.; Callegari, A.; Zafar, S.; Jamison, P.C.; Neumayer, D.A.; et al. Ultrathin high-K gate stacks for advanced CMOS devices. In Proceedings of IEEE International Electron Devices Meeting, Washington, DC, USA, 3–5 December 2001; pp. 451–454.
  43. Narayanan, V.; Maitra, K.; Linder, B.P.; Paruchuri, V.K.; Gusev, E.P.; Jamison, P.; Frank, M.M.; Steen, M.L.; La Tulipe, D.; Arnold, J.; et al. Process optimization for high electron mobility in nMOSFETs with aggressively scaled HfO2/metal stacks. IEEE Electron Device Lett. 2006, 27, 591–594. [Google Scholar] [CrossRef]
  44. Guha, S.; Narayanan, V. Oxygen vacancies in high dielectric constant oxide-semiconductor films. Phys. Rev. Lett. 2007, 98, 196101:1–196101:4. [Google Scholar] [CrossRef]
  45. Kerber, A.; Cartier, E.A. Reliability challenges for CMOS technology qualifications with hafnium oxide/titanium nitride gate stacks. IEEE Trans. Device Mater. Rel. 2009, 9, 147–161. [Google Scholar] [CrossRef]
  46. Ando, T.; Sathaye, N.D.; Murali, K.V.R.M.; Cartier, E.A. On the electron and hole tunneling in a HfO2 gate stack with extreme interfacial-layer scaling. IEEE Electron Device Lett. 2011, 32, 865–867. [Google Scholar] [CrossRef]
  47. Kirsch, P.D.; Sivasubramani, P.; Huang, J.; Young, C.D.; Quevedo-Lopez, M.A.; Wen, H.C.; Alshareef, H.; Choi, K.; Park, C.S.; Freeman, K.; et al. Dipole model explaining high-k/metal gate field effect transistor threshold voltage tuning. Appl. Phys. Lett. 2008, 92, 092901:1–092901:3. [Google Scholar] [CrossRef]
  48. Kita, K.; Toriumi, A. Origin of electric dipoles formed at high-k/SiO2 interface. Appl. Phys. Lett. 2009, 94, 132902:1–132902:3. [Google Scholar]
  49. Jagannathan, H.; Watanabe, K.; Sunamura, H.; Ariyoshi, K.; Allegret-Maret, S.; Paruchuri, V.K. Impact of extreme scaling on cap layer induced dipoles in high-k metal gate stacks. In Presented at the 2011 IEEE Semiconductor Interface Specialists Conference, Arlington, VA, USA, 6–8 December 2011.
  50. Miyata, N.; Yasuda, T.; Abe, Y. Kelvin probe study on formation of electric dipole at direct-contact HfO2/Si interfaces. J. Appl. Phys. 2011, 110, 074115:1–074115:8. [Google Scholar] [CrossRef]
  51. Yamaguchi, S.; Tai, K.; Hirano, T.; Ando, T.; Hiyama, S.; Wang, J.; Hagimoto, Y.; Nagahama, Y.; Kato, T.; Nagano, K.; et al. High Performance Dual Metal Gate CMOS with High Mobility and Low Threshold Voltage Applicable to Bulk CMOS Technology. In Proceedings of VLSI Technology Symposium, Honololu, HA, USA, 13–17 June 2006; pp. 152–153.
  52. Hyun, S.; Han, J.H.; Park, H.B.; Na, H.J.; Son, H.J.; Lee, H.Y.; Hong, H.S.; Lee, H.L.; Song, J.; Kim, J.J.; et al. Aggressively scaled high-k last metal gate stack with low variability for 20 nm logic high performance and low power applications. In Proceedings of VLSI Technology Symposium, Kyoto, Japan, 13–17 June 2011; pp. 32–33.
  53. Veloso, A.; Ragnarsson, L.Å.; Cho, M.J.; Devriendt, K.; Kellens, K.; Sebaai, F.; Suhard, S.; Brus, S.; Crabbe, Y.; Schram, T.; et al. Gate-last vs. gate-first technology for aggressively scaled EOT Logic/RF CMOS. In Proceedings of VLSI Technology Symposium, Kyoto, Japan, 13–17 June 2011; pp. 34–35.
  54. Akiyama, K.; Wang, W.; Mizubayashi, W.; Ikeda, M.; Ota, H.; Nabatame, T.; Toriumi, A. VFB roll-off in HfO2 gate stack after high temperature annealing process—A crucial role of out-diffused oxygen from HfO2 to Si. In Proceedings of VLSI Technology Symposium, Kyoto, Japan, 12–16 June 2007; pp. 72–73.
  55. Bersuker, G.; Park, C.S.; Wen, H.C.; Choi, K.; Price, J.; Lysaght, P.; Tseng, H.H.; Sharia, O.; Demkov, A.; Ryan, J.T.; Lenahan, P. Origin of the flatband-voltage roll-off phenomenon in metal/high-κ gate stacks. IEEE Trans. Electron Devices 2010, 57, 2047–2056. [Google Scholar] [CrossRef]
  56. Pandey, R.K.; Murali, K.V.R.M.; Furkay, S.S.; Oldiges, P.J.; Nowak, E.J. Crystallographic-orientation-dependent gate-induced drain leakage in nanoscale MOSFETs. IEEE Trans. Electron Devices 2010, 57, 2098–2105. [Google Scholar] [CrossRef]
  57. Yang, H.; Niimi, H.; Keister, J.W.; Lucovsky, G.; Rowe, J.E. The effects of interfacial sub-oxide transition regions and monolayer level nitridation on tunneling currents in silicon devices. IEEE Electron Device Lett. 2000, 21, 76–78. [Google Scholar] [CrossRef]
  58. Akasaka, Y.; Nakamura, G.; Shiraishi, K.; Umezawa, N.; Yamabe, K.; Ogawa, O.; Lee, M.; Amiaka, T.; Kasuya, T.; Watanabe, H.; et al. Modified oxygen vacancy induced fermi level pinning model extendable to P-metal pinning. Jpn. J. Appl. Phys. 2006, 45, L1289–L1292. [Google Scholar] [CrossRef]
  59. Kerber, A.; Pantisano, L.; Veloso, A.; Groeseneken, G.; Kerber, M. Reliability screening of high-κ dielectrics based on voltage ramp stress. Microelectron. Reliab. 2007, 47, 513–517. [Google Scholar] [CrossRef]
  60. Kerber, A.; Krishnan, S.A.; Cartier, E.A. Voltage ramp stress for bias temperature instability testing of metal-gate/high-κ stacks. IEEE Electron Device Lett. 2009, 30, 1347–1349. [Google Scholar] [CrossRef]
  61. Cartier, E.; Kerber, A.; Ando, T.; Frank, M.M.; Choi, K.; Krishnan, S.; Linder, B.; Zhao, K.; Monsieur, F.; Stathis, J.; Narayanan, V. Fundamental aspects of HfO2-based high-κ metal gate stack reliability and implications on tinv-scaling. In Proceedings of IEEE International Electron Devices Meeting, Washington, DC, USA, 5–7 December 2011; pp. 18.4.1–18.4.4.
  62. Fischetti, M.V.; Neumayer, D.A.; Cartier, E.A. Effective electron mobility in Si inversion layers in metal-oxide-semiconductor systems with a high-κ insulator: The role of remote phonon scattering. J. Appl. Phys. 2001, 90, 4587–4608. [Google Scholar] [CrossRef]
  63. Yamaguchi, T.; Iijima, R.; Ino, T.; Nishiyama, A.; Satake, H.; Fukushima, N. Additional scattering effects for mobility degradation in Hf-silicate gate MISFETs. In Proceedings of IEEE International Electron Devices Meeting, Washington, DC, USA, 8–10 December 2002; pp. 621–624.
  64. Saito, S.; Hisamoto, D.; Kimura, S.; Hiratani, M. Unified mobility model for high-κ gate stacks. In Proceedings of IEEE International Electron Devices Meeting, Washington, DC, USA, 8–10 December 2003; pp. 797–800.
  65. Ando, T.; Shimura, T.; Watanabe, H.; Hirano, T.; Yoshida, S.; Tai, K.; Yamaguchi, S.; Iwamoto, H.; Kadomura, S.; Toyoda, S.; et al. Mechanism of carrier mobility degradation induced by crystallization of HfO2 gate dielectrics. Appl. Phys. Express 2009, 2, 071402:1–071402:3. [Google Scholar] [CrossRef]
  66. Ota, H.; Hirano, A.; Watanabe, Y.; Yasuda, N.; Iwamoto, K.; Akiyama, K.; Okada, K.; Migita, S.; Nabatame, T.; Toriumi, A. Intrinsic origin of electron mobility reduction in high-κ MOSFETs from remote phonon to bottom interface dipole scattering. In Proceedings of IEEE International Electron Devices Meeting, Washington, DC, USA, 10–12 December 2007; pp. 65–68.
  67. Takagi, S.; Toriumi, A.; Iwase, M.; Tango, H. On the universality of inversion layer mobility in Si MOSFET’s: Part I—Effects of substrate impurity concentration. IEEE Trans. Electron Devices 1994, 41, 2257–2362. [Google Scholar]
  68. Copel, M.; Cartier, E.; Ross, F.M. Formation of a stratified lanthanum silicate dielectric by reaction with Si(001). Appl. Phys. Lett. 2001, 78, 1607–1609. [Google Scholar] [CrossRef]
  69. Li, J.; Ma, T.P. Scattering of silicon inversion layer electrons by metal/oxide interface roughness. J. Appl. Phys. 1987, 62, 4212–4215. [Google Scholar] [CrossRef]
  70. Takagi, S.; Irisawa, T.; Tezuka, T.; Numata, T.; Nakaharai, S.; Hirashita, N.; Moriyama, Y.; Usuda, K.; Toyoda, E.; Dissanayake, S.; et al. Carrier-transport-enhanced channel CMOS for improved power consumption and performance. IEEE Trans. Electron Devices 2008, 55, 21–39. [Google Scholar] [CrossRef]
  71. Saitoh, M.; Uchida, K. Universal relationship between low-field mobility and high-field carrier velocity in high-κ and SiO2 gate dielectric MOSFETs. In Proceedings of IEEE International Electron Devices Meeting, Washington, DC, USA, 11–13 December 2006; pp. 261–264.
  72. Natori, K. Ballistic metal-oxide-semiconductor field effect transistor. J. Appl. Phys. 1994, 76, 4879–4890. [Google Scholar] [CrossRef][Green Version]
  73. Lochtefeld, A.; Antoniadis, D.A. On experimental determination of carrier velocity in deeply scaled NMOS: How close to the thermal limit? IEEE Electron Device Lett. 2001, 22, 95–97. [Google Scholar] [CrossRef]
  74. Lundstrom, M.S. On the mobility versus drain current relation for a nanoscale MOSFET. IEEE Electron Device Lett. 2001, 22, 293–295. [Google Scholar] [CrossRef]
  75. Tatsumura, K.; Goto, M.; Kawanaka, S.; Kinoshita, A. Correlation between low-field mobility and high-field carrier velocity in quasi-ballistic-transport MISFETs scaled down to Lg = 30 nm. In Proceedings of IEEE International Electron Devices Meeting, Washington, DC, USA, 7–9 December 2007; pp. 1–4.

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Ando, T. Ultimate Scaling of High-κ Gate Dielectrics: Higher-κ or Interfacial Layer Scavenging? Materials 2012, 5, 478-500. https://doi.org/10.3390/ma5030478

AMA Style

Ando T. Ultimate Scaling of High-κ Gate Dielectrics: Higher-κ or Interfacial Layer Scavenging? Materials. 2012; 5(3):478-500. https://doi.org/10.3390/ma5030478

Chicago/Turabian Style

Ando, Takashi. 2012. "Ultimate Scaling of High-κ Gate Dielectrics: Higher-κ or Interfacial Layer Scavenging?" Materials 5, no. 3: 478-500. https://doi.org/10.3390/ma5030478

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