# An Examination of AC/HVDC Power Circuits for Interconnecting Bulk Wind Generation with the Electric Grid

^{*}

## Abstract

**:**

## 1. Introduction

**Figure 1.**A simplified single line diagram of a sample HVDC interconnection of wind generation sources and ac grids.

## 2. HVDC Converter Topologies, a Brief Review

#### 2.1. Current Sourced Converter (CSC)

**Figure 2.**(a) Simplified schematic of the typical 12-pulse CSC implementation for HVDC (b) a 6 pulse thyristor bridge (c) thyristor (SCR) sub-module.

#### 2.2. Voltage Sourced Converter (VSC)

**Figure 3.**(a) Simplified schematic of a 2-level voltage sourced converter HVDC implementation, (b) IGBT-diode Sub-Module.

#### 2.3. Bridge of Bridge Converter (BoBC)

**Figure 4.**(a) Simplified BoBC schematic for HVDC realization (b) Simplified BoBC sub-module schematic, half bridge configuration.

## 3. Converter Comparison

#### 3.1. Power Semiconductor Requirements

_{p}) for practical reactive component design such as the dc link capacitance and line filters. Furthermore, most IGBT packs have an anti-parallel diode integrated into the planar module making their implementation simpler. Unlike the CSC or the VSC, whose N series devices must switch simultaneously, the BoBC may stagger the switching amongst the sub-modules allowing each sub-module to switch at a lower frequency, typically on the order of 3f

_{p}[13]. Congruence of maintaining switching signals in the BoBC is less critical due to this reason, and hence leads to a more robust realization of the control. This further has an impact on reactive component sizing and will be covered in greater detail in passive component discussion section. Due to the low switching frequency of the BoBC sub-modules, while any of the proposed two quadrant switching packages may be used for the BoBC, IGCTs become a natural choice due to their lower conduction losses in comparison to IGBTs. The viable choices for semiconductors for each converter topology are summarized in Table 1.

CSC | VSC | BoBC | |
---|---|---|---|

Device type | SCR | IGBT | IGCT |

_{dc}. Unlike the CSC and VSC topologies whose arm currents are entirely dc, the BoBC has both ac and dc current flowing in each arm in order to facilitate power conversion. Each of the six arms of the BoBC has an ac current component of 1/2 I

_{ph}and a dc component of 1/3 I

_{dc}flowing through it. Simply put, the arm current is largely ac with a dc offset. Furthermore, due to the asymmetry of the half bridge, the devices forming the two throws of the bridge have unequal current stress levels. Also note that the BoBC does not require the use a transformer to step up the generation voltage prior to the converter as in the CSC or VSC. In applications using the BoBC, the converter itself may act as the transformer for the purposes of voltage matching with an apparent transformer ratio Q

_{bobc}. In such a case, Q

_{bobc}for the BoBC is equivalent to Q

_{tran}for the other converters, since they all perform the same task with the same input and output quantities. However, since the input ac voltage to the BoBC may be lower than the CSC or VSC by a factor of the transformer ratio Q

_{tran}, conservation of energy dictates that the ac component of the BoBC arm current increase by a factor of Q

_{tran}as well. On this basis of this discussion, the average converter device currents and voltages for the three topologies in their per unit form are summarized in Table 2. Detailed derivations of these quantities are shown in the Appendix.

CSC | VSC | BoBC |
---|---|---|

${I}_{arm\_pu}=\frac{1}{\pi \sqrt{2}{Q}_{tran}}(\mathrm{cos}(\alpha )+1)$ | ${I}_{arm\_pu}=\frac{\sqrt{2}}{\pi {Q}_{tran}}$ | ${I}_{arm\_pu}=\frac{\pi}{3\sqrt{6}{Q}_{bobc}}+\frac{\sqrt{2}}{\pi}$ |

${I}_{T\_pu}={I}_{arm\_pu}$ | ${I}_{T\_pu}=\frac{1}{\sqrt{2}\pi {Q}_{tran}}+\frac{\pi}{6\sqrt{6}{Q}_{tran}}$ | ${I}_{T1\_pu}={I}_{D1\_pu}=\frac{1}{2\pi \sqrt{2}}-\frac{\pi \sqrt{2}}{54{{Q}_{bobc}}^{2}}\approx \frac{1}{2\pi \sqrt{2}}$ |

${I}_{D\_pu}=\frac{1}{\sqrt{2}\pi {Q}_{tran}}-\frac{\pi}{6\sqrt{6}{Q}_{tran}}$ | ${I}_{T2\_pu}={I}_{D2\_pu}=\frac{1}{2\pi \sqrt{2}}+\frac{\pi}{3\sqrt{6}{Q}_{bobc}}+\frac{\pi \sqrt{2}}{54{{Q}_{bobc}}^{2}}\approx \frac{1}{2\pi \sqrt{2}}$ | |

${V}_{T\_pu}=\frac{1}{{N}_{\mathrm{csc}}+1}$ | ${V}_{T\_pu}={V}_{D\_pu}=\frac{1}{{N}_{vsc}+1}$ | ${V}_{T\_pu}={V}_{D\_pu}=\frac{1}{{N}_{bobc}+1}$ |

CSC | VSC | BoBC | |
---|---|---|---|

Device Type | Thyristor (SCR) | IGBT-diode pair | IGCT –diode pair |

Blocking voltage (kV) | 6.5 | 6.5 | 4.5 |

Part number | ABB 5STP 03X6500 | ABB 5SNA 0400J650100 | ABB 5SHX 14H4510 |

De-rated application voltage V_{ca}(kV) | 3.3 | 3 | 2.8 |

Number of series sub-modules per arm | ${N}_{\mathrm{csc}}=ceil\left[\frac{{V}_{dc}}{{V}_{ca}}\right]+1=46$ | ${N}_{vsc}=ceil\left[\frac{{V}_{dc}}{{V}_{ce}}\right]+1=38$ | ${N}_{bobc}=ceil\left[\frac{{V}_{dc}}{{V}_{Csm}}\right]+1=55$ |

Total number of devices | 276 thyristors | 228 IGBT-diode pairs | 330 IGCT-diode pairs |

Total semiconductor MVA (p.u.) | 4.1 | 6.6 | 17.8 |

#### 3.2. Reactive Component Requirements & Waveform Quality

#### 3.2.1. AC side Reactive Components

^{th}harmonic. Although the design evaluation of such filters is not considered in detail in this paper, a representative ac side filter rated at 0.25 p.u. is considered to be typical [41]. Unlike the VSC, the BoBC does not require any ac side reactive components as the energy storage elements are contained within the individual sub-modules. The ac side reactive component requirements are summarized in Table 4.

CSC | VSC | BoBC | |
---|---|---|---|

Transformer rating MVA (p.u) | 1.1 | 1.04 | 1.0 (optional) |

Lowest harmonic number Pulse Number, N_{pulse} | $6{N}_{rect}=12$ | ${f}_{sw}/{f}_{p}=40$ | ${N}_{bobc}{f}_{sw}/{f}_{p}=165$ |

Switching frequency filter MVA (p.u) | 0.35 | 0.25 | 0 |

Displacement power factor correction MVA (p.u) | 0.5 | 0 | 0 |

Total ac side reactive component MVA (p.u.) | 1.95 | 1.29 | (optional) |

#### 3.2.2. Sub-Module Reactive Components

_{T1}or I

_{D1}from Table 2. Assuming an allowable peak-to-peak voltage ripple V

_{rip}of 10% using a base time-scale of 1/ω

_{B}and dc voltage base, the capacitance may be found using (3.1) and (3.2). It should be noted that due to the inherently large arm currents of this converter each sub-module, the dc link capacitor is relatively large.

_{Bac}

_{bobc}sub-modules placed in series with the converter arm. Obviously, the inductor must be sized to accommodate the average arm current, i

_{arm}in Table 2. For the purpose of selecting a necessary value of inductance, an acceptable amount of ripple current and time period due to switching must be selected. As the arm current contains significant dc and ac components, the rms combination of the two will serve as the baseline for a nominal amount of 20%. The time period over which this ripple occurs is a function of switching frequency of each level and the number of levels. If each level’s switching is phase shifted from the next, an effective pulse number from Table 4 may be used in calculating the lump sum inductance. Using the BoBC averaged model [29], the inductance may be calculated by means of (3.4) and (3.5).

_{Bac}

Inductor size, L_{arm_pu} | 0.031 |

Inductor RMS current, I_{arm} | 0.5 |

BoBC total inductor MVA | 0.028 |

Capacitor size, C_{sm} | 70 |

Capacitor RMS current, i_{cb-rms} | 0.25 |

BoBC total capacitor MVA | 9.3 |

Sub-module stored energy | 0.13 |

BoBC total stored energy | 43 |

#### 3.2.3. DC Side Reactive Components

_{Bdc}

_{Bdc}

CSC | VSC | |
---|---|---|

Inductor size, L_{csc} | 1.3 | ---- |

Average inductor current, I_{dc} | 1 | ---- |

Inductor MVA | 1 | ---- |

Capacitor size, C_{vsc} | ---- | 1.7 |

Capacitor RMS current, i_{cv-rms} | ---- | 0.58 |

Capacitor MVA | ---- | 0.58 |

Total converter stored energy | 0.104 | 0. 126 |

#### 3.3. System Operating Losses

_{sw}and I

_{D}are not average value currents and must be calculated using the current amplitude at the switching event. In addition, the BoBC possesses asymmetries in the converter arms regarding the direction of dc current which must be accounted for. A more thorough treatment of these two caveats may be found in [13]. As seen in (3.11), the switching losses are directly proportional to switching frequency, which characterizes the VSC as switching loss dominant. The BoBC switches at frequency 1/N

_{BoBC}times less than the VSC due to its capability to offset switching between levels, which results in lower switching losses. This situation is the dual to the VSC and BoBC conductive losses discussed earlier. The calculated semiconductor losses for all three topologies in the benchmark application are listed in Table 7.

CSC | VSC | BoBC | |
---|---|---|---|

Device Conduction Losses (p.u.) | 0.0026 | 0.0031 | 0.024 |

Device Switching Losses (p.u.) | ---- | 0.023 | 0.0084 |

Total Semiconductor Losses (p.u.) | 0.0026 | 0.026 | 0.033 |

Transformer & Filter Losses (p.u.) | 0.01 | 0.01 | 0.01 |

Total Capacitor Losses (p.u.) | ---- | 3·10^{-5} | 4.7·10^{-4} |

Total losses (p.u.) | 0.013 | 0.036 | 0.043 |

Efficiency (%) | 98.7 | 96.5 | 95.7 |

#### 3.4. Multi-terminal Operation

CSC | VSC | BoBC | |
---|---|---|---|

Multi-terminal Operation | 0 | 0 | 0 |

Weak ac network compatibility | 1 | 0 | 0 |

Multi-terminal rank | 2^{nd} | 1^{st} | 1^{st} |

#### 3.5. Fault Tolerance

_{1}) in an on state, which will reverse bias the freewheeling diodes thus preventing them from feeding the fault. The number of sub-modules required during such events is determined by the magnitude of the ac line voltage.

CSC | VSC | BoBC | |
---|---|---|---|

Controllable HVDC fault current | 0 | 1 | 0 |

HVDC breakers necessary? | 0 | 1 | 0 |

Possible HV Transformer Fault? | 1 | 1 | 0 |

Fast Dynamic response? | 1 | 0 | 0 |

Fault tolerance rank | 2^{nd} | 3^{rd} | 1^{st} |

#### 3.6. Modularity & Complexity

CSC | VSC | BoBC | |
---|---|---|---|

Degree of Modularity | 1 | 1 | 0 |

Stand Alone Sub-Module | 1 | 1 | 0 |

Ease of integration | 0 | 1 | 0 |

Relative control complexity | 0 | 0 | 1 |

Modularity & integration rank | 2^{nd} | 3^{rd} | 1^{st} |

## 4. Conclusions

CSC | VSC | BoBC | |
---|---|---|---|

Semiconductor MVA | 4.1 (p.u.) | 6.6 (p.u.) | 17.8 (p.u.) |

Total capacitor MVA | ---- | 0.58 (p.u.) | 9.3 (p.u.) |

Total inductor MVA | 1 (p.u.) | ---- | 0.028 (p.u.) |

AC filter/reactor & transformer MVA | 1.95 (p.u.) | 1.29 (p.u.) | 1 (p.u.) optional |

Stored energy | 0.104 (p.u.) | 0.126 (p.u.) | 43 (p.u.) |

Converter losses | 0.013 (p.u.) | 0.036 (p.u.) | 0.043 (p.u.) |

Converter efficiency | 98.7% | 96.5% | 95.7% |

CSC | VSC | BoBC | |
---|---|---|---|

Multi-terminal operation rank | 2nd | 1st | 1st |

Fault tolerance rank | 2nd | 3rd | 1st |

Modularity & integration rank | 2nd | 3rd | 1st |

Technology maturity level | 1st | 2nd | 3rd |

## Acknowledgements

## Nomenclature

V_{S} | Source rms phase voltage, [kV] |

V_{ph} | converter rms phase voltage, [kV] |

V_{dc} | HVDC output voltage, [kV] |

V_{Csm} | BoBC sub-module dc bus voltage [kV] |

V_{sm} | BoBC sub-module output voltage [kV] |

V_{ca} | Thyristor cathode-anode voltage [kV] |

V_{ce} | IGBT collected-emitter voltage [kV] |

V_{ca_i} | IGCT cathode-anode voltage [kV] |

Q_{tran} | CSC & VSC transformer turns ratio |

Q_{bobc} | BoBC apparent transformer turns ratio |

α | CSC thyristor firing angle |

m | VSC modulation index |

d_{sm} | BoBC sub-module duty cycle |

I_{S} | Source rms phase current, [A] |

I_{ph} | Converter rms phase current, [A] |

I_{dc} | HVDC output current, [A] |

I_{arm} | Converter rms arm current, [A] |

i_{cv-rms} | VSC rms capacitor current, [A] |

i_{cb-rms} | BoBC rms capacitor current, [A] |

C_{vsc} | VSC dc bus capacitance, [μF] |

C_{sm} | BoBC sub-module capacitance, [μF] |

L_{csc} | CSC HVDC line inductance, [H] |

L_{sm} | BoBC sub-module inductance, [μH] |

L_{arm} | BoBC arm inductance, [μH] |

N_{csc} | Number of sub-modules, CSC |

N_{vsc} | Number of sub-modules, VSC |

N_{bobc} | Number of sub-modules, BoBC |

f_{sw} | Switching frequency |

f_{p} | Power frequency |

N_{pulse} | Lowest harmonic pulse number |

## Appendix: Per-Unit base quantities and selected derivations

Power base, P_{B} | 50 MVA |

Frequency base, f_{B}, ω_{B} | 60 Hz, 377 rads/s |

Energy base, E_{B} | ${E}_{B}/{f}_{B}$ = 833 kJ |

AC source voltage base, V_{Bs} | 13.8 kV rms |

Converter AC voltage base, V_{Bph} | 117 kV rms |

DC voltage base, V_{Bdc} | 150 kV |

AC source current base, I_{Bs} | ${P}_{B}/\sqrt{3}{V}_{Bs}$ = 2092 A rms |

DC current base, I_{Bdc} | ${P}_{B}/{V}_{Bdc}$ = 333 A |

AC Impedance base, Z_{Bac} | ${V}_{Bs}/{I}_{Bs}$ = 6.6 Ω |

DC Impedance base, Z_{Bdc} | ${V}_{Bdc}/{I}_{Bdc}$ = 450 Ω |

AC Inductance base, L_{Bac} | ${Z}_{Bac}/{\omega}_{B}$ = 17.5 mH |

DC Inductance base, L_{Bdc} | ${Z}_{Bdc}/{\omega}_{B}$ = 1.2 H |

AC Capacitance base, C_{Bac} | $1/\left({Z}_{Bac}{\omega}_{B}\right)$ = 400 μF |

DC Capacitance base, C_{Bdc} | $1/\left({Z}_{Bdc}{\omega}_{B}\right)$ = 5.9 μF |

#### Current Sourced Converter semiconductor selected derivations

_{T}per-unitized to the source current yields:

#### Voltage Sourced Converter semiconductor device current and voltage derivations

_{ph}and I

_{dc}and per-unitizing to the source current the arm/device currents may be written as:

#### Bridge of Bridge Converter semiconductor device current and voltage derivations

_{arm}(t)and the sub-module duty ratio d

_{sm}(t). Since the average capacitor current over a power cycle must be zero the transistor and diode currents I

_{T1}and I

_{D1}must have equivalent average values over one cycle as well. With this, the currents may be calculated as follows:

_{T1}and I

_{D1}, we obtain:

**, which is identical to the ratio of the actual transformer used in the CSC and VSC.**

_{bobc}_{dc}, I

_{dc}, and I

_{ph}along with per-unitizing to the source current the arm and device currents may be written as:

_{bobc}grows large

_{bobc}grows large

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## Share and Cite

**MDPI and ACS Style**

Ludois, D.; Venkataramanan, G.
An Examination of AC/HVDC Power Circuits for Interconnecting Bulk Wind Generation with the Electric Grid. *Energies* **2010**, *3*, 1263-1289.
https://doi.org/10.3390/en3061263

**AMA Style**

Ludois D, Venkataramanan G.
An Examination of AC/HVDC Power Circuits for Interconnecting Bulk Wind Generation with the Electric Grid. *Energies*. 2010; 3(6):1263-1289.
https://doi.org/10.3390/en3061263

**Chicago/Turabian Style**

Ludois, Daniel, and Giri Venkataramanan.
2010. "An Examination of AC/HVDC Power Circuits for Interconnecting Bulk Wind Generation with the Electric Grid" *Energies* 3, no. 6: 1263-1289.
https://doi.org/10.3390/en3061263