# Three-Leg Quasi-Z-Source Inverter with Input Ripple Suppression for Renewable Energy Application

^{1}

^{2}

^{*}

^{†}

## Abstract

**:**

_{PN}falls from 70.75 V to 6.54 V, representing a reduction of 90.76%. The Total Harmonic Distortion (THD) of the output voltage and current are both less than 1%. The simulation results validated the feasibility of the proposed approach.

## 1. Introduction

_{1}and C

_{2}. Compared to traditional quasi-Z-source inverter photovoltaic power generation systems, although the capacitance value is reduced, the voltage stress of the switch increases slightly, leading to a decrease in efficiency.

## 2. Circuit Topology and Operating Principle of the Proposed Inverter

#### 2.1. Traditional Quasi-Z-Source Inverter and the Analysis of Its Secondary Ripple

_{1}= C

_{2}and L

_{1}= L

_{2}, which can be obtained as follows:

_{C1}and V

_{C2}represent the voltages across the capacitors C

_{1}and C

_{2}, while V

_{L}

_{1}and V

_{L}

_{2}denote the voltages across inductors L

_{1}and L

_{2}, respectively.

_{1}and L

_{2}store energy, while capacitors C

_{1}and C

_{2}release energy. Equations (2) and (3) can be obtained using Kirchhoff’s Voltage Law (KVL) and Kirchhoff’s Current Law (KCL):

_{i}represents the DC input current, and V

_{PN}represents the DC bus voltage.

_{C1}and i

_{C2}represent the currents flowing through capacitors C

_{1}and C

_{2}, respectively. i

_{VD}represents the current flowing through diode VD. i

_{L1}and i

_{L2}represent the currents flowing through inductors L

_{1}and L

_{2}, respectively. i

_{PN}represents the DC bus current.

_{1}and L

_{2}release energy, while the capacitors C

_{1}and C

_{2}store energy. Equations (4) and (5) can be obtained from KVL and KCL:

_{1}and L

_{2}are both zero within one cycle. Using Equations (2) and (4) and the volt-second balance, Equation (6) can be obtained:

_{0}is the time in the shoot-through state, T

_{1}is the time in the non-shoot-through state, and the period T = T

_{0}+ T

_{1}.

_{1}and L

_{2}.

_{L}is the power factor angle, and V

_{o}and I

_{o}are the rms output voltage and current, respectively.

_{PN}can be expressed as

_{PN}is the DC component, and ${\tilde{i}}_{PN-2\mathsf{\omega}}$ is the 2ω component of the DC bus current. The inductor currents i

_{L1}and i

_{L2}and capacitor voltages v

_{C1}and v

_{C2}in the impedance network are directly influenced via i

_{PN}, so that

_{1}= L

_{2}= L, C

_{1}= C

_{2}= C). From Equations (17) and (18), one can write

_{1}and the voltage of capacitor C

_{1}, respectively.

#### 2.2. Circuit Topology of the Proposed Inverter

_{1}= L

_{2}and C

_{1}= C

_{2}.

#### 2.3. Operating Principle of the Proposed Inverter

_{T}indicates the shoot-through state, while S (S

_{A}, S

_{B}, S

_{E}) indicates the non-shoot-through state, where S

_{A}, S

_{B}, and S

_{E}can take the value of 0 or 1, the value of 0 indicates that the switch below the corresponding bridge leg is turned on, and the value of 1 indicates that the switch above the corresponding bridge leg is turned on. The topology operating states and points A, B, and E voltage are shown in Table 1.

_{A}, v

_{B}, and v

_{E}, respectively, only have two possible values: V

_{PN}and 0. Using the Fourier transform, v

_{A}, v

_{B}, and v

_{E}can be expressed as follows

_{dcA}represents the DC component of the voltage at point A, while A

_{n}represents the amplitude of the nth harmonic component of the voltage at point A. V

_{dcB}represents the DC component of the voltage at point B, and B

_{n}represents the amplitude of the nth harmonic component of the voltage at point B. V

_{dc2}represents the DC component of the voltage at point E, and V

_{n}represents the amplitude of the nth harmonic component of the voltage at point E.

_{dc1}represents the DC component of the voltage at point A and point B.

_{o1}and v

_{o2}represent the voltages across the output filter capacitors C

_{f1}and C

_{f2}, respectively, while i

_{o1}and i

_{o2}represent the currents through the output filter inductors L

_{f1}and L

_{f2}, respectively. C

_{f}denotes the output filter capacitor, C

_{f1}= C

_{f2}= C

_{f}, V

_{dc}= V

_{dc2}− V

_{dc1}, and

_{1}+ B

_{2}= 0 into Equations (24) and (27), the following results can be obtained

_{E}; therefore, Q

_{E}can be expressed as follows

_{i}= 144 V, V

_{dc}= 150 V, C

_{f}= 52 μf, V

_{o}= 110 V, and φ

_{L}= 0. Analysis of Table 2 indicates that the harmonic content of the input current is relatively insignificant in comparison to the DC component when the additional bridge leg injects second and fourth harmonic voltages simultaneously. However, injecting second, third, and fourth harmonic voltages actually increases the ripple content of the input current. These observations reveal that injecting specific combinations of harmonic voltages can impact the harmonic content of the input current, highlighting the importance of carefully selecting the appropriate harmonic injection strategy to minimize undesirable effects on the system.

_{com1}and V

_{com2}.

_{A}, v

_{B}, and v

_{E}satisfy Equations (37) and (38), the inverter can simultaneously achieve boosting, inversion, and low-frequency ripple suppression of input current.

## 3. The Control Strategy of the Proposed Inverter

^{2}+ ω

^{2}. This process enables accurate tracking of the sinusoidal signal without any static errors.

_{rA}, u

_{rB}, and u

_{rE}, with a triangular waveform u

_{c}as the carrier signal. When u

_{r}≥ u

_{c}, the switches of the upper leg of the corresponding bridge leg are turned on, while the switches of the lower leg are turned off. When u

_{r}≤ u

_{c}, the switches of the upper leg of the corresponding bridge leg are turned off, and the switches of the lower leg are turned on. When u

_{c}≥ V

_{com1}or u

_{c}≤ V

_{com2}, the bridge leg is in a shoot-through state.

## 4. Parameter Design of the System

#### 4.1. Parameter Design of Inductance and Capacitance in Impedance Network

_{1}and L

_{2}, as well as the capacitance C

_{1}and C

_{2}in the impedance network, satisfy the following relationship, they can suppress the switching frequency current ripple and voltage ripple, respectively.

_{1}denotes the percentage of current ripple at the frequency of the inductive switch, W

_{2}represents the percentage of voltage ripple at the frequency of the capacitive switch, W

_{1}is usually selected as 20%, and W

_{2}is selected as 1%. D denotes the duty cycle of the shoot-through, and f

_{s}represents the switching frequency.

#### 4.2. Parameter Design for Modulation of the Third Bridge Leg

_{dc}and C

_{f}in Equation (32) is directly correlated with crucial circuit parameters, such as the input voltage level and the voltage stress on switches, which impact the overall performance of the circuit. Therefore, a more comprehensive and in-depth analysis is required to thoroughly understand the interdependence of these parameters.

_{dc}and V

_{2}can be obtained when S = 300 VA, C

_{f}= 52 μf, and φ

_{L}= 0, as shown in Figure 9. From Figure 9, it can be inferred that the value of V

_{2}decreases as the value of V

_{dc}increases. Hence, it is crucial to avoid selecting an excessively small value for V

_{dc}to prevent V

_{2}from becoming excessively large. Furthermore, the values of V

_{dc}and V

_{2}are closely related to the magnitude of V

_{PN}; the DC bus voltage, which is dependent on the input voltage; and the shoot-through duty cycle. As a result, the value of V

_{dc}should also not be excessively large.

_{dc}within the range of 100 V to 200 V is more reasonable. The minimum value of V

_{PN}is related to other parameters, as shown in Table 3. It is worth noting that V

_{PNmin}remains constant for both schemes. According to Equation (31), when the second harmonic power in the output power is cancelled out due to the second harmonic power in the p

_{2cf}, Equation (40) can be obtained.

_{dc1}is greater than V

_{dc2}, the following situations occur:

_{V2}is located in the second quadrant. When $\left|{V}_{o}{I}_{o}\mathrm{sin}{\mathsf{\phi}}_{\mathrm{L}}\right|\le \left|\mathsf{\omega}{C}_{f}{V}_{o}^{2}/2\right|,\mathrm{tan}{\mathsf{\phi}}_{\mathrm{V}2}\ge 0,\mathrm{sin}{\mathsf{\phi}}_{\mathrm{V}2}\le 0,$ φ

_{V2}is located in the third quadrant.

_{dc1}is less than V

_{dc2}, φ

_{V2}is always located in the first or fourth quadrant. Therefore, it can be seen that selecting the second scheme where V

_{dc1}≤ V

_{dc2}is more in line with the actual situation and easier to implement. Therefore, V

_{dc1}is chosen to be less than or equal to V

_{dc2}, and the value of V

_{dc}is set to 150 V.

_{dc1}≤ V

_{dc2}, V

_{dc}= 150 V is chosen, and one can simply write

_{PNmin}, and capacitance, C

_{f}, is presented in Figure 10 for the specific case of S = 300 VA, V

_{dc}= 150 V, and φ

_{L}= 0. Furthermore, Figure 10 depicts the relationship between V

_{PNmin}and the power factor angle, φ

_{L}, in the case of S = 300 VA, C

_{f}= 52 uF, and V

_{dc}= 150 V.

_{2}should be 20 to 30% of V

_{dc}when V

_{dc}is chosen as 150 V. Otherwise, it will affect the boosting capability of the quasi-Z-source inverter, thus affecting the value of the DC bus voltage. From Equation (42), the relationship between the injected secondary voltage amplitude V

_{2}and the filter capacitor C

_{f}can be obtained. Based on the range of values for the injected secondary voltage amplitude, the range of C

_{f}can be determined to be 36 to 56 μF.

_{f}is intimately tied to both the voltage stress experienced by the switches and the overall capacity of the system. Hence, a comprehensive evaluation of these factors is crucial in determining the optimal value for capacitance C

_{f}. If the capacitance is too large, it will significantly increase the size of the inverter and the current flowing through the capacitor, which reduces the power density of the inverter and increases the current stress on the power switching devices. Similarly, if the capacitance is too small, the demand for the minimum DC bus voltage is too high, and the voltage stress on the power switching devices increases, which limits the selection of the switching devices.

## 5. Simulation Results

#### 5.1. Simulation of the System under Full Load

_{1}and C

_{2}are 360 V and 216 V, respectively; and the DC bus voltage V

_{PN}is 576 V. According to Figure 11a, it can be observed that the inductor current ripple ΔI is 1.89 A, which is 90.87% of the theoretical value. Figure 11b,c show the voltage ripples across capacitor C

_{1}and C

_{2}are 34.74 V and 35.57 V, respectively. Figure 11d shows the DC bus voltage ripple ΔV

_{PN}is 70.75 V, which accounts for 12.28% of the theoretical value. Figure 11e is an enlarged view of the DC bus voltage V

_{PN}, and Figure 11f is a further enlarged view of Figure 11e. When V

_{PN}is 0, it is in a shoot-through state, and the shoot-through state duty cycle can be calculated as 0.376 from Figure 11f, which is consistent with the set value.

_{1}is 0.513 A, and Figure 13b,c show the ripples of the voltage across capacitors C

_{1}and C

_{2}ΔV are 3.3 V and 3.4 V respectively, accounting for only 0.92% and 1.57% of their theoretical values. Figure 13d shows that the ripple of the DC bus voltage ΔV

_{PN}is 6.54 V, which is only 1.14% of its theoretical value.

#### 5.2. Simulation of the System under Underload

_{L1}, voltage across capacitors v

_{C1}and v

_{C2}, and DC bus voltage V

_{PN}contain a high level of low frequency ripple, which can cause distortions in the inverter output voltage and current waveforms, leading to a shorter system lifespan.

_{L1}, capacitor voltages v

_{C1}, and v

_{C2}contain only a small amount of low-frequency ripple. This result shows that the suppression method proposed in this paper still has a good suppression effect on the input current on the DC side under the condition of underload. The injected second-frequency harmonic and fourth-frequency harmonic voltage waveforms from the third bridge leg are shown in Figure 18d,e.

#### 5.3. Dynamic Simulation of the System

- (1)
- When transitioning from full load to under load at 0.5 s, the inductor current i
_{L1}of the impedance network stabilizes quickly and maintains good low-frequency ripple suppression capability. - (2)
- The output voltage v
_{o}waveform performs as expected and fluctuates within 1 V, even during the disturbance. The voltage THD remains less than 1% throughout the process, while the output current io smoothly decreases and changes due to the increase in load. - (3)
- The DC bus voltage V
_{PN}remains stable after a short disturbance. - (4)
- As the output pulsating power decreases after the load changes, the power required to buffer the third bridge leg decreases. Consequently, the amplitude of the second and fourth harmonic voltages V
_{2}and V_{4}injected using the third bridge leg decreases, and the amplitude of the filter capacitor voltages v_{o1}and v_{o2}also decreases.

## 6. Conclusions

_{PN}from 70.75 V to 6.54 V, representing a reduction of 90.76%. The second harmonic ripple of the input current is reduced from 18.2% to 4.5%, and the fourth harmonic ripple is reduced from 16.5% to 2.1%. Additionally, the closed-loop control ensures the good dynamic tracking performance of the inverter, while stable control can be achieved in a short time when the load undergoes disturbances, meeting the expected results. As a result, the proposed method only necessitates the inductor and capacitor of the impedance network to handle the switching frequency ripple. This situation significantly reduces the size of the inverter and improves the overall system efficiency. The simulation results validate the accuracy and practicality of the proposed circuit topology. In order to further reduce the volume of the inverter and make it more applicable to relevant fields, the integration of inductors in circuits will be studied in future research.

## Author Contributions

## Funding

## Data Availability Statement

## Conflicts of Interest

## References

- Chen, Y.-C.; Chen, L.-R.; Lai, C.-M.; Lin, Y.-C.; Kuo, T.-J. Development of a DC-Side Direct Current Controlled Active Ripple Filter for Eliminating the Double-Line-Frequency Current Ripple in a Single-Phase DC/AC Conversion System. Energies
**2020**, 13, 4772. [Google Scholar] [CrossRef] - Yao, W.-L.; Tang, Y.; Zhang, X.-B.; Wang, X.F.; Loh, P.-C.; Blaabjerg, F. Power Decoupling Method for Single Phase Differential Buck Converter. In Proceedings of the 2015 9th International Conference on Power Electronics and ECCE Asia (ICPE-ECCE Asia), Seoul, Republic of Korea, 1–5 June 2015; pp. 2395–2402. [Google Scholar]
- Singh, B.; Singh, B.-N.; Chandra, A.; Al-Haddad, K.; Pandey, A.; Kothari, D.-P. A Review of Single-Phase Improved Power Quality AC-DC Converters. IEEE Trans. Ind. Electron.
**2003**, 50, 962–981. [Google Scholar] [CrossRef] - Zhang, M.; Liu, Y.; Li, D.; Cui, X.; Wang, L.; Li, L.; Wang, K. Electrochemical Impedance Spectroscopy: A New Chapter in the Fast and Accurate Estimation of the State of Health for Lithium-Ion Batteries. Energies
**2023**, 16, 1599. [Google Scholar] [CrossRef] - Wang, L.-C.; Xie, L.-C.; Yang, Y.; Zhang, Y.-B.; Wang, K.; Cheng, S.-J. Distributed Online Voltage Control with Fast PV Power Fluctuations and Imperfect Communication. IEEE Trans. Smart Grid
**2023**. [Google Scholar] [CrossRef] - Talha, M.; Raihan, S.; Rahim, N.-A. PV inverter with decoupled active and reactive power control to mitigate grid faults. Renew. Energ.
**2020**, 162, 877–892. [Google Scholar] [CrossRef] - Jiang, J.-H.; Zhang, T.; Chen, D.-L. Analysis, Design, and Implementation of a Differential Power Processing DMPPT with Multiple Buck–Boost Choppers for Photovoltaic Module. IEEE Trans. Power Electron.
**2021**, 36, 10214–10223. [Google Scholar] [CrossRef] - Seth, A.-K.; Singh, M. Second-Order Ripple Minimization in Single-Phase Single-Stage Onboard PEV Charger. IEEE Trans. Transp. Electrif.
**2021**, 7, 1186–1195. [Google Scholar] [CrossRef] - Wen, J.-P.; Zhao, D.; Zhang, C.-W. An overview of electricity powered vehicles: Lithium-ion battery energy storage density and energy conversion efficiency. Renew. Energ.
**2020**, 162, 1629–1648. [Google Scholar] [CrossRef] - Yuan, J.; Yang, Y.; Blaabjerg, F. A Switched Quasi-Z-Source Inverter with Continuous Input Currents. Energies
**2020**, 13, 1390. [Google Scholar] [CrossRef] - Gautam, A.-R.; Fulwani, D.-M.; Makineni, R.-R.; Rathore, A.-K.; Singh, D. Control Strategies and Power Decoupling Topologies to Mitigate 2ω-Ripple in Single-Phase Inverters: A Review and Open Challenges. IEEE Access
**2020**, 8, 147533–147559. [Google Scholar] [CrossRef] - Zhou, Y.-L.; Liu, Y.-L.; Su, M.; Sun, Y. A Single-phase Voltage Source Inverter with Lower-Voltage-Rated Capacitor and Ripple Power Decoupling Function. In Proceedings of the 2020 15th IEEE Conference on Industrial Electronics and Applications (ICIEA), Kristiansand, Norway, 9–13 November 2020; pp. 1944–1948. [Google Scholar]
- Dang, H.; Ruan, X.-B. A Current Reference Compensation Scheme for Second Harmonic Current Compensator. In Proceedings of the 2020 IEEE 9th International Power Electronics and Motion Control Conference (IPEMC2020-ECCE Asia), Nanjing, China, 29 November–2 December 2020; pp. 2364–2367. [Google Scholar]
- Huang, X.-Z.; Ruan, X.-B.; Zhang, L.; Liu, F. Second Harmonic Current Reduction Schemes for DC–DC Converter in Two-Stage PFC Converters. IEEE Trans. Power Electron.
**2022**, 37, 332–343. [Google Scholar] [CrossRef] - Liu, F.; Ruan, X.-B.; Huang, X.-Z.; Qiu, Y.; Jiang. Y.-Y. Control Scheme for Reducing Second Harmonic Current in AC–DC–AC Converter System. IEEE Trans. Power Electron.
**2022**, 37, 2593–2605. [Google Scholar] [CrossRef] - Ellabban, O.; Abu-Rub, H. Z-Source Inverter: Topology Improvements Review. IEEE Ind. Electron. Mag.
**2016**, 10, 6–24. [Google Scholar] [CrossRef] - Liu, Y.-S.; Ge, B.; Abu-Rub, H.; Blaabjerg, F. Single-Phase Z-Source\/Quasi-Z-Source Inverters and Converters: An Overview of Double-Line-Frequency Power-Decoupling Methods and Perspectives. IEEE Ind. Electron. Mag.
**2018**, 12, 6–23. [Google Scholar] [CrossRef] - Vadi, S.; Bayindir, R.; Hossain, E. A Review of Control Methods on Suppression of 2ω Ripple for Single-Phase Quasi-Z-Source Inverter. IEEE Access
**2020**, 8, 42055–42070. [Google Scholar] [CrossRef] - Chub, A.; Vinnikov, D.; Blaabjerg, F.; Peng, F.-Z. A Review of Galvanically Isolated Impedance-Source DC–DC Converters. IEEE Trans. Power Electron.
**2016**, 31, 2808–2828. [Google Scholar] [CrossRef] - Liu, Y.; Ge, B.; Abu-Rub, H.; Sun, D. Comprehensive Modeling of Single-Phase Quasi-Z-Source Photovoltaic Inverter to Investigate Low-Frequency Voltage and Current Ripple. IEEE Trans. Ind. Electron.
**2015**, 62, 4194–4202. [Google Scholar] [CrossRef] - Zhou, Y.; Li, H.-B.; Li, H. A Single-Phase PV Quasi-Z-Source Inverter with Reduced Capacitance Using Modified Modulation and Double-Frequency Ripple Suppression Control. IEEE Trans. Power Electron.
**2016**, 31, 2166–2173. [Google Scholar] [CrossRef] - Cao, X.; Zhong, Q.-C.; Ming, W.-L. Ripple Eliminator to Smooth DC-Bus Voltage and Reduce the Total Capacitance Required. IEEE Trans. Ind. Electron.
**2015**, 62, 2224–2235. [Google Scholar] [CrossRef] - Wang, R.-X.; Wang, F.; Boroyevich, D.; Burgos, R.; Lai, R.-X.; Ning, P.-Q.; Rajashekara, K. A High Power Density Single-Phase PWM Rectifier with Active Ripple Energy Storage. IEEE Trans. Power Electron.
**2011**, 26, 1430–1443. [Google Scholar] [CrossRef] - Sun, Y.; Liu, Y.-L.; Su, M.; Xiong, W.-J.; Yang, J. Review of Active Power Decoupling Topologies in Single-Phase Systems. IEEE Trans. Power Electron.
**2016**, 31, 4778–4794. [Google Scholar] [CrossRef] - Nandi, P.; Adda, R. Integration of Boost-Type Active Power Decoupling Topology with Single-Phase Switched Boost Inverter. IEEE Trans. Power Electron.
**2020**, 35, 11965–11975. [Google Scholar] [CrossRef] - Cai, W.; Liu, B.-Y.; Duan, S.-X.; Jiang, L. An Active Low-Frequency Ripple Control Method Based on the Virtual Capacitor Concept for BIPV Systems. IEEE Trans. Power Electron.
**2014**, 29, 1733–1745. [Google Scholar] [CrossRef] - Li, L.-Z.; Meng, L.-H.; Zhang, S.; Wang, T.-X.; Shu, Z.-L. ZVS Analysis and Control Strategy for Back-Stage of Single-Phase AC-DC-DC Converter with Low-Frequency DC-Link Voltage Ripple. In Proceedings of the 2021 IEEE 16th Conference on Industrial Electronics and Applications (ICIEA), Chengdu, China, 1–4 August 2021; pp. 1001–1006. [Google Scholar]
- Yu, Y.; Zhang, Q.; Liang, B.; Liu, X.; Cui, S. Analysis of A Single-Phase Z-Source Inverter for Battery Discharging in Vehicle to Grid Applications. Energies
**2011**, 4, 2224–2235. [Google Scholar] [CrossRef] - Anderson, J.; Peng, F.-Z. Four Quasi-Z-Source Inverters. In Proceedings of the 2008 IEEE Power Electronics Specialists Conference, Rhodes, Greece, 15–19 June 2008; pp. 2743–2749. [Google Scholar]
- Sun, D.-S.; Ge, B.-M.; Yan, X.-Y.; Bi, D.-Q.; Zhang, H.; Liu, Y.-S.; Abu-Rub, H.; Ben-Brahim, L.; Peng, F.-Z. Modeling, Impedance Design, and Efficiency Analysis of Quasi-Z-Source Module in Cascaded Multilevel Photovoltaic Power System. IEEE Trans. Ind. Electron.
**2014**, 61, 6108–6117. [Google Scholar] [CrossRef] - Zhou, Y.; Liu, L.-M.; Li, H. A High-Performance Photovoltaic Module-Integrated Converter (MIC) Based on Cascaded Quasi-Z-Source Inverters (qZSI) Using eGaN FETs. IEEE Trans. Ind. Electron.
**2013**, 28, 2727–2738. [Google Scholar] [CrossRef] - Ge, B.-M.; Liu, Y.-S.; Abu-Rub, H.; Balog, R.S.; Peng, F.-Z.; McConnell, S.; Li, X. Current Ripple Damping Control to Minimize Impedance Network for Single-Phase Quasi-Z Source Inverter System. IEEE Trans. Ind. Electron.
**2016**, 12, 1043–1054. [Google Scholar] [CrossRef] - Liu, Y.-S.; Ge, B.; Abu-Rub, H.; Sun, H.-X. Hybrid Pulsewidth Modulated Single-Phase Quasi-Z-Source Grid-Tie Photovoltaic Power System. IEEE Trans. Ind. Inform.
**2016**, 12, 621–632. [Google Scholar] [CrossRef]

**Figure 11.**Simulation waveform of disabling third leg: (

**a**) current of inductor L

_{1}, (

**b**) voltage across capacitors C

_{1}, (

**c**) voltage across capacitors C

_{2}, (

**d**) voltage of DC bus, (

**e**) amplified part of DC bus voltage V

_{PN}, and (

**f**) further enlarged view of (

**e**).

**Figure 12.**Fast Fourier Transform (FFT) analysis of output voltage when third bridge leg is disabled.

**Figure 13.**Simulation waveform with third leg enabled: (

**a**) current of inductor L

_{1}, (

**b**) voltage across capacitors C

_{1}, (

**c**) voltage across capacitors C

_{2}, (

**d**) voltage of DC bus, (

**e**) output voltage, (

**f**) voltage across capacitors C

_{f1}and C

_{f2}, (

**g**) current of inductor L

_{f1}and L

_{f2}, (

**h**) second-frequency harmonic voltage injected into third bridge leg, and (

**i**) fourth-frequency harmonic voltage injected into third bridge leg.

**Figure 15.**Comparison of low-frequency current ripple in input current before and after enabling third bridge leg under full load conditions.

**Figure 16.**Simulation waveform of disabling third leg: (

**a**) current of inductor L

_{1}, (

**b**) voltage across capacitors C

_{1}, (

**c**) voltage across capacitors C

_{2}, and (

**d**) voltage of DC bus.

**Figure 18.**Simulation waveform with third leg enabled: (

**a**) current of inductor L

_{1}, (

**b**) voltage across capacitors C

_{1}, (

**c**) voltage across capacitors C

_{2}, (

**d**) second-frequency harmonic voltage injected into third bridge leg, and (

**e**) fourth-frequency harmonic voltage injected into third bridge leg.

**Figure 20.**Comparison of low-frequency current ripple in input current before and after enabling the third bridge leg under condition of underload.

**Figure 21.**Dynamic simulation waveform of transition from full load to under load (0.5 s): (

**a**) current of inductor L

_{1}, (

**b**) voltage across capacitor C

_{1}, (

**c**) voltage across capacitor C

_{2}, (

**d**) voltage of DC bus, (

**e**) output voltage, (

**f**) output current, (

**g**) voltage across capacitors C

_{f1}and C

_{f2}, (

**h**) second-frequency harmonic voltage injected into third bridge leg, and (

**i**) fourth-frequency harmonic voltage injected into third bridge leg.

State | v_{A} | v_{B} | v_{E} |
---|---|---|---|

S_{T} | 0 | 0 | 0 |

S (000) | 0 | 0 | 0 |

S (001) | 0 | 0 | V_{PN} |

S (010) | 0 | V_{PN} | 0 |

S (011) | 0 | V_{PN} | V_{PN} |

S (100) | V_{PN} | 0 | 0 |

S (101) | V_{PN} | 0 | V_{PN} |

S (110) | V_{PN} | V_{PN} | 0 |

S (111) | V_{PN} | V_{PN} | V_{PN} |

Injected Harmonic Voltage Frequency | Input Current nth Harmonic Amplitude/Input Current DC Component | |||||||
---|---|---|---|---|---|---|---|---|

n = 1 | n = 2 | n = 3 | n = 4 | n = 5 | n = 6 | n = 7 | n = 8 | |

2 | 0 | 0 | 0 | 27.92% | 0 | 0 | 0 | 0 |

2, 4 | 0 | 2.35% | 0 | 0 | 0 | 7.06% | 0 | 0.40% |

2, 3, 4 | 0.48% | 2.35% | 101.94% | 0 | 28.67% | 0 | 3.39% | 0.40% |

V_{dc1} ≤ V_{dc2} | V_{dc1} ≥ V_{dc2} | ||||
---|---|---|---|---|---|

V_{dc2} (V) | V_{dc} (V) | V_{PNmin} (V) | V_{dc1} (V) | V_{dc} (V) | V_{PNmin} (V) |

285.8 | 100 | 340.0 | 259.2 | 100 | 340.0 |

295.8 | 110 | 344.1 | 263.7 | 110 | 344.1 |

305.8 | 120 | 349.5 | 269.3 | 120 | 349.5 |

315.8 | 130 | 355.6 | 275.7 | 130 | 355.6 |

325.8 | 140 | 362.5 | 282.7 | 140 | 362.5 |

335.8 | 150 | 369.8 | 290.2 | 150 | 369.8 |

345.8 | 160 | 377.4 | 298.0 | 160 | 377.4 |

355.8 | 170 | 385.4 | 306.1 | 170 | 385.4 |

365.8 | 180 | 393.7 | 314.4 | 180 | 393.7 |

375.8 | 190 | 402.1 | 322.9 | 190 | 402.1 |

385.8 | 200 | 410.7 | 331.6 | 200 | 410.7 |

Parameters | Values | Parameters | Values |
---|---|---|---|

Input voltage V_{i} | 144 V | Output voltage V_{o} | 110 V |

Output voltage frequency f | 50 Hz | Rated power P | 300 W |

Switching frequency f_{s} | 40 kHz | DC bus voltage V_{PN} | 576 V |

Inductors L_{1}, L_{2} | 6 mH | Output-filtering inductors L_{f1}, L_{f2} | 2 mH |

Capacitors C_{1}, C_{2} | 30 μF | Output-filtering capacitors C_{f1}, C_{f2} | 52 μF |

Shoot-through duty cycle D | 0.375 | Modulation index M | 0.27 |

Disclaimer/Publisher’s Note: The statements, opinions and data contained in all publications are solely those of the individual author(s) and contributor(s) and not of MDPI and/or the editor(s). MDPI and/or the editor(s) disclaim responsibility for any injury to people or property resulting from any ideas, methods, instructions or products referred to in the content. |

© 2023 by the authors. Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (https://creativecommons.org/licenses/by/4.0/).

## Share and Cite

**MDPI and ACS Style**

Zhang, C.; Cao, C.; Chen, R.; Jiang, J.
Three-Leg Quasi-Z-Source Inverter with Input Ripple Suppression for Renewable Energy Application. *Energies* **2023**, *16*, 4393.
https://doi.org/10.3390/en16114393

**AMA Style**

Zhang C, Cao C, Chen R, Jiang J.
Three-Leg Quasi-Z-Source Inverter with Input Ripple Suppression for Renewable Energy Application. *Energies*. 2023; 16(11):4393.
https://doi.org/10.3390/en16114393

**Chicago/Turabian Style**

Zhang, Chuanyu, Chuanxu Cao, Ruiqi Chen, and Jiahui Jiang.
2023. "Three-Leg Quasi-Z-Source Inverter with Input Ripple Suppression for Renewable Energy Application" *Energies* 16, no. 11: 4393.
https://doi.org/10.3390/en16114393