# A Simple Mismatch Mitigating Partial Power Processing Converter for Solar PV Modules

^{1}

^{2}

^{3}

^{*}

## Abstract

**:**

## 1. Introduction

_{mod}conducts through all submodules, as depicted in Figure 1b. If a mismatch occurs, the parallel-connected bypass diode turns ON due to the appearance of a negative voltage across the shaded PV submodule, and this shaded PV submodule is bypassed by that ON-state diode, as exemplified in Figure 1c. A current I

_{by}starts to flow through this bypass diode. However, the bypassed submodule causes a voltage mismatch, which results in several power peaks. Hence, the conventional maximum power point tracking (MPPT) algorithms are generally unable to distinguish between local and global maxima in the power-voltage (P-V) curve of PV systems, which also impacts the performance of the whole PV system. Therefore, global maximum power point tracking (GMPPT) algorithms are required to identify the global peak [15,16,17,18,19].

- (a)
- In the first category [37,42], the secondary sides of the central inverter and the DC bus are connected in parallel and they share the same voltage. Furthermore, the switching devices on the secondary side of the module-level DC-DC converter experience high voltage stress, as the DC-bus voltage is the summation of all the PV module output voltages [44].
- (b)
- The second category [37,43], which is known as an isolated bus, is formed by connecting the secondary ports of DC-DC converters in parallel. The selection of DC-bus voltage in PV to an isolated bus DPP converter topology enhances the complexity of the design, as it can be selected independently from the PV module voltage. Also, in (a) and (b), the size and power loss increase due to the presence of more components along with the cost.
- (c)
- Lastly, the third DPP, which is known as the PV-PV DPP converter [42,45] are non-isolated DPP architectures, which can be built cost-effectively through modular combinations. These PV-PV DPP converters draw power from adjacent PV modules. The general structure of PV-PV DPP is shown in Figure 3. Moreover, this topology has one less power converter than the number of PV modules, i.e., one less PV-PV DPP converters is required than the total number of PV modules. The main benefit of this architecture is that its converters are designed according to the voltage characteristics of the PV module rather than that of the main bus voltage. Therefore, the PV-PV DPP converter is independent of bus voltage and need not withstand the high voltage stresses. PV-PV DPP converters are emerging DPP topologies, which are improving continuously in terms of performance, cost, and reliability [42,46].

## 2. Proposed DPP Methodology

#### 2.1. Conventional Mismatch Mitigation Method

^{2}, 750 W/m

^{2}, and 500 W/m

^{2}. The P-V characteristics are obtained under these conditions, which is shown in Figure 4b. As observed in Figure 4b, the output power is reduced due to the bypassing of a submodule, which shows that the shading over a single PV cell can cause a bypassing of the whole PV sub-module, which consists of 12 series-connected PV cells. Additionally, the bypassed submodule has no contribution to the output power and the overall 150 W PV module has lost around 33% of its power due to shading over one PV cell when irradiance over the module is 900 W/m

^{2}. Therefore, it is highly desirable to extract the lost energy. Furthermore, the bypassed submodule becomes a cause of multiple power peaks due to the partial shading. Therefore, the proposed DPP technique is employed to extract the lost power due to the bypass diode method that is highlighted in the subsequent sections.

#### 2.2. Main Features and Qualitative Comparison with Other DPP Converter Topologies

- a better performance under severe mismatching,
- less inductor current ripple,
- simple control circuitry, and
- equalization of the series-connected PV submodule voltages.

#### 2.3. Operational Analysis

_{1~4}) are used during the operation, which is operating at a high frequency to distribute the mismatch charges equally between the submodules. These MOSFET devices are switched at a duty cycle of 50%. During the first cycle, Q

_{1}and Q

_{3}are switched OFF by keeping Q

_{2}and Q

_{4}in an ON-state, as demonstrated in Figure 5b. In the next cycle, the transistors Q

_{1}and Q

_{3}are switched ON while Q

_{2}and Q

_{4}are switched OFF, as shown in Figure 5c. The difference of the currents named as the mismatched current I

_{L}flows across the inductor L. The value of the current I

_{L}is maintained by the inductor L, which is represented in Figure 6a. Furthermore, the mismatch charges between SM1 and SM2 are distributed by the capacitor C in a way that the equalization of voltages is achieved at a submodule level with the proposed topology. Moreover, switching at a higher frequency allows maintaining the constant voltage on capacitor C. Additionally, the capacitor current is also shown in Figure 6b.

_{1}and V

_{2}, respectively. Considering the scenario of partial shading at SM1, the switching sequence and the associated equivalent circuit of the DPP converter are presented in Figure 5b,c. In the case when Q

_{2}and Q

_{4}are switched ON (Q

_{1}and Q

_{3}OFF), corresponding to Figure 5b, the differential current I

_{L}passes and charges the inductor L and a capacitor C. The voltage across the capacitor V

_{C}and the current I

_{2}flowing across SM2 can be mathematically represented by Equations (1) and (2) as below:

_{L}is the mismatch current flowing across the inductor L, V

_{2}is the voltage across the SM2, L is the value of the inductance, V

_{C}is the voltage across the switched-capacitor, and I

_{1}is the current flowing across SM1.

_{1}and Q

_{3}are turned ON while keeping Q

_{2}and Q

_{4}in an OFF-state. In this scenario, the capacitor voltage V

_{C}and the current passing through SM2 can be represented by (3) and (4)

_{1}is the voltage across the SM1.

_{L}is distributed equally into I

_{S}

_{1}and I

_{S}

_{2}(currents flowing through Q

_{1}, Q

_{2}, Q

_{3}, and Q

_{4}). The current following through the output and switches can be found by using (5) and (6).

_{out}is the current flowing towards the output load.

#### 2.4. Component Design

_{L}. A high RMS current ripple results in a high-frequency RMS flux density and hence substantial core losses [57,58]. Furthermore, a high RMS current ripple (should be less than 5%) causes a high-frequency copper loss due to proximity and the skin effect. Therefore, the inductor current ripple ΔI

_{L}is a reasonable performance indicator for the design of the inductor, which should be as small as possible. On the other hand, the capacitance value should be large enough to limit the DC voltage ripple ΔV

_{C}to less than 5%. The inductance and capacitance can be calculated as

_{sw}is the switching frequency.

#### 2.5. Power Loss Analysis

_{on}) for the switches in the proposed topology can be calculated by

_{on}is the ON-state resistance of the MOSFETs and I

_{Si(RMS)}(i = 1 or 2) is the RMS value of mismatch current flowing across the switches while the switch is in an ON-state. In each cycle, two MOSFETs are ON. Therefore, the ON-state losses are multiplied by a factor of 2.

_{sw}reduces the capacitor and inductor sizes. However, it enhances the switching losses [40]. At any switching instance, since two switches are involved, switching power losses (P

_{swloss}) can be estimated as (10)

_{Si(tsw_on)}is the instantaneous MOSFET current during the turn-ON, i

_{Si(tsw_off)}is the current during the turn-OFF, and t

_{on}and t

_{off}are the rise and fall time of the switch, which are mentioned in the datasheet.

_{L}always flows through L and C. Firstly, power losses of the inductor can be determined with the inductor’s current (I

_{L(RMS)}) and the inductor copper resistance R

_{L}at f

_{sw}. For the inductor L, the copper losses (P

_{L_loss}) can be computed as

_{C_loss}) can be calculated by

_{sw}) is the effective series resistance of C at f

_{sw}.

_{t}is the total power loss.

## 3. Simulation Results

_{1}for SM1 and E

_{2}for SM2. The rating of the used PV module is shown in Table 1. The converter is operating at a 50% duty cycle and the operating frequency is 100 kHz. The value of inductor L and a capacitor C are 100 µH and 50 µF, respectively by taking a consideration of the inductor current ripple ΔI

_{L}and capacitor voltage ripple ΔV

_{C}to be less than 5% according to (7) and (8).

- Scenario 1—No shading

_{L}between SM1 and SM2 is negligible, which can be seen from Figure 7b.

- Scenario 2—SM1 is shaded

^{2}, while it remains constant over SM2 to 1000 W/m

^{2}during this scenario. The simulation results are given in Figure 7b. In Figure 7b, the mismatch current I

_{L}is passing through the inductor. An average mismatch current is around 1.4 A.

- Scenario 3—SM2 is shaded

^{2}while it remains constant over SM1 to 1000 W/m

^{2}. The simulation results are shown in Figure 7b.

_{out}) and PV modules (I

_{1}and I

_{2}) in Figure 8a, inductor L (I

_{L}) in Figure 8b, and MOSFET switches (I

_{S}

_{1}and I

_{S}

_{2}) in Figure 8c,d during both operational states. For further assessment and evaluation, the performance of the SCL methodology in Figure 5 is compared with the conventional bypass diode method in Figure 1. For this purpose, several cases are developed and performed in PSIM, which are given in Table 2.

_{1}) over SM1 (1000 W/m

^{2}, 750 W/m

^{2}, 500 W/m

^{2}, and 250 W/m

^{2}) while keeping the irradiance (E

_{2}) over SM2 constant (i.e., 1000 W/m

^{2}) in Figure 5. In Figure 9, under these mismatch conditions, the proposed SCL-based DPP topology has achieved only one power peak while there are multiple peaks by using the conventional bypass diode method, as shown in Figure 9b–d.

## 4. Experimental Results and Discussion

#### 4.1. Prototype and Experimental Setup

_{L}and capacitor voltage ripple ΔV

_{C}of less than 5% according to (7) and (8). Moreover, the proposed DPP converter only has to process the mismatched power. Therefore, the power rating requirement for the proposed DPP converter is lower. Hence, the low power components allow the use of small and fast-switching MOSFET transistors, which can operate at high switching frequencies. The inductance, capacitance, and switching frequency values were determined earlier. More importantly, this prototype is designed to prove the concept, and is not for practical use. Therefore, the components used during the testing should be replaced by the more efficient and small-size components for practical implementation.

#### 4.2. Results

_{L}is shown in Figure 12a. It can be seen from Figure 12a that the mismatch current during this test condition is zero. During Test 2, PV1 is producing more power than PV2. The mismatch current during this case is shown in Figure 12b. Lastly, in Test 3, PV2 is producing more power than PV1, while the difference of mismatch current I

_{L}between the two series-connected PV modules is shown in Figure 12c.

_{on}) and switching power losses (P

_{swloss}) are 109.83 mW and 71.69 mW, respectively. Moreover, the calculated losses across the capacitor (P

_{C_loss}) and inductor (P

_{L_loss}) are 8.3 mW and 300 mW, correspondingly. The overall calculated efficiency (ƞ

_{c}) is 99.28% and the measured efficiency from the simulated results under similar conditions is 98.66%. Additionally, the calculated and simulated efficiencies are only considered because this prototype is designed only to prove the concept, not for practical use. Therefore, the components used during the testing should be replaced by the more efficient and small-size components for practical implementation for better performance and efficiency. As a continuation, it can be seen from Figure 14 that the losses associated with the inductor are the highest up to 61% because the copper loss is the most dominant material showing major losses at higher frequencies. Also, the ON-state switch losses are lower due to the low R

_{on}of the selected MOSFET.

## 5. Conclusions

## Author Contributions

## Funding

## Institutional Review Board Statement

## Informed Consent Statement

## Data Availability Statement

## Conflicts of Interest

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**Figure 1.**A PV module having three series-connected PV submodules (SM1, SM2, and SM3): (

**a**) General schematic diagram, (

**b**) A schematic diagram when there is no mismatch (no shade), (

**c**) Schematic diagram when SM1 is shaded. Here, D

_{1}, D

_{2}, and D

_{3}are parallel-connected bypass diodes. I

_{mod}and I

_{by}are the submodule and bypassing currents, respectively.

**Figure 4.**Experimental evaluation of the mismatch effect on a solar PV module (Solvis: SV36-150) containing three submodules with bypass diodes: (

**a**) SPI-SUN 5600 SLP solar sun simulator, (

**b**) Power-voltage (P-V) characteristics when one of the PV cells is shaded from the three submodules and overall irradiance levels are 900 W/m

^{2}, 750 W/m

^{2}, and 500 W/m

^{2}.

**Figure 5.**Proposed DPP topology (

**a**) General circuit, (

**b**) Energizing state/mode 1: power flow when SM2 is producing more than SM1, (

**c**) De-energizing state/mode 2: power flow when SM2 is producing more than SM1. Here, L and C are switched-inductor and switched-capacitor used for the mismatch energy processing. I

_{S}

_{1}and I

_{S}

_{2}are the currents flowing through the switches Q

_{1}, Q

_{2}, Q

_{3}, and Q

_{4}.

**Figure 6.**Basic operational waveforms during mismatch: (

**a**) Current flowing through the inductor L, (

**b**) Current flowing through the capacitor C, where T is the switching period.

**Figure 7.**Mismatch scenarios and results: (

**a**) Mismatch scenarios (scenario 1: when SM1 and SM2 is producing Scheme 2. when SM1 producing lower than SM2, and scenario 3: when SM2 is producing lower than SM1), (

**b**) Mismatch current (I

_{L}) passing through the inductor L under various mismatch scenarios in Figure 7a.

**Figure 8.**Simulated results under scenario 2 (SM1 is shaded) for the proposed SCL-based DPP topology: (

**a**) Output current and submodules current, (

**b**) mismatch current (I

_{L}) passing through the inductor L (

**c**) current passing through Q

_{1}and Q

_{3}, (

**d**) current passing through Q

_{2}and Q

_{4}.

**Figure 9.**P-V characteristics for the proposed topology under mismatch cases given in Table 2 for proposed DPP and traditional bypass diode technique (

**a**) Case 1, (

**b**) Case 2, (

**c**) Case 3, (

**d**) Case 4.

**Figure 10.**Output power for traditional bypass diode and proposed DPP technique for various mismatch cases or solar irradiance profiles shown in Table 2.

**Figure 12.**Experimental results showing mismatch current (I

_{L}) for various test conditions in Table 5 for SCL-based DPP topology. (

**a**) Test 1 (

**b**) Test 2 and (

**c**) Test 3.

**Figure 13.**Experimentally achieved P-V characteristics for the proposed technique when SM2 in Figure 5 is producing 90%, 50%, and 25% of SM1 (30 W).

**Figure 14.**Theoretical analysis of power loss distribution among various components present in the proposed SCL-based DPP topology while one of the PV modules is half-shaded in Figure 5.

Average Maximum Power (P_{max}) | 45 W |
---|---|

Maximum Voltage (V_{mp}) | 17.50 V |

Maximum Current (I_{mp}) | 2.58 A |

Open-Circuit Voltage (V_{oc}) | 22 V |

Short-Circuit Current (I_{sc}) | 2.86 A |

Cases | Case 1 | Case 2 | Case 3 | Case 4 |
---|---|---|---|---|

E_{1} (W/m^{2}) | 1000 | 750 | 500 | 250 |

E_{2} (W/m^{2}) | 1000 | 1000 | 1000 | 1000 |

**Table 3.**Voltages across PV submodules for proposed SCL-based DPP topology for the mismatch cases in Table 2.

Cases | V_{1} | V_{2} |
---|---|---|

Case 1 | 17.50 | 17.50 |

Case 2 | 17.21 | 17.23 |

Case 3 | 16.89 | 16.94 |

Case 4 | 16.61 | 16.68 |

Components | Value |
---|---|

MOSFET | IRFZ44VPbF, R_{on} = 16.5 mΩ |

Inductance (L) | 100 µH, R_{L} = 180 mΩ |

Capacitance (C) | Ceramic capacitor, 10 µF × 5, 1 mΩ |

Gate driver | TC4428M |

DSP | Texas Instrumentation TI F28379D |

Mismatch Conditions | I_{1}(A), V_{1}(V) | I_{2}(A), V_{2}(V) |
---|---|---|

Test 1 | 2, 15 | 2, 15 |

Test 2 | 2, 15 | 1.56, 14.8 |

Test 3 | 1.41, 14.7 | 2, 15 |

**Table 6.**Theoretical losses for the SCL-based proposed technique across each component when one PV module is half shaded.

Components | Switch P _{on} | Switch P _{swloss} | Capacitor P _{C_loss} | Inductor P _{L_loss} |
---|---|---|---|---|

Calculated loss (mW) | 109.83 | 71.69 | 8.3 | 300 |

Calculated efficiency (ƞ) | 67.5/(67.5 + 0.489) = 99.28% | |||

Simulated efficiency (ƞ) | (66.5 × 100)/67.4 = 98.66% |

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## Share and Cite

**MDPI and ACS Style**

Niazi, K.A.K.; Yang, Y.; Kerekes, T.; Sera, D.
A Simple Mismatch Mitigating Partial Power Processing Converter for Solar PV Modules. *Energies* **2021**, *14*, 2308.
https://doi.org/10.3390/en14082308

**AMA Style**

Niazi KAK, Yang Y, Kerekes T, Sera D.
A Simple Mismatch Mitigating Partial Power Processing Converter for Solar PV Modules. *Energies*. 2021; 14(8):2308.
https://doi.org/10.3390/en14082308

**Chicago/Turabian Style**

Niazi, Kamran Ali Khan, Yongheng Yang, Tamas Kerekes, and Dezso Sera.
2021. "A Simple Mismatch Mitigating Partial Power Processing Converter for Solar PV Modules" *Energies* 14, no. 8: 2308.
https://doi.org/10.3390/en14082308