# A Novel Concept for Three-Phase Cascaded Multilevel Inverter Topologies

^{*}

## Abstract

**:**

## 1. Introduction

## 2. Proposed Concept of 3-Phase CMLI

_{C}’ of a magnitude greater than the summation of the input voltage supplies in the cascaded stage.

_{a3}, S

_{a4}), or (S

_{b3}, S

_{b4}), or (S

_{c3}, S

_{c4}) within the CTPTLI at different PG cells are responsible for generating V

_{C}and zero voltage levels in the output voltage waveform at the output nodes A, B, C. For any PG cell, the PD-switch is turned off while the two switches within the CTPTLI operate to generate V

_{C}and zero voltage level. The pair switches in the CTPTLI and the BD switch always function in a toggle mode. As mentioned above, any existing CMLI topology can be utilized as a cascaded stage and, hence, no significant change is required in the switching logic for existing CMLI topology when used as a cascaded stage to generate different voltage levels in the proposed topology.

_{C}and 0 in the pole voltage V

_{Ag}which are achieved by toggle operation of switches S

_{a3}and S

_{a4}. Figure 2b shows the conduction path of the inverter when it generates intermediate levels between V

_{C}and 0 in the pole voltage. Figure 2c shows the final pole voltage.

_{Ag}, V

_{Bg}, V

_{Cg}are the pole voltages, then the line voltage, V

_{AB}, V

_{BC}, V

_{CA}can be derived as below,

## 3. Proposed CMLI Using H-Bridge Topology as Cascaded Stage

_{k1}, G

_{k2}, G

_{k3}, G

_{k4}) and a dc-power supply (V

_{k}) as depicted in Figure 4b. Any CHB cell is able to produce three different voltage levels (V

_{k}, 0, −V

_{k}) in the output voltage, V

_{out}. Table A1 in the Appendix A shows the switching logic to achieve the aforementioned three output voltages.

^{n}). The Trinary ratio format (1:3: … :3

^{n}) has been also proposed for CHB MLI asymmetric structure [38]. The new proposed three-phase CMLI concept in this paper can adopt both symmetric and asymmetric structure of the CHB MLI in the cascaded stage.

_{C}should be greater than the summation of the connected voltage supplies in the cascaded stage. If V

_{1}, V

_{2}, …, V

_{3}are the input voltages for n-number of cells in the cascaded stage, then the following respective equations for symmetric, binary-related and trinary-related input supplies can be written,

_{C}can be calculated from,

_{1}= V

_{2}= V

_{3}= v; V

_{C}= 4v. With the contribution of CTPTLI and CHB cells along with the BD-switches, pole voltages, V

_{Ag}, V

_{Bg}, V

_{Cg}are produced. Only the CTPTLI switches operate to generate the voltage levels, V

_{C}and 0 as shown in Figure 5a,e, respectively. The other voltage levels, (V

_{1}+ V

_{2}+ V

_{3}), (V

_{1}+ V

_{2}), V

_{1}between 0 and V

_{C}levels are produced using different switching logics among the CHB cells, when the BD-switches are turned on. Figure 5e shows the pole voltage output, V

_{Ag}, which can be obtained by the above mentioned switching operation.

_{Ag}; the other two pole voltages follow the same switching logics with 120° phase shift among the PG-cells. The switching function for each phase arm lasts for 120° phase angle.

## 4. Implementation of the Proposed MLI

_{P}is the number of levels in the pole voltages.

_{P}= 2 and the following hexagons is for N

_{P}= 3, N

_{P}= 4, and N

_{P}= 5; respectively. According to Figure 5, the proposed topology generates N

_{P}= 5 in the pole voltages. Hence, the most upper hexagon in Figure 6 is appropriate for getting 24 switching states to generate five voltage levels, 4v, 3v, 2v, v, 0 in the pole voltages.

_{a}, S

_{b}, S

_{c}for three-phase voltage generation. The pole voltages, V

_{Ag}, V

_{Bg}, V

_{Cg}are taken as reference to achieve the three switching vectors in each switching state at any instant of time [39]. In general, the switching angles, φ for each of the switching states are equal and can be calculated from,

## 5. Results and Discussions

_{1}= V

_{2}= V

_{3}= v = 70 V and V

_{C}= 4v = 280 V. Inductive 3-phase load (Z = 55 + j 37.68 Ω/phase) is considered for testing the inverter performance.

_{Jg}and pole voltages, V

_{Ag}, V

_{Bg}, V

_{Cg}, respectively. As shown in the figure, the pole voltages comprise five levels (280 V, 210 V, 140 V, 70 V, 0) while V

_{Jg}comprises three levels (210 V, 140 V, 70 V). Figure 8b,c show the load voltages, V

_{AN}, V

_{BN}, V

_{CN}, and their THD, respectively. The relation between the pole voltages V

_{Ag}, V

_{Bg}, V

_{Cg}, and load voltages can be expressed by,

_{AB}, V

_{BC}, V

_{CA}shown in Figure 9a comprise nine levels (280 V, 210 V, 140 V, 70 V, 0 V, −70 V, −140 V, −210 V, −280 V).

_{AN}, I

_{BN}, I

_{CN}. It is worth mentioning that no harmonic filter was used in the implemented hardware setup. The total harmonic distortion (THD) of the unfiltered line voltage and line current are 9.27% and 2.09%; respectively as shown in Figure 9c,d, respectively. The THD of the line current and voltage must be less than 5%, to comply with the IEEE standard [41]. While the current THD complies with the mentioned standard, voltage THD is more than 5% in the implemented 9-level CMLI topology. Voltage THD can be reduced by increasing the number of levels in the output voltage.

_{1}, V

_{2}, V

_{3}are set to 20 V, 60 V, 180 V; respectively and hence the magnitude of V

_{C}is 280 V.

_{P}= 15) in the pole voltage and 29-levels in the line voltage. Hence, it needs 84-switching states to generate three-phase output voltages according to (5). Table A4 in the Appendix A shows the switching logics for generating 15 levels in the pole voltage. The junction voltage, and line voltage, V

_{AB}are shown in Figure 10a. Figure 10b shows 29-level three-phase line voltages on the same plot. The THD of the unfiltered 29-level line voltages is nearly 5% as shown in Figure 10c.

_{11}= V

_{21}= V

_{31}= V

_{21}= V

_{22}= V

_{23}= V’

_{0}= 40 V and V

_{C}= 280 V. The cascaded stage in Figure 11b is arranged in a similar pattern by imitating the single-phase structure for three-phase conversion.

_{11}= V

_{21}= V

_{31}= V

_{21}= V

_{22}= V

_{23}= V’

_{0}= 40 V and V

_{C}= 280 V. The cascaded stage in Figure 11b is arranged in a similar pattern by imitating the single-phase structure for three-phase conversion.

_{Jg}, pole voltages and line voltage, V

_{AB}of the extended three-phase inverter. Figure 12b shows the three-phase 17-level line voltages on the same plot.

## 6. Semiconductor Losses and Inverter Efficiency

_{out}, the inverter efficiency (ƞ) can be calculated from:

_{C}and I

_{line}are the input voltage to the CTPTLI and output line current, respectively.

_{T}= 1.8 V, R

_{T}= 0.10, V

_{D}= 1.2 V, R

_{D}= 0.1, β = 1, t

_{on}= t

_{off}= 1 µs. where, the on-state voltage drop of the transistor and diode are expressed by V

_{T}and V

_{D}, respectively. The on-state resistances of the transistor and diode, are given by R

_{T}and R

_{D}, respectively. The transistor amplification factor and ON-OFF time is expressed by ‘β’, t

_{on}and t

_{off}, respectively.

_{total_loss}= 2.9067 watt with 1.3076 watt losses associated in the cascaded stage and 1.5991 watt in the PG stage. For a connected load of 0.82 lagging power factor (PF) and by using (15), the output power is 98.64 watt which gives an overall efficiency of about 97%.

## 7. Comparison with Other Topologies

## 8. Conclusions

## Acknowledgments

## Author Contributions

## Conflicts of Interest

## Appendix A

V_{out} | Turn on Switches |

V_{k} | G_{k1}, G_{k3} |

0 | G_{k1}, G_{k4} |

−V_{k} | G_{k2}, G_{k4} |

Switching Vector, S_{a}/S_{b}/S_{c} | Switching Logic |
---|---|

4 | Figure 5a |

3 | Figure 5b |

2 | Figure 5c |

1 | Figure 5d |

0 | Figure 5e |

Input DC Source Voltage in CHB Stage (V_{1}, V_{2}, V_{3}) | 70 V Each |

Input DC source voltage in PGS (V_{C}) | 280 V |

Switching frequency | 50 Hz |

Magnitude of line voltages | 280 V (Peak) |

Load power factor | 0.82 |

Tested power of the prototype | 523 Watt |

Number of levels in the peak–peak line voltages | 9 |

Switching Vector, S_{a} | Pole Voltage | Switching Logic | ||
---|---|---|---|---|

14 | V_{C} | 280 V | Figure 5a | |

13 | v + 3v + 9v | 260 V | V_{1} + V_{2} + V_{3} | BD-Switch-A ON |

12 | 0 + 3v + 9v | 240 V | 0 + V_{2} + V_{3} | |

11 | −v + 3v + 9v | 220 V | −V_{1} + V_{2} + V_{3} | |

10 | v + 0 + 9v | 200 V | V_{1} + 0 + V_{3} | |

9 | 0 + 0 + 9v | 180 V | 0 + 0 + V_{3} | |

8 | −v + 0 + 9v | 160 V | −V_{1} + 0 + V_{3} | |

7 | v − 3v + 9v | 140 V | V_{1} − V_{2} + V_{3} | |

6 | 0 − 3v + 9v | 120 V | 0 − V_{2} + V_{3} | |

5 | −v − 3v + 9v | 100 V | −V_{1} − V_{2} + V_{3} | |

4 | v + 3v + 0 | 80 V | V_{1} + V_{2} + 0 | |

3 | 0 + 3v + 0 | 60 V | 0 + V_{2} + 0 | |

2 | −v + 3v + 0 | 40 V | −V_{1} + V_{2} + 0 | |

1 | v + 0 + 0 | 20 V | V_{1} + 0 + 0 | |

0 | 0 | 0 | Figure 5e |

**Table A5.**Switching logic in the cascaded stage and PG-stage for generating 9 levels in the pole voltage, V

_{Ag}.

Switching Vector | Pole Voltage (V) | Switching Logic | |
---|---|---|---|

0 | 0 | Figure 5a | |

1 | 20 | S′_{1}, S_{51}, S_{52} | BD-Switch-A Turn ON |

2 | 40 | S′_{2}, S_{11}, S_{31}, S_{41}, S_{52} | |

3 | 60 | S′_{1}, S_{11}, S_{31}, S_{41}, S_{52} | |

4 | 80 | S′_{1}, S_{11}, S_{21}, S_{31}, S_{52} | |

5 | 100 | S′_{2}, S_{11}, S_{21}, S_{31}, S_{12}, S_{32}, S_{42} | |

6 | 120 | S′_{2}, S_{11}, S_{21}, S_{31}, S_{12}, S_{22}, S_{32} | |

7 | 140 | S′_{1}, S_{11}, S_{21}, S_{31}, S_{12}, S_{22}, S_{32} | |

8 | 160 | Figure 5e |

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**Figure 1.**Block diagrams: (

**a**) level and polarity generators-based cascaded multilevel inverter (CMLI) topology; (

**b**) CMLI topology with no polarity generator; (

**c**) 3-phase CMLI topology; (

**d**) proposed 3-phase CMLI; (

**e**) Circuital model of the PG-stage. Reprint with permission [4261051118814]; 2018, IEEE.

**Figure 2.**Simplified structure of the proposed CMLI, (

**a**) generation of maximum and zero voltage levels; (

**b**) intermediate level generation; (

**c**) pole voltage waveform. Reprint with permission [4261051118814]; 2018, IEEE.

**Figure 4.**Proposed three-phase CMLI (

**a**) CHB cells are considered as cascaded stage; (

**b**) a standard CHB cell. Reprint with permission [4261051118814]; 2018, IEEE.

**Figure 5.**Different switching logics for generating four levels in the pole voltages: (

**a**) level 3v; (

**b**) Level 2v; (

**c**) Level v; (

**d**) Level 0; (

**e**) Complete cycle of the pole voltage. Reprint with permission [4261051118814]; 2018, IEEE.

**Figure 6.**Generalized switching states for generating different number of levels in the pole voltage. Reprint with permission [4261051118814]; 2018, IEEE.

**Figure 7.**Experimental prototype hardware model. Reprint with permission [4261051118814]; 2018, IEEE.

**Figure 8.**Experimental results of (

**a**) Junction voltage, and Pole voltages when the CHB-cells are fed by symmetric dc-power supplies; (

**b**) load voltage; (

**c**) load voltage harmonics.

**Figure 9.**Experimental results, (

**a**) line voltages; (

**b**) line currents; (

**c**) THD of the line voltage; (

**d**) THD of the line current, when CHB cells are fed by Symmetric dc power supplies.

**Figure 10.**Experimental results, (

**a**) Junction voltage, pole voltages (V

_{Ag}, V

_{Bg}), line voltage (V

_{AB}); (

**b**) 29-level 3-phase line voltages; (

**c**) THD of the line voltage, when CHB cells are fed by trinary related dc power supplies. Reprint with permission [4261051118814]; 2018, IEEE.

**Figure 11.**Three-phase conversion of a single phase topology (

**a**) existing single phase topology proposed in [12]; (

**b**) three-phase conversion of existing topology according to the concept proposed in this paper.

**Figure 12.**Experimental results, (

**a**) Junction voltage, pole voltages (V

_{Ag}, V

_{Bg}), line voltages (V

_{AB}); (

**b**) 17-level three-phase line voltages.

**Table 1.**Comparison between three-phase conversion of a single-phase structure using conventional methods and proposed concept in this paper.

Topology | Single Phase Structure | Conventional 3 Phase Conversion | This Paper Proposed Concept | ||||||
---|---|---|---|---|---|---|---|---|---|

Line Voltage Levels | Switches | DC-Supplies | Line Voltage Levels | Switches | DC-Supplies | Line Voltage Levels | Switches | DC-Supplies | |

Non-isolated inverter topology [9] | 15 | 12 | 7 | 15 | 36 | 21 | 17 | 24 | 8 |

DC-link half-bridge cascaded inverter [21] | 13 | 12 | 6 | 13 | 36 | 18 | 15 | 24 | 7 |

**Table 2.**Comparison among conventional three-phase CHB topologies and the proposed three-phase cascaded MLI for different asymmetric input voltage arrangements.

Category | Binary Related Two CHB Cell Topology [35] | Trinary Related Three CHB Cell Topology [42] | Trinary Related Four CHB Cell Topology [38] | |||
---|---|---|---|---|---|---|

Existing 3-Phase | Proposed New Concept | Existing 3-Phase | Proposed New Concept | Existing 3-Phase | Proposed New Concept | |

No of levels in line voltage | 7 | 9 | 27 | 29 | 81 | 83 |

No of switches | 24 | 20 | 36 | 24 | 48 | 28 |

No of diodes | 24 | 20 | 36 | 24 | 48 | 28 |

No of gate driver | 24 | 20 | 36 | 24 | 48 | 28 |

No of dc supplies | 6 | 3 | 9 | 4 | 12 | 5 |

© 2018 by the authors. Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (http://creativecommons.org/licenses/by/4.0/).

## Share and Cite

**MDPI and ACS Style**

Hasan, M.M.; Abu-Siada, A.; Islam, S.M.; Muyeen, S.M.
A Novel Concept for Three-Phase Cascaded Multilevel Inverter Topologies. *Energies* **2018**, *11*, 268.
https://doi.org/10.3390/en11020268

**AMA Style**

Hasan MM, Abu-Siada A, Islam SM, Muyeen SM.
A Novel Concept for Three-Phase Cascaded Multilevel Inverter Topologies. *Energies*. 2018; 11(2):268.
https://doi.org/10.3390/en11020268

**Chicago/Turabian Style**

Hasan, Md Mubashwar, A. Abu-Siada, Syed M. Islam, and S. M. Muyeen.
2018. "A Novel Concept for Three-Phase Cascaded Multilevel Inverter Topologies" *Energies* 11, no. 2: 268.
https://doi.org/10.3390/en11020268